1 /* 2 Copyright (c) 2002, Thomas Kurschel 3 4 5 Part of Radeon accelerant 6 7 Interface between kernel driver and accelerant 8 */ 9 10 11 #ifndef _RADEON_INTERFACE_H 12 #define _RADEON_INTERFACE_H 13 14 #include <Accelerant.h> 15 #include <Drivers.h> 16 #include <PCI.h> 17 #include <OS.h> 18 #include "video_overlay.h" 19 #include "benaphore.h" 20 #include "ddc.h" 21 22 // magic code for ioctls 23 // changed from TKRA to TKR1 for RADEON_WAITFORFIFO ioctl 24 // changed from TKRA to TKR2 for VIP FIFO ioctls 25 #define RADEON_PRIVATE_DATA_MAGIC 'TKR2' 26 27 #define MAX_RADEON_DEVICE_NAME_LENGTH MAXPATHLEN 28 29 // list ioctls 30 enum { 31 RADEON_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1, 32 33 RADEON_DEVICE_NAME, 34 RADEON_GET_LOG_SIZE, 35 RADEON_GET_LOG_DATA, 36 RADEON_ALLOC_MEM, 37 RADEON_FREE_MEM, 38 39 RADEON_WAITFORIDLE, 40 RADEON_WAITFORFIFO, 41 RADEON_RESETENGINE, 42 RADEON_VIPREAD, 43 RADEON_VIPWRITE, 44 RADEON_VIPFIFOREAD, 45 RADEON_VIPFIFOWRITE, 46 RADEON_FINDVIPDEVICE, 47 RADEON_VIPRESET, 48 49 RADEON_WAIT_FOR_CAP_IRQ, 50 RADEON_DMACOPY, 51 }; 52 53 54 // number of indirect buffers 55 // see CP.c for this magic number 56 #define NUM_INDIRECT_BUFFERS 253 57 // size of an indirect buffer in dwords; 58 // as hardware wants buffers to be 4k aligned and as we store all 59 // buffers in one chunk, the size per buffer in bytes must be a multiple of 4k 60 #define INDIRECT_BUFFER_SIZE (4096/4) 61 62 typedef struct { 63 uint32 loginfo; 64 uint32 logflow; 65 uint32 logerror; 66 bool switchhead; 67 bool force_lcd; 68 bool dynamic_clocks; // power saving / management for mobility chips 69 bool force_pci; 70 bool unhide_fastwrites; 71 bool force_acc_dma; // one or the other 72 bool force_acc_mmio; // one or the other 73 bool acc_writeback; 74 } radeon_settings; 75 76 // type of memory 77 typedef enum { 78 mt_local, // local graphics memory 79 mt_PCI, // PCI memory (read: fully cachable) 80 mt_AGP, // AGP memory (read: not cachable; currently not supported) 81 mt_nonlocal, // non-local graphics memory (alias to one of the 82 // previously defined types, see si->nonlocal_type) 83 84 mt_last = mt_nonlocal 85 } memory_type_e; 86 87 // list of multi-monitor modes 88 typedef enum { 89 mm_none, // use one display only 90 mm_combine, // combine displays to larger workspace 91 mm_clone, // clone workspace, all displays show the 92 // same but have independant timing 93 mm_mirror // mirror heads (as used by Laptop) - not implemented yet 94 } multi_mode_e; 95 96 97 // displays devices; 98 // this must be a bit field as multiple devices may be connected to one CRTC 99 typedef enum { 100 dd_none = 0, 101 dd_tv_crt = 1, // CRT on TV-DAC, i.e. on DVI port 102 dd_crt = 2, // CRT on CRT-DAC, i.e. VGA port 103 dd_lvds = 4, // laptop flap panel 104 dd_dvi = 8, // DVI on primary port (i.e. standard DVI connector) 105 dd_ctv = 16, // composite TV on TV-DAC 106 dd_stv = 32, // S-Video out on TV-DAC 107 108 // the following connectors/devices are not supported 109 dd_dvi_ext = 64 // external DVI (only provided by few models) 110 } display_device_e; 111 112 typedef enum 113 { 114 ddc_none_detected, 115 ddc_monid, 116 ddc_dvi, 117 ddc_vga, 118 ddc_crt2 119 } radeon_ddc_type; 120 121 typedef enum 122 { 123 mt_unknown = -1, 124 mt_none = 0, 125 mt_crt = 1, 126 mt_lcd = 2, 127 mt_dfp = 3, 128 mt_ctv = 4, 129 mt_stv = 5 130 } radeon_monitor_type; 131 132 typedef enum 133 { 134 connector_none, 135 connector_proprietary, 136 connector_crt, 137 connector_dvi_i, 138 connector_dvi_d, 139 connector_ctv, 140 connector_stv, 141 connector_unsupported 142 } radeon_connector_type; 143 144 typedef enum 145 { 146 connector_none_atom, 147 connector_vga_atom, 148 connector_dvi_i_atom, 149 connector_dvi_d_atom, 150 connector_dvi_a_atom, 151 connector_stv_atom, 152 connector_ctv_atom, 153 connector_lvds_atom, 154 connector_digital_atom, 155 connector_unsupported_atom 156 } radeon_connector_type_atom; 157 158 typedef enum 159 { 160 dac_unknown = -1, 161 dac_primary = 0, 162 dac_tvdac = 1 163 } radeon_dac_type; 164 165 typedef enum 166 { 167 tmds_unknown = -1, 168 tmds_int = 0, 169 tmds_ext = 1 170 } radeon_tmds_type; 171 172 typedef struct 173 { 174 radeon_ddc_type ddc_type; 175 radeon_dac_type dac_type; 176 radeon_tmds_type tmds_type; 177 radeon_connector_type connector_type; 178 radeon_monitor_type mon_type; 179 edid1_info edid; 180 bool edid_valid; 181 } radeon_connector; 182 183 typedef struct 184 { 185 bool has_secondary; 186 187 /* 188 * The next two are used to make sure CRTC2 is restored before CRTC_EXT, 189 * otherwise it could lead to blank screens. 190 */ 191 bool is_secondary_restored; 192 bool restore_primary; 193 194 int mon_type1; 195 int mon_type2; 196 197 bool reversed_DAC; /* TVDAC used as primary dac */ 198 bool reversed_TMDS; /* DDC_DVI is used for external TMDS */ 199 200 radeon_connector port_info[2]; 201 } disp_entity, *ptr_disp_entity; 202 203 204 // type of ASIC 205 typedef enum { 206 rt_r100, // original Radeon 207 rt_rv100, // original VE version 208 rt_rs100, // IGP 320M 209 rt_rv200, // Radeon 7500 210 rt_rs200, // IGP 330M/340M/350M 211 rt_r200, // Radeon 8500/9100 212 rt_rv250, // Radeon 9000 213 rt_rs300, // IGP rs300 214 rt_rv280, // Radeon 9200 215 // from here on, r300 and up must be located as ATI modified the 216 // PLL design and the PLL code only tests for >= rt_r300 217 rt_r300, // Radeon 9700 218 rt_r350, // Radeon 9800 219 rt_rv350, // Radeon 9600 220 rt_rv380, // X600 221 rt_r420 // X800 222 } radeon_type; 223 224 #define IS_RV100_VARIANT ( \ 225 (ai->si->asic == rt_rv100) || \ 226 (ai->si->asic == rt_rv200) || \ 227 (ai->si->asic == rt_rs100) || \ 228 (ai->si->asic == rt_rs200) || \ 229 (ai->si->asic == rt_rv250) || \ 230 (ai->si->asic == rt_rv280) || \ 231 (ai->si->asic == rt_rs300)) 232 233 #define IS_DI_R300_VARIANT ( \ 234 (di->asic == rt_r300) || \ 235 (di->asic == rt_r350) || \ 236 (di->asic == rt_rv350) || \ 237 (di->asic == rt_rv380) || \ 238 (di->asic == rt_r420)) 239 240 #define IS_R300_VARIANT ( \ 241 (ai->si->asic == rt_r300) || \ 242 (ai->si->asic == rt_r350) || \ 243 (ai->si->asic == rt_rv350) || \ 244 (ai->si->asic == rt_rv380) || \ 245 (ai->si->asic == rt_r420)) 246 247 // TV standard 248 typedef enum { 249 ts_off, 250 ts_ntsc, 251 ts_pal_bdghi, 252 ts_pal_m, 253 ts_pal_nc, 254 ts_scart_pal, 255 ts_pal_60, 256 ts_max = ts_pal_60 257 } tv_standard_e; 258 259 260 // type of TV-Chip 261 typedef enum { 262 tc_none, 263 tc_external_rt1, // external Rage Theatre 264 tc_internal_rt1, // internal version 1 265 tc_internal_rt2, // internal version 2 266 } tv_chip_type; 267 268 269 // info about cursor 270 typedef struct { 271 uint8* data; // pointer to framebuffer containing cursor image 272 uint16 hot_x; 273 uint16 hot_y; 274 uint16 x; 275 uint16 y; 276 uint16 width; 277 uint16 height; 278 uint32 mem_handle; // memory handle 279 uint32 fb_offset; // offset in frame buffer 280 bool is_visible; // official flag whether cursor is visible 281 } cursor_info; 282 283 284 // info about flat panel connected to LVDS or DVI port 285 typedef struct { 286 uint panel_pwr_delay; 287 uint panel_xres, panel_yres; 288 289 uint h_blank, h_over_plus, h_sync_width; 290 uint v_blank, v_over_plus, v_sync_width; 291 uint dot_clock; // in kHz (this is BeOS like, ATI uses 10 kHz steps!) 292 293 bool is_fp2; // true, if second flat panel 294 // display_type_e disp_type; 295 uint16 ref_div; 296 uint8 post_div; 297 uint8 feedback_div; 298 bool fixed_dividers; 299 300 uint64 h_ratio; // current stretch ratio, needed for overlays 301 uint64 v_ratio; // (mode_res/native_res; 32.32) 302 } fp_info; 303 304 305 // crtc info 306 typedef struct { 307 //bool is_crtc2; // true, if crtc2 308 int8 flatpanel_port; // linked flat panel port (-1 if none) 309 bool cursor_on_screen; // cursor is visible on this head 310 int crtc_idx; // index of CRTC 311 display_device_e active_displays; // currently driven displays 312 display_device_e chosen_displays; // displays to be driven after next mode switch 313 sem_id vblank; // vertical blank interrupt semaphore 314 uint32 rel_x, rel_y; // relative position in multi-monitor mode 315 display_mode mode; // display mode of this head 316 } crtc_info; 317 318 319 // info about PLLs on graphics card as retrieved from BIOS 320 // all values are in 10kHz 321 typedef struct { 322 uint32 max_pll_freq; // maximum PLL output frequency 323 uint32 min_pll_freq; // minimum PLL output frequency 324 uint32 xclk; // core frequency 325 uint32 ref_div; // default reference divider 326 uint32 ref_freq; // PLL reference frequency 327 } general_pll_info; 328 329 330 // mapping of pll divider code to actual divider value 331 typedef struct { 332 uint8 divider; // divider 333 uint8 code; // code as used in register 334 } pll_divider_map; 335 336 337 // info about a PLL 338 // all values are in 10 kHz 339 typedef struct { 340 pll_divider_map *post_divs; // list of possible post dividers 341 pll_divider_map *extra_post_divs; // list of possible extra post dividers 342 uint32 ref_freq; // reference frequency 343 uint32 vco_min, vco_max; // VCO frequency range 344 uint32 min_ref_div, max_ref_div; // reference divider range 345 uint32 pll_in_min, pll_in_max; // PLL input frequency range 346 uint32 extra_feedback_div; // hardwired divider before feedback divider 347 uint32 min_feedback_div, max_feedback_div; // feedback divider range 348 uint32 best_vco; // preferred VCO frequency (0 for don't care) 349 } pll_info; 350 351 // info for ext tmds pll 352 typedef struct { 353 uint32 freq; 354 uint32 value; 355 } tmds_pll_info; 356 357 // one overlay buffer 358 typedef struct overlay_buffer_node { 359 struct overlay_buffer_node *next, *prev; 360 uint32 mem_handle; 361 uint32 mem_offset; 362 uint ati_space; // colour space according to ATI 363 uint test_reg; // content of test reg 364 overlay_buffer buffer; 365 } overlay_buffer_node; 366 367 368 // info about active overlay 369 typedef struct { 370 overlay_token ot; 371 overlay_buffer ob; 372 overlay_window ow; 373 overlay_view ov; 374 uint16 h_display_start; 375 uint16 v_display_start; 376 377 overlay_buffer_node *on; // current buffer 378 overlay_buffer_node *prev_on; // previous buffer (for temporal deinterlace, currently unused) 379 int crtc_idx; // crtc where the overlay is shown on 380 uint32 rel_offset; // offset of overlay source due to clipping 381 } overlay_info; 382 383 384 // each accelerant gets one "virtual card", i.e. you 385 // can have independant accelerants for each head 386 // (this is an ongoing project ;) 387 typedef struct { 388 uint32 id; // identifier used to know which card the 2D accelerator 389 // is prepared for (we use area_id of this structure) 390 bool assigned_crtc[2]; // mask of heads assigned to virtual card 391 bool used_crtc[2]; // mask of heads assigned to virtual card 392 393 display_device_e controlled_displays; // displays devices controlled byvc 394 display_device_e connected_displays; // bit-field of connected displays 395 396 int8 independant_heads; // number of heads to be programmed independantly 397 int8 different_heads; // number of heads showing different parts of framebuffer 398 bool scroll; // scrolling in virtual area enabled 399 400 uint32 datatype; // Radeon code for pixel format 401 uint bpp; // bytes per pixel 402 uint32 pitch; // byte offset between two lines 403 404 uint32 eff_width, eff_height; // size of visible area (including both monitors) 405 uint32 fb_mem_handle; // memory handle 406 uint32 fb_offset; // offset of frame buffer in graphics mem 407 408 cursor_info cursor; 409 410 bool swap_displays; // true to swap monitors 411 bool use_laptop_panel; // true to always use laptop panel 412 tv_standard_e tv_standard; // standard to use for TV Out 413 bool enforce_mode_change; // set to make sure next display mode change 414 // is executed even if display mode seems to be 415 // still the same 416 417 frame_buffer_config fbc; // data for direct frame buffer access 418 419 display_mode mode; // offical mode with multi-monitor bits set 420 overlay_buffer_node *overlay_buffers; // list of allocated overlay buffers 421 422 //int8 whished_overlay_head; // head where users whishes the overlay to be 423 bool uses_overlay; // true if this virtual card owns overlay 424 425 int state_buffer_idx; 426 int state_buffer_size; 427 } virtual_card; 428 429 430 // status of overlay 431 typedef struct { 432 vint32 inuse; // one, if someone allocated overlay head 433 // (this doesn't necessarily mean that an overlay is shown) 434 uint32 token; // arbitrarily chosen token to identify overlay owner 435 // (increased by 1 whenever there is a new owner) 436 uint32 auto_flip_reg; // content of auto_flip_reg 437 } overlay_mgr_info; 438 439 440 // info about indirect CP buffer 441 typedef struct { 442 int next; // next used/free buffer (-1 for EOL) 443 int32 send_tag; // tag assigned when buffer was submitted 444 } indirect_buffer; 445 446 447 // info about command processor (CP) state 448 typedef struct { 449 benaphore lock; // lock to be acquired when talking to CP or 450 // when accesing this structure 451 452 // ring buffer (in non-local memory) 453 struct { 454 uint32 mem_offset; // offset in non-local memory 455 uint32 vm_base; // base of ring buffer as seen by graphics card 456 uint32 tail, tail_mask; // next write position in dwords; mask for wrap-arounds 457 uint32 size; // size in dwords 458 //uint32 head_offset; // offset for automatically updates head in DMA buffer 459 460 //uint32 start_offset; 461 memory_type_e mem_type; 462 //uint32 *start; // pointer to ring buffer 463 //vuint32 *head; // pointer to automatically updated read position 464 465 uint32 space; // known space in ring buffer 466 uint32 mem_handle; // handle of memory of indirect buffers 467 } ring; 468 469 // feedback registers (in PCI memory) 470 struct { 471 //vuint32 *ptr; // pointer to scratch registers 472 uint32 scratch_mem_offset; // offset of scratch registers in feedback memory 473 uint32 head_mem_offset; // offset of head register in feedback memory 474 uint32 scratch_vm_start; // virtual address of scratch as seen by GC 475 uint32 head_vm_address; // virtual address of head as seen by GC 476 memory_type_e mem_type; // memory type of feedback memory 477 uint32 mem_handle; // handle of feedback memory 478 } feedback; 479 480 481 // indirect buffers (in non-local memory) 482 // for indeces: -1 means "none" 483 struct { 484 int free_list; // index of first empty buffer 485 int oldest, // oldest submitted buffer 486 newest; // newest submitted buffer 487 int active_state; // index of active state buffer 488 uint64 cur_tag; // tag of last submitted indirect buffer 489 490 memory_type_e mem_type; 491 uint32 mem_offset; // offset of indirect buffers in non-local memory 492 uint32 vm_start; // start of indirect buffers as seen by graphics card 493 494 indirect_buffer buffers[NUM_INDIRECT_BUFFERS]; // info about buffers 495 uint32 mem_handle; // handle of memory of indirect buffers 496 } buffers; 497 } CP_info; 498 499 500 // info about different graphics-related memory 501 // (see memory_type_e) 502 typedef struct { 503 area_id area; // area to memory 504 uint32 size; // usable size in bytes 505 uint32 virtual_addr_start; // virtual address (for graphics card!) 506 uint32 virtual_size; // reserved virtual address space in bytes 507 } memory_type_info; 508 509 510 // data published by kernel and shared by all accelerant/virtual cards 511 typedef struct { 512 // filled out by kernel 513 CP_info cp; // info concerning command processor 514 bool acc_dma; // prevent use of dma engine 515 516 // set by accelerant 517 struct { 518 uint64 count; // count of submitted CP commands 519 uint64 last_idle; // count when engine was idle last time 520 uint64 written; // last count passed to CP 521 benaphore lock; // engine lock 522 } engine; 523 524 uint16 vendor_id; // PCI vendor id 525 uint16 device_id; // PCI device id 526 uint8 revision; // PCI device revision 527 528 radeon_type asic; // ASIC version 529 bool is_mobility; // mobility version 530 bool is_igp; // might need to know if it's an integrated chip 531 bool is_atombios; 532 533 tv_chip_type tv_chip; // type of TV-Out encoder 534 bool new_pll; // r300 style PLL 535 bool has_no_i2c; // I2C is broken 536 uint16 panel_pwr_delay; // delay for LCD backlight to stabilise 537 uint8 theatre_channel; // VIP channel of Rage Theatre (if applicable) 538 539 general_pll_info pll; 540 tmds_pll_info tmds_pll[4]; 541 542 area_id regs_area; // area of memory mapped registers 543 area_id ROM_area; // area of ROM 544 void *framebuffer_pci; // physical address of frame buffer (aka local memory) 545 // this is a hack needed by BeOS 546 547 crtc_info crtc[2]; // info about each crtc 548 uint8 num_crtc; // number of physical heads 549 550 fp_info flatpanels[2]; // info about connected flat panels (if any) 551 disp_entity routing; // info if display connector routings eg DVI-I <- EXT TMDS <- DAC2 <- CRTC2 552 553 memory_type_info memory[mt_last]; // info about memory types 554 memory_type_e nonlocal_type; // default type of non-local memory 555 556 uint8 *local_mem; // address of local memory; 557 // this is a hack requested by BeOS 558 559 area_id mode_list_area; // area containing display mode list 560 uint mode_count; 561 562 uint32 active_vc; // currently selected virtual card in terms of 2D acceleration 563 564 uint32 dac_cntl2; // content of dac_cntl2 register 565 uint32 tmds_pll_cntl; // undocumented here be dragons 566 uint32 tmds_transmitter_cntl; // undocumented here be dragons 567 568 overlay_info pending_overlay; // overlay to be shown 569 overlay_info active_overlay; // overlay shown 570 overlay_mgr_info overlay_mgr; // status of overlay 571 572 // data needed for VBI emulation 573 // (currently not fully implemented - if the user disabled graphics card 574 // IRQ in the BIOS, it's his fault) 575 int refresh_period; // duration of one frame in ms 576 int blank_period; // vertical blank period of a frame in ms 577 int enable_virtual_irq; // true, to enable virtual interrupts 578 579 radeon_settings settings; // settings from radeon.settings file 580 581 struct log_info_t *log; // fast logger data 582 } shared_info; 583 584 585 // retrieve the area_id of the kernel/accelerant shared info 586 typedef struct { 587 uint32 magic; // magic number 588 area_id shared_info_area; 589 area_id virtual_card_area; 590 } radeon_get_private_data; 591 592 // get devie name (used to clone accelerant) 593 typedef struct { 594 uint32 magic; // magic number 595 char *name; // pointer to buffer containing name (in) 596 } radeon_device_name; 597 598 // alloc (non-)local memory 599 typedef struct { 600 uint32 magic; 601 memory_type_e memory_type;// type of memory 602 uint32 size; // size in bytes 603 uint32 offset; // offset in memory 604 uint32 handle; // handle (needed to free memory) 605 bool global; // set this to true if memory should persist even 606 // if client gets terminated 607 } radeon_alloc_mem; 608 609 // free (non-)local memory 610 typedef struct { 611 uint32 magic; 612 memory_type_e memory_type;// type of memory 613 uint32 handle; // memory handle 614 bool global; // must be same as on alloc_local_mem 615 } radeon_free_mem; 616 617 // wait for idle 618 typedef struct { 619 uint32 magic; 620 bool keep_lock; // keep lock after engine is idle 621 } radeon_wait_for_idle; 622 623 // wait for idle 624 typedef struct { 625 uint32 magic; 626 int entries; // keep lock after engine is idle 627 } radeon_wait_for_fifo; 628 629 // read VIP register 630 typedef struct { 631 uint32 magic; 632 uint channel; // channel, i.e. device 633 uint address; // address 634 uint32 data; // read data 635 bool lock; // true, if CP lock must be acquired 636 } radeon_vip_read; 637 638 // write VIP register 639 typedef struct { 640 uint32 magic; 641 uint channel; // channel, i.e. device 642 uint address; // address 643 uint32 data; // data to write 644 bool lock; // true, if CP lock must be acquired 645 } radeon_vip_write; 646 647 // read VIP fifo 648 typedef struct { 649 uint32 magic; 650 uint channel; // channel, i.e. device 651 uint address; // address 652 uint32 count; // size of buffer 653 uint8 *data; // read data 654 bool lock; // true, if CP lock must be acquired 655 } radeon_vip_fifo_read; 656 657 // write VIP fifo 658 typedef struct { 659 uint32 magic; 660 uint channel; // channel, i.e. device 661 uint address; // address 662 uint32 count; // size of buffer 663 uint8 *data; // data to write 664 bool lock; // true, if CP lock must be acquired 665 } radeon_vip_fifo_write; 666 667 // find channel of device with given ID 668 typedef struct { 669 uint32 magic; 670 uint32 device_id; // id of device 671 uint channel; // channel of device (-1 if not found) 672 } radeon_find_vip_device; 673 674 // reset / init VIP 675 typedef struct { 676 uint32 magic; 677 bool lock; 678 } radeon_vip_reset; 679 680 681 // wait for capture interrupt and get status about 682 typedef struct { 683 uint32 magic; 684 bigtime_t timeout; // timeout to wait for irq 685 bigtime_t timestamp; // timestamp when last capturing was finished 686 uint32 int_status; // content of RADEON_CAP_INT_STATUS 687 uint32 counter; // number of capture interrupts so far 688 } radeon_wait_for_cap_irq; 689 690 // copy data from frame buffer to some memory location 691 typedef struct { 692 uint32 magic; 693 uint32 src; // offset of source data in frame buffer 694 void *target; // target buffer 695 size_t size; // number of bytes to copy 696 bool lock_mem; // true, if target needs to be locked 697 bool contiguous; // true, if target is physically contiguous 698 } radeon_dma_copy; 699 700 // parameter for ioctl without further arguments 701 typedef struct { 702 uint32 magic; 703 } radeon_no_arg; 704 705 #endif 706