1 /* 2 Copyright (c) 2002, Thomas Kurschel 3 4 5 Part of Radeon driver 6 7 PLL registers and access macros 8 */ 9 10 #ifndef _PLL_REG_H 11 #define _PLL_REG_H 12 13 #include "mmio.h" 14 15 // atomic updates of PLL clock don't seem to always work and stick, thus 16 // the bit never resets. Here - we use our own check by reading back the 17 // register we've just wrote to make sure it's got the right value 18 #define RADEON_ATOMIC_UPDATE 0 // Use PLL Atomic updates (seems broken) 19 20 21 // mmio registers 22 #define RADEON_CLOCK_CNTL_DATA 0x000c 23 #define RADEON_CLOCK_CNTL_INDEX 0x0008 24 # define RADEON_PLL_WR_EN (1 << 7) 25 # define RADEON_PLL_DIV_SEL_MASK (3 << 8) 26 # define RADEON_PLL_DIV_SEL_DIV0 (0 << 8) 27 # define RADEON_PLL_DIV_SEL_DIV1 (1 << 8) 28 # define RADEON_PLL_DIV_SEL_DIV2 (2 << 8) 29 # define RADEON_PLL_DIV_SEL_DIV3 (3 << 8) 30 31 32 // indirect PLL registers 33 #define RADEON_CLK_PIN_CNTL 0x0001 34 #define RADEON_PPLL_CNTL 0x0002 35 # define RADEON_PPLL_RESET (1 << 0) 36 # define RADEON_PPLL_SLEEP (1 << 1) 37 # define RADEON_PPLL_ATOMIC_UPDATE_EN (1 << 16) 38 # define RADEON_PPLL_VGA_ATOMIC_UPDATE_EN (1 << 17) 39 # define RADEON_PPLL_ATOMIC_UPDATE_VSYNC (1 << 18) 40 #define RADEON_PPLL_REF_DIV 0x0003 41 # define RADEON_PPLL_REF_DIV_MASK 0x03ff 42 # define RADEON_PPLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */ 43 # define RADEON_PPLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */ 44 #define RADEON_PPLL_DIV_0 0x0004 45 #define RADEON_PPLL_DIV_1 0x0005 46 #define RADEON_PPLL_DIV_2 0x0006 47 #define RADEON_PPLL_DIV_3 0x0007 48 # define RADEON_PPLL_FB3_DIV_MASK 0x07ff 49 # define RADEON_PPLL_POST3_DIV_MASK 0x00070000 50 #define RADEON_VCLK_ECP_CNTL 0x0008 51 # define RADEON_VCLK_SRC_SEL_MASK (3 << 0) 52 # define RADEON_VCLK_SRC_CPU_CLK (0 << 0) 53 # define RADEON_VCLK_SRC_PSCAN_CLK (1 << 0) 54 # define RADEON_VCLK_SRC_BYTE_CLK (2 << 0) 55 # define RADEON_VCLK_SRC_PPLL_CLK (3 << 0) 56 # define RADEON_ECP_DIV_SHIFT 8 57 # define RADEON_ECP_DIV_MASK (3 << 8) 58 # define RADEON_ECP_DIV_VCLK (0 << 8) 59 # define RADEON_ECP_DIV_VCLK_2 (1 << 8) 60 #define RADEON_HTOTAL_CNTL 0x0009 61 #define RADEON_SCLK_CNTL 0x000d 62 # define RADEON_DYN_STOP_LAT_MASK 0x00007ff8 63 # define RADEON_CP_MAX_DYN_STOP_LAT 0x0008 64 # define RADEON_SCLK_FORCEON_MASK 0xffff8000 65 #define RADEON_SCLK_MORE_CNTL 0x0035 66 # define RADEON_SCLK_MORE_FORCEON 0x0700 67 #define RADEON_MCLK_CNTL 0x0012 68 # define RADEON_FORCEON_MCLKA (1 << 16) 69 # define RADEON_FORCEON_MCLKB (1 << 17) 70 # define RADEON_FORCEON_YCLKA (1 << 18) 71 # define RADEON_FORCEON_YCLKB (1 << 19) 72 # define RADEON_FORCEON_MC (1 << 20) 73 # define RADEON_FORCEON_AIC (1 << 21) 74 #define RADEON_P2PLL_CNTL 0x002a 75 # define RADEON_P2PLL_RESET (1 << 0) 76 # define RADEON_P2PLL_SLEEP (1 << 1) 77 # define RADEON_P2PLL_ATOMIC_UPDATE_EN (1 << 16) 78 # define RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN (1 << 17) 79 # define RADEON_P2PLL_ATOMIC_UPDATE_VSYNC (1 << 18) 80 #define RADEON_P2PLL_REF_DIV 0x002B 81 # define RADEON_P2PLL_REF_DIV_MASK 0x03ff 82 # define RADEON_P2PLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */ 83 # define RADEON_P2PLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */ 84 #define RADEON_P2PLL_DIV_0 0x002c 85 # define RADEON_P2PLL_FB0_DIV_MASK 0x07ff 86 # define RADEON_P2PLL_POST0_DIV_MASK 0x00070000 87 #define RADEON_PIXCLKS_CNTL 0x0002d 88 # define RADEON_PIX2CLK_SRC_SEL_MASK (3 << 0) 89 # define RADEON_PIX2CLK_SRC_SEL_CPU_CLK (0 << 0) 90 # define RADEON_PIX2CLK_SRC_SEL_PSCAN_CLK (1 << 0) 91 # define RADEON_PIX2CLK_SRC_SEL_P2PLL_CLK (3 << 0) 92 # define RADEON_PIXCLK_TV_SRC_SEL_MASK (1 << 8) 93 # define RADEON_PIXCLK_TV_SRC_SEL_PIXCLK (0 << 8) 94 # define RADEON_PIXCLK_TV_SRC_SEL_PIX2CLK (1 << 8) 95 #define RADEON_HTOTAL2_CNTL 0x002e 96 97 // r300: to be called after each CLOCK_CNTL_INDEX access; 98 // all functions declared in this header take care of that 99 // (hardware bug fix suggested by XFree86) 100 void R300_PLLFix( accelerator_info *ai ); 101 102 // in general: 103 // - the PLL is connected via special port 104 // - you need first to choose the PLL register and then write/read its value 105 // 106 // if atomic updates are not safe we: 107 // - verify each time whether the right register is chosen 108 // - verify all values written to PLL-registers 109 110 111 // read value "val" from PLL-register "addr" 112 uint32 Radeon_INPLL( accelerator_info *ai, int addr ); 113 114 // write value "val" to PLL-register "addr" 115 void Radeon_OUTPLL( accelerator_info *ai, uint8 addr, uint32 val ); 116 117 // write "val" to PLL-register "addr" keeping bits "mask" 118 void Radeon_OUTPLLP( accelerator_info *ai, uint8 addr, uint32 val, uint32 mask ); 119 120 #endif 121