1 /* 2 Copyright (c) 2002, Thomas Kurschel 3 4 5 Part of Radeon driver 6 7 Basic PLL registers access 8 */ 9 10 #ifndef _PLL_ACCESS_H 11 #define _PLL_ACCESS_H 12 13 #include "mmio.h" 14 15 16 // to be called after each CLOCK_CNTL_INDEX access; 17 // all functions declared in this header take care of that 18 // (hardware bug fix suggested by XFree86) 19 void RADEONPllErrataAfterIndex( vuint8 *regs, radeon_type asic ); 20 21 // to be called after each CLOCK_CNTL_DATA access; 22 // all functions declared in this header take care of that 23 // (hardware bug fix suggested by XFree86) 24 void RADEONPllErrataAfterData( vuint8 *regs, radeon_type asic ); 25 26 // in general: 27 // - the PLL is connected via special port 28 // - you need first to choose the PLL register and then write/read its value 29 // 30 // if atomic updates are not safe we: 31 // - verify each time whether the right register is chosen 32 // - verify all values written to PLL-registers 33 34 35 // read value "val" from PLL-register "addr" 36 uint32 Radeon_INPLL( vuint8 *regs, radeon_type asic, int addr ); 37 38 // write value "val" to PLL-register "addr" 39 void Radeon_OUTPLL( vuint8 *regs, radeon_type asic, uint8 addr, uint32 val ); 40 41 // write "val" to PLL-register "addr" keeping bits "mask" 42 void Radeon_OUTPLLP( vuint8 *regs, radeon_type asic, uint8 addr, uint32 val, uint32 mask ); 43 44 #endif 45