14f5f1b3cSshadow303 /* 24f5f1b3cSshadow303 Copyright (c) 2002, Thomas Kurschel 34f5f1b3cSshadow303 44f5f1b3cSshadow303 54f5f1b3cSshadow303 Part of Radeon driver 64f5f1b3cSshadow303 74f5f1b3cSshadow303 Overlay unit and Subpicture registers 84f5f1b3cSshadow303 */ 94f5f1b3cSshadow303 104f5f1b3cSshadow303 #ifndef _OVERLAY_REGS_H 114f5f1b3cSshadow303 #define _OVERLAY_REGS_H 124f5f1b3cSshadow303 134f5f1b3cSshadow303 144f5f1b3cSshadow303 #define RADEON_OV0_Y_X_START 0x0400 154f5f1b3cSshadow303 #define RADEON_OV0_Y_X_END 0x0404 164f5f1b3cSshadow303 #define RADEON_OV0_PIPELINE_CNTL 0x0408 174f5f1b3cSshadow303 #define RADEON_OV0_REG_LOAD_CNTL 0x0410 184f5f1b3cSshadow303 # define RADEON_REG_LD_CTL_LOCK 0x00000001L 194f5f1b3cSshadow303 # define RADEON_REG_LD_CTL_VBLANK_DURING_LOCK 0x00000002L 204f5f1b3cSshadow303 # define RADEON_REG_LD_CTL_STALL_GUI_UNTIL_FLIP 0x00000004L 214f5f1b3cSshadow303 # define RADEON_REG_LD_CTL_LOCK_READBACK 0x00000008L 224f5f1b3cSshadow303 #define RADEON_OV0_SCALE_CNTL 0x0420 234f5f1b3cSshadow303 # define RADEON_SCALER_HORZ_PICK_NEAREST 0x00000004L 244f5f1b3cSshadow303 # define RADEON_SCALER_VERT_PICK_NEAREST 0x00000008L 254f5f1b3cSshadow303 # define RADEON_SCALER_SIGNED_UV 0x00000010L 264f5f1b3cSshadow303 # define RADEON_SCALER_GAMMA_SEL_MASK 0x00000060L 274f5f1b3cSshadow303 # define RADEON_SCALER_GAMMA_SEL_BRIGHT 0x00000000L 284f5f1b3cSshadow303 # define RADEON_SCALER_GAMMA_SEL_G22 0x00000020L 294f5f1b3cSshadow303 # define RADEON_SCALER_GAMMA_SEL_G18 0x00000040L 304f5f1b3cSshadow303 # define RADEON_SCALER_GAMMA_SEL_G14 0x00000060L 314f5f1b3cSshadow303 # define RADEON_SCALER_COMCORE_SHIFT_UP_ONE 0x00000080L 324f5f1b3cSshadow303 # define RADEON_SCALER_SURFAC_FORMAT 0x00000f00L 334f5f1b3cSshadow303 # define RADEON_SCALER_SOURCE_15BPP 0x00000300L 344f5f1b3cSshadow303 # define RADEON_SCALER_SOURCE_16BPP 0x00000400L 354f5f1b3cSshadow303 # define RADEON_SCALER_SOURCE_32BPP 0x00000600L 364f5f1b3cSshadow303 # define RADEON_SCALER_SOURCE_YUV9 0x00000900L 374f5f1b3cSshadow303 # define RADEON_SCALER_SOURCE_YUV12 0x00000A00L 384f5f1b3cSshadow303 # define RADEON_SCALER_SOURCE_VYUY422 0x00000B00L 394f5f1b3cSshadow303 # define RADEON_SCALER_SOURCE_YVYU422 0x00000C00L 404f5f1b3cSshadow303 # define RADEON_SCALER_ADAPTIVE_DEINT 0x00001000L 414f5f1b3cSshadow303 # define R200_SCALER_TEMPORAL_DEINT 0x00002000L 424f5f1b3cSshadow303 # define RADEON_SCALER_CRTC_SEL 0x00004000L 43*8841d8bcSAxel Dörfler # define RADEON_SCALER_SMART_SWITCH 0x00008000L 444f5f1b3cSshadow303 # define RADEON_SCALER_BURST_PER_PLANE 0x007F0000L 454f5f1b3cSshadow303 # define RADEON_SCALER_DOUBLE_BUFFER 0x01000000L 464f5f1b3cSshadow303 # define RADEON_SCALER_DIS_LIMIT 0x08000000L 47*8841d8bcSAxel Dörfler # define RADEON_SCALER_LIN_TRANS_BYPASS 0x10000000L 484f5f1b3cSshadow303 # define RADEON_SCALER_INT_EMU 0x20000000L 494f5f1b3cSshadow303 # define RADEON_SCALER_ENABLE 0x40000000L 504f5f1b3cSshadow303 # define RADEON_SCALER_SOFT_RESET 0x80000000L 514f5f1b3cSshadow303 #define RADEON_OV0_V_INC 0x0424 524f5f1b3cSshadow303 #define RADEON_OV0_P1_V_ACCUM_INIT 0x0428 534f5f1b3cSshadow303 # define RADEON_OV0_P1_MAX_LN_IN_PER_LN_OUT 0x00000003L 544f5f1b3cSshadow303 # define RADEON_OV0_P1_V_ACCUM_INIT_MASK 0x01ff8000L 554f5f1b3cSshadow303 #define RADEON_OV0_P23_V_ACCUM_INIT 0x042C 564f5f1b3cSshadow303 # define RADEON_OV0_P23_MAX_LN_IN_PER_LN_OUT 0x00000003L 574f5f1b3cSshadow303 # define RADEON_OV0_P23_V_ACCUM_INIT_MASK 0x00ff8000L 584f5f1b3cSshadow303 #define RADEON_OV0_P1_BLANK_LINES_AT_TOP 0x0430 594f5f1b3cSshadow303 # define RADEON_P1_BLNK_LN_AT_TOP_M1_MASK 0x00000fffL 604f5f1b3cSshadow303 # define RADEON_P1_ACTIVE_LINES_M1 0x0fff0000L 614f5f1b3cSshadow303 #define RADEON_OV0_P23_BLANK_LINES_AT_TOP 0x0434 624f5f1b3cSshadow303 # define RADEON_P23_BLNK_LN_AT_TOP_M1_MASK 0x000007ffL 634f5f1b3cSshadow303 # define RADEON_P23_ACTIVE_LINES_M1 0x07ff0000L 644f5f1b3cSshadow303 #define RADEON_OV0_VID_BUF0_BASE_ADRS 0x0440 654f5f1b3cSshadow303 # define RADEON_VIF_BUF0_PITCH_SEL 0x00000001L 664f5f1b3cSshadow303 # define RADEON_VIF_BUF0_TILE_ADRS 0x00000002L 674f5f1b3cSshadow303 # define RADEON_VIF_BUF0_BASE_ADRS_MASK 0x03fffff0L 684f5f1b3cSshadow303 # define RADEON_VIF_BUF0_1ST_LINE_LSBS_MASK 0x48000000L 694f5f1b3cSshadow303 #define RADEON_OV0_VID_BUF1_BASE_ADRS 0x0444 704f5f1b3cSshadow303 # define RADEON_VIF_BUF1_PITCH_SEL 0x00000001L 714f5f1b3cSshadow303 # define RADEON_VIF_BUF1_TILE_ADRS 0x00000002L 724f5f1b3cSshadow303 # define RADEON_VIF_BUF1_BASE_ADRS_MASK 0x03fffff0L 734f5f1b3cSshadow303 # define RADEON_VIF_BUF1_1ST_LINE_LSBS_MASK 0x48000000L 744f5f1b3cSshadow303 #define RADEON_OV0_VID_BUF2_BASE_ADRS 0x0448 754f5f1b3cSshadow303 # define RADEON_VIF_BUF2_PITCH_SEL 0x00000001L 764f5f1b3cSshadow303 # define RADEON_VIF_BUF2_TILE_ADRS 0x00000002L 774f5f1b3cSshadow303 # define RADEON_VIF_BUF2_BASE_ADRS_MASK 0x03fffff0L 784f5f1b3cSshadow303 # define RADEON_VIF_BUF2_1ST_LINE_LSBS_MASK 0x48000000L 794f5f1b3cSshadow303 #define RADEON_OV0_VID_BUF3_BASE_ADRS 0x044C 804f5f1b3cSshadow303 #define RADEON_OV0_VID_BUF4_BASE_ADRS 0x0450 814f5f1b3cSshadow303 #define RADEON_OV0_VID_BUF5_BASE_ADRS 0x0454 824f5f1b3cSshadow303 #define RADEON_OV0_VID_BUF_PITCH0_VALUE 0x0460 834f5f1b3cSshadow303 #define RADEON_OV0_VID_BUF_PITCH1_VALUE 0x0464 844f5f1b3cSshadow303 #define RADEON_OV0_AUTO_FLIP_CNTRL 0x0470 854f5f1b3cSshadow303 # define RADEON_OV0_SOFT_BUF_NUM_MASK 0x00000007 864f5f1b3cSshadow303 # define RADEON_OV0_SOFT_REPEAT_FIELD_MASK 0x00000008 874f5f1b3cSshadow303 # define RADEON_OV0_SOFT_REPEAT_FIELD 0x00000008 884f5f1b3cSshadow303 # define RADEON_OV0_SOFT_BUF_ODD_MASK 0x00000010 894f5f1b3cSshadow303 # define RADEON_OV0_SOFT_BUF_ODD 0x00000010 904f5f1b3cSshadow303 # define RADEON_OV0_IGNORE_REPEAT_FIELD_MASK 0x00000020 914f5f1b3cSshadow303 # define RADEON_OV0_IGNORE_REPEAT_FIELD 0x00000020 924f5f1b3cSshadow303 # define RADEON_OV0_SOFT_EOF_TOGGLE_MASK (1 << 6) 934f5f1b3cSshadow303 # define RADEON_OV0_SOFT_EOF_TOGGLE (1 << 6) 944f5f1b3cSshadow303 # define RADEON_OV0_VID_PORT_SELECT_MASK (3 << 8) 954f5f1b3cSshadow303 # define RADEON_OV0_VID_PORT_SELECT_PORT0 (0 << 8) 964f5f1b3cSshadow303 # define RADEON_OV0_VID_PORT_SELECT_SOFTWARE (2 << 8) 974f5f1b3cSshadow303 # define RADEON_OV0_P1_FIRST_LINE_EVEN_MASK 0x00010000 984f5f1b3cSshadow303 # define RADEON_OV0_P1_FIRST_LINE_EVEN 0x00010000 994f5f1b3cSshadow303 # define RADEON_OV0_SHIFT_EVEN_DOWN_MASK 0x00040000 1004f5f1b3cSshadow303 # define RADEON_OV0_SHIFT_EVEN_DOWN 0x00040000 1014f5f1b3cSshadow303 # define RADEON_OV0_SHIFT_ODD_DOWN_MASK 0x00080000 1024f5f1b3cSshadow303 # define RADEON_OV0_SHIFT_ODD_DOWN 0x00080000 1034f5f1b3cSshadow303 # define RADEON_OV0_FIELD_POL_SOURCE_MASK 0x00800000 1044f5f1b3cSshadow303 # define RADEON_OV0_FIELD_POL_SOURCE 0x00800000 1054f5f1b3cSshadow303 1064f5f1b3cSshadow303 #define RADEON_OV0_DEINTERLACE_PATTERN 0x0474 1074f5f1b3cSshadow303 # define RADEON_OV0_DEINT_PAT_SHIFT 0 1084f5f1b3cSshadow303 # define RADEON_OV0_DEINT_PAT_MASK (0xfffff << 0) 1094f5f1b3cSshadow303 # define RADEON_OV0_DEINT_PAT_PNTR_SHIFT 24 1104f5f1b3cSshadow303 # define RADEON_OV0_DEINT_PAT_PNTR_MASK (0xf << 24) 1114f5f1b3cSshadow303 # define RADEON_OV0_DEINT_PAT_LEN_M1_SHIFT 28 1124f5f1b3cSshadow303 # define RADEON_OV0_DEINT_PAT_LEN_M1_MASK (0xf << 28) 1134f5f1b3cSshadow303 #define RADEON_OV0_H_INC 0x0480 1144f5f1b3cSshadow303 #define RADEON_OV0_STEP_BY 0x0484 1154f5f1b3cSshadow303 #define RADEON_OV0_P1_H_ACCUM_INIT 0x0488 1164f5f1b3cSshadow303 # define RADEON_OV0_P1_H_ACCUM_INIT_MASK 0x000f8000L 1174f5f1b3cSshadow303 # define RADEON_OV0_P1_PRESHIFT_MASK 0xf0000000L 1184f5f1b3cSshadow303 #define RADEON_OV0_P23_H_ACCUM_INIT 0x048C 1194f5f1b3cSshadow303 # define RADEON_OV0_P23_H_ACCUM_INIT_MASK 0x000f8000L 1204f5f1b3cSshadow303 # define RADEON_OV0_P23_PRESHIFT_MASK 0x70000000L 1214f5f1b3cSshadow303 #define RADEON_OV0_P1_X_START_END 0x0494 1224f5f1b3cSshadow303 #define RADEON_OV0_P2_X_START_END 0x0498 1234f5f1b3cSshadow303 #define RADEON_OV0_P3_X_START_END 0x049C 1244f5f1b3cSshadow303 #define RADEON_OV0_FILTER_CNTL 0x04A0 1254f5f1b3cSshadow303 # define RADEON_OV0_HC_COEF_ON_HORZ_Y 0x0001 1264f5f1b3cSshadow303 # define RADEON_OV0_HC_COEF_ON_HORZ_UV 0x0002 1274f5f1b3cSshadow303 # define RADEON_OV0_HC_COEF_ON_VERT_Y 0x0004 1284f5f1b3cSshadow303 # define RADEON_OV0_HC_COEF_ON_VERT_UV 0x0008 1294f5f1b3cSshadow303 #define RADEON_OV0_FOUR_TAP_COEF_0 0x04B0 1304f5f1b3cSshadow303 #define RADEON_OV0_FOUR_TAP_COEF_1 0x04B4 1314f5f1b3cSshadow303 #define RADEON_OV0_FOUR_TAP_COEF_2 0x04B8 1324f5f1b3cSshadow303 #define RADEON_OV0_FOUR_TAP_COEF_3 0x04BC 1334f5f1b3cSshadow303 #define RADEON_OV0_FOUR_TAP_COEF_4 0x04C0 1344f5f1b3cSshadow303 #define RADEON_OV0_COLOUR_CNTL 0x04E0 1354f5f1b3cSshadow303 1364f5f1b3cSshadow303 #define RADEON_OV0_VIDEO_KEY_CLR 0x04E4 1374f5f1b3cSshadow303 #define RADEON_OV0_VIDEO_KEY_MSK 0x04E8 1384f5f1b3cSshadow303 #define RADEON_OV0_GRAPHICS_KEY_CLR 0x04EC 1394f5f1b3cSshadow303 #define RADEON_OV0_GRAPHICS_KEY_MSK 0x04F0 1404f5f1b3cSshadow303 1414f5f1b3cSshadow303 #define RADEON_OV0_VIDEO_KEY_CLR_LOW 0x04E4 1424f5f1b3cSshadow303 #define RADEON_OV0_VIDEO_KEY_CLR_HIGH 0x04E8 1434f5f1b3cSshadow303 #define RADEON_OV0_GRAPHICS_KEY_CLR_LOW 0x04EC 1444f5f1b3cSshadow303 #define RADEON_OV0_GRAPHICS_KEY_CLR_HIGH 0x04F0 1454f5f1b3cSshadow303 1464f5f1b3cSshadow303 #define RADEON_OV0_KEY_CNTL 0x04F4 1474f5f1b3cSshadow303 # define RADEON_VIDEO_KEY_FN_MASK 0x00000003L 1484f5f1b3cSshadow303 # define RADEON_VIDEO_KEY_FN_FALSE 0x00000000L 1494f5f1b3cSshadow303 # define RADEON_VIDEO_KEY_FN_TRUE 0x00000001L 1504f5f1b3cSshadow303 # define RADEON_VIDEO_KEY_FN_EQ 0x00000002L 1514f5f1b3cSshadow303 # define RADEON_VIDEO_KEY_FN_NE 0x00000003L 1524f5f1b3cSshadow303 # define RADEON_GRAPHIC_KEY_FN_MASK 0x00000030L 1534f5f1b3cSshadow303 # define RADEON_GRAPHIC_KEY_FN_FALSE 0x00000000L 1544f5f1b3cSshadow303 # define RADEON_GRAPHIC_KEY_FN_TRUE 0x00000010L 1554f5f1b3cSshadow303 # define RADEON_GRAPHIC_KEY_FN_EQ 0x00000020L 1564f5f1b3cSshadow303 # define RADEON_GRAPHIC_KEY_FN_NE 0x00000030L 1574f5f1b3cSshadow303 # define RADEON_CMP_MIX_MASK 0x00000100L 1584f5f1b3cSshadow303 # define RADEON_CMP_MIX_OR 0x00000000L 1594f5f1b3cSshadow303 # define RADEON_CMP_MIX_AND 0x00000100L 1604f5f1b3cSshadow303 #define RADEON_OV0_TEST 0x04F8 1614f5f1b3cSshadow303 1624f5f1b3cSshadow303 #define RADEON_OV1_Y_X_START 0x0600 1634f5f1b3cSshadow303 #define RADEON_OV1_Y_X_END 0x0604 1644f5f1b3cSshadow303 #define RADEON_OV1_PIPELINE_CNTL 0x0608 1654f5f1b3cSshadow303 1664f5f1b3cSshadow303 #define RADEON_OV0_GAMMA_0_F 0x0d40 1674f5f1b3cSshadow303 #define RADEON_OV0_GAMMA_10_1F 0x0d44 1684f5f1b3cSshadow303 #define RADEON_OV0_GAMMA_20_3F 0x0d48 1694f5f1b3cSshadow303 #define RADEON_OV0_GAMMA_40_7F 0x0d4c 1704f5f1b3cSshadow303 /* the registers that control gamma in the 80-37f range do not 1714f5f1b3cSshadow303 exist on pre-R200 radeons */ 1724f5f1b3cSshadow303 #define RADEON_OV0_GAMMA_80_BF 0x0e00 1734f5f1b3cSshadow303 #define RADEON_OV0_GAMMA_C0_FF 0x0e04 1744f5f1b3cSshadow303 #define RADEON_OV0_GAMMA_100_13F 0x0e08 1754f5f1b3cSshadow303 #define RADEON_OV0_GAMMA_140_17F 0x0e0c 1764f5f1b3cSshadow303 #define RADEON_OV0_GAMMA_180_1BF 0x0e10 1774f5f1b3cSshadow303 #define RADEON_OV0_GAMMA_1C0_1FF 0x0e14 1784f5f1b3cSshadow303 #define RADEON_OV0_GAMMA_200_23F 0x0e18 1794f5f1b3cSshadow303 #define RADEON_OV0_GAMMA_240_27F 0x0e1c 1804f5f1b3cSshadow303 #define RADEON_OV0_GAMMA_280_2BF 0x0e20 1814f5f1b3cSshadow303 #define RADEON_OV0_GAMMA_2C0_2FF 0x0e24 1824f5f1b3cSshadow303 #define RADEON_OV0_GAMMA_300_33F 0x0e28 1834f5f1b3cSshadow303 #define RADEON_OV0_GAMMA_340_37F 0x0e2c 1844f5f1b3cSshadow303 #define RADEON_OV0_GAMMA_380_3BF 0x0d50 1854f5f1b3cSshadow303 #define RADEON_OV0_GAMMA_3C0_3FF 0x0d54 1864f5f1b3cSshadow303 #define RADEON_OV0_LIN_TRANS_A 0x0d20 1874f5f1b3cSshadow303 #define RADEON_OV0_LIN_TRANS_B 0x0d24 1884f5f1b3cSshadow303 #define RADEON_OV0_LIN_TRANS_C 0x0d28 1894f5f1b3cSshadow303 #define RADEON_OV0_LIN_TRANS_D 0x0d2c 1904f5f1b3cSshadow303 #define RADEON_OV0_LIN_TRANS_E 0x0d30 1914f5f1b3cSshadow303 #define RADEON_OV0_LIN_TRANS_F 0x0d34 1924f5f1b3cSshadow303 1934f5f1b3cSshadow303 #define RADEON_SUBPIC_CNTL 0x0540 1944f5f1b3cSshadow303 1954f5f1b3cSshadow303 #endif 196