1 /* 2 Copyright (c) 2002, Thomas Kurschel 3 4 5 Part of Radeon driver 6 7 BusMemory Control registers 8 */ 9 10 #ifndef _MEMCNTRL_REGS_H 11 #define _MEMCNTRL_REGS_H 12 13 #define RADEON_AGP_BASE 0x0170 14 #define RADEON_MEM_CNTL 0x0140 15 16 #define RADEON_MC_AGP_LOCATION 0x014c 17 #define RADEON_MC_FB_LOCATION 0x0148 18 #define RADEON_MEM_INIT_LAT_TIMER 0x0154 19 #define RADEON_MEM_SDRAM_MODE_REG 0x0158 20 # define RADEON_MEM_CFG_TYPE_MASK (1 << 30) 21 # define RADEON_MEM_CFG_SDR (0 << 30) 22 # define RADEON_MEM_CFG_DDR (1 << 30) 23 #define RADEON_GC_NB_TOM 0x015c 24 #define RADEON_DISPLAY_BASE_ADDRESS 0x023c 25 #define RADEON_CRTC2_DISPLAY_BASE_ADDRESS 0x033c 26 #define RADEON_OV0_BASE_ADDRESS 0x043c 27 28 #define RADEON_GRPH_BUFFER_CNTL 0x02f0 29 # define RADEON_GRPH_START_REQ_MASK (0x7f) 30 # define RADEON_GRPH_START_REQ_SHIFT 0 31 # define RADEON_GRPH_STOP_REQ_MASK (0x7f<<8) 32 # define RADEON_GRPH_STOP_REQ_SHIFT 8 33 # define RADEON_GRPH_CRITICAL_POINT_MASK (0x7f<<16) 34 # define RADEON_GRPH_CRITICAL_POINT_SHIFT 16 35 # define RADEON_GRPH_CRITICAL_CNTL (1<<28) 36 # define RADEON_GRPH_BUFFER_SIZE (1<<29) 37 # define RADEON_GRPH_CRITICAL_AT_SOF (1<<30) 38 # define RADEON_GRPH_STOP_CNTL (1<<31) 39 #define RADEON_GRPH2_BUFFER_CNTL 0x03f0 40 # define RADEON_GRPH2_START_REQ_MASK (0x7f) 41 # define RADEON_GRPH2_START_REQ_SHIFT 0 42 # define RADEON_GRPH2_STOP_REQ_MASK (0x7f<<8) 43 # define RADEON_GRPH2_STOP_REQ_SHIFT 8 44 # define RADEON_GRPH2_CRITICAL_POINT_MASK (0x7f<<16) 45 # define RADEON_GRPH2_CRITICAL_POINT_SHIFT 16 46 # define RADEON_GRPH2_CRITICAL_CNTL (1<<28) 47 # define RADEON_GRPH2_BUFFER_SIZE (1<<29) 48 # define RADEON_GRPH2_CRITICAL_AT_SOF (1<<30) 49 # define RADEON_GRPH2_STOP_CNTL (1<<31) 50 51 #endif 52