14f5f1b3cSshadow303 /* 24f5f1b3cSshadow303 Copyright (c) 2002, Thomas Kurschel 34f5f1b3cSshadow303 44f5f1b3cSshadow303 54f5f1b3cSshadow303 Part of Radeon driver 64f5f1b3cSshadow303 74f5f1b3cSshadow303 Config registers (most are in PCI configuration space) 84f5f1b3cSshadow303 */ 94f5f1b3cSshadow303 104f5f1b3cSshadow303 #ifndef _CONFIG_REGS_H 114f5f1b3cSshadow303 #define _CONFIG_REGS_H 124f5f1b3cSshadow303 134f5f1b3cSshadow303 // mmio registers 14*8841d8bcSAxel Dörfler #define RADEON_CONFIG_APER_0_BASE 0x0100 15*8841d8bcSAxel Dörfler #define RADEON_CONFIG_APER_1_BASE 0x0104 16*8841d8bcSAxel Dörfler #define RADEON_CONFIG_APER_SIZE 0x0108 17*8841d8bcSAxel Dörfler 184f5f1b3cSshadow303 #define RADEON_CONFIG_CNTL 0x00e0 19*8841d8bcSAxel Dörfler # define RADEON_CFG_ATI_REV_A11 (0 << 16) 20*8841d8bcSAxel Dörfler # define RADEON_CFG_ATI_REV_A12 (1 << 16) 21*8841d8bcSAxel Dörfler # define RADEON_CFG_ATI_REV_A13 (2 << 16) 228f6c61bcSshadow303 # define RADEON_CFG_ATI_REV_ID_MASK (0xf << 16) 23*8841d8bcSAxel Dörfler #define RADEON_CFG_ATI_REV_ID_SHIFT 16 244f5f1b3cSshadow303 #define RADEON_CONFIG_MEMSIZE 0x00f8 254f5f1b3cSshadow303 # define RADEON_CONFIG_MEMSIZE_MASK 0x1ff00000 264f5f1b3cSshadow303 274f5f1b3cSshadow303 // following registers can be accessed via PCI configuration space too 284f5f1b3cSshadow303 // (PCI-configuration-space-add + 0xf00 = MMIO-address) 294f5f1b3cSshadow303 #define RADEON_VENDOR_ID 0x0f00 304f5f1b3cSshadow303 #define RADEON_DEVICE_ID 0x0f02 314f5f1b3cSshadow303 #define RADEON_COMMAND 0x0f04 324f5f1b3cSshadow303 #define RADEON_STATUS 0x0f06 334f5f1b3cSshadow303 #define RADEON_REVISION_ID 0x0f08 344f5f1b3cSshadow303 #define RADEON_REGPROG_INF 0x0f09 354f5f1b3cSshadow303 #define RADEON_SUB_CLASS 0x0f0a 364f5f1b3cSshadow303 #define RADEON_BASE_CODE 0x0f0b 374f5f1b3cSshadow303 #define RADEON_CACHE_LINE 0x0f0c 384f5f1b3cSshadow303 #define RADEON_LATENCY 0x0f0d 394f5f1b3cSshadow303 #define RADEON_HEADER 0x0f0e 404f5f1b3cSshadow303 #define RADEON_BIST 0x0f0f 414f5f1b3cSshadow303 #define RADEON_MEM_BASE 0x0f10 424f5f1b3cSshadow303 #define RADEON_IO_BASE 0x0f14 434f5f1b3cSshadow303 #define RADEON_REG_BASE 0x0f18 444f5f1b3cSshadow303 #define RADEON_ADAPTER_ID 0x0f2c //mirror of AADPER_ID_W 454f5f1b3cSshadow303 #define RADEON_BIOS_ROM 0x0f30 464f5f1b3cSshadow303 #define RADEON_CAPABILITIES_PTR 0x0f34 474f5f1b3cSshadow303 #define RADEON_INTERRUPT_LINE 0x0f3c 484f5f1b3cSshadow303 #define RADEON_INTERRUPT_PIN 0x0f3d 494f5f1b3cSshadow303 #define RADEON_MIN_GRANT 0x0f3e 504f5f1b3cSshadow303 #define RADEON_MAX_LATENCY 0x0f3f 514f5f1b3cSshadow303 #define RADEON_ADAPTER_ID_W 0x0f4c 524f5f1b3cSshadow303 #define RADEON_CAPABILITIES_ID 0x0f50 534f5f1b3cSshadow303 544f5f1b3cSshadow303 #define RADEON_PMI_CAP_ID 0x0f50 554f5f1b3cSshadow303 #define RADEON_PMI_NXT_CAP_PTR 0x0f51 564f5f1b3cSshadow303 #define RADEON_PMI_PMC_REG 0x0f52 574f5f1b3cSshadow303 #define RADEON_PMI_STATUS 0x0f54 584f5f1b3cSshadow303 #define RADEON_PMI_DATA 0x0f57 594f5f1b3cSshadow303 604f5f1b3cSshadow303 #define RADEON_AGP_CAP_ID 0x0f58 614f5f1b3cSshadow303 #define RADEON_AGP_STATUS 0x0f5c 624f5f1b3cSshadow303 #define RADEON_AGP_COMMAND 0x0f60 634f5f1b3cSshadow303 644f5f1b3cSshadow303 654f5f1b3cSshadow303 #endif 66