1 /* 2 Copyright (c) 2002, Thomas Kurschel 3 4 5 Part of Radeon driver 6 7 Bus Control registers 8 */ 9 10 #ifndef _BUSCNTRL_REGS_H 11 #define _BUSCNTRL_REGS_H 12 13 #define RADEON_BUS_CNTL 0x0030 14 # define RADEON_BUS_MASTER_DIS (1 << 6) 15 # define RADEON_BUS_RD_DISCARD_EN (1 << 24) 16 # define RADEON_BUS_RD_ABORT_EN (1 << 25) 17 # define RADEON_BUS_MSTR_DISCONNECT_EN (1 << 28) 18 # define RADEON_BUS_WRT_BURST (1 << 29) 19 # define RADEON_BUS_READ_BURST (1 << 30) 20 #define RADEON_BUS_CNTL1 0x0034 21 # define RADEON_BUS_WAIT_ON_LOCK_EN (1 << 4) 22 23 #define RADEON_AGP_CNTL 0x0174 24 # define RADEON_AGP_APER_SIZE_256MB (0x00 << 0) 25 # define RADEON_AGP_APER_SIZE_128MB (0x20 << 0) 26 # define RADEON_AGP_APER_SIZE_64MB (0x30 << 0) 27 # define RADEON_AGP_APER_SIZE_32MB (0x38 << 0) 28 # define RADEON_AGP_APER_SIZE_16MB (0x3c << 0) 29 # define RADEON_AGP_APER_SIZE_8MB (0x3e << 0) 30 # define RADEON_AGP_APER_SIZE_4MB (0x3f << 0) 31 # define RADEON_AGP_APER_SIZE_MASK (0x3f << 0) 32 #define RADEON_AGP_COMMAND 0x0f60 /* PCI */ 33 #define RADEON_AGP_PLL_CNTL 0x000b /* PLL */ 34 #define RADEON_AGP_STATUS 0x0f5c /* PCI */ 35 # define RADEON_AGP_1X_MODE 0x01 36 # define RADEON_AGP_2X_MODE 0x02 37 # define RADEON_AGP_4X_MODE 0x04 38 # define RADEON_AGP_MODE_MASK 0x07 39 40 #define RADEON_MM_DATA 0x0004 41 42 #define RADEON_AIC_CNTL 0x01d0 43 # define RADEON_PCIGART_TRANSLATE_EN (1 << 0) 44 45 // the limit is taken from XFree86; actually, I haven't 46 // found any restrictions in the specs 47 #define ATI_MAX_PCIGART_PAGES 8192 // 32 MB aperture, 4K pages 48 #define ATI_PCIGART_PAGE_SIZE 4096 // PCI GART page size 49 50 #define RADEON_AIC_STAT 0x01d4 51 #define RADEON_AIC_PT_BASE 0x01d8 52 #define RADEON_AIC_LO_ADDR 0x01dc 53 #define RADEON_AIC_HI_ADDR 0x01e0 54 #define RADEON_AIC_TLB_ADDR 0x01e4 55 #define RADEON_AIC_TLB_DATA 0x01e8 56 57 #define RADEON_HOST_PATH_CNTL 0x0130 58 # define RADEON_HDP_SOFT_RESET (1 << 26) 59 # define RADEON_HDP_APER_CNTL (1 << 23) 60 61 #endif 62