1 /* NV registers definitions and macros for access to them */ 2 3 /* PCI_config_space */ 4 #define NVCFG_DEVID 0x00 5 #define NVCFG_DEVCTRL 0x04 6 #define NVCFG_CLASS 0x08 7 #define NVCFG_HEADER 0x0c 8 #define NVCFG_BASE1REGS 0x10 9 #define NVCFG_BASE2FB 0x14 10 #define NVCFG_BASE3 0x18 11 #define NVCFG_BASE4 0x1c //unknown if used 12 #define NVCFG_BASE5 0x20 //unknown if used 13 #define NVCFG_BASE6 0x24 //unknown if used 14 #define NVCFG_BASE7 0x28 //unknown if used 15 #define NVCFG_SUBSYSID1 0x2c 16 #define NVCFG_ROMBASE 0x30 17 #define NVCFG_CFG_0 0x34 18 #define NVCFG_CFG_1 0x38 //unknown if used 19 #define NVCFG_INTERRUPT 0x3c 20 #define NVCFG_SUBSYSID2 0x40 21 #define NVCFG_AGPREF 0x44 22 #define NVCFG_AGPSTAT 0x48 23 #define NVCFG_AGPCMD 0x4c 24 #define NVCFG_ROMSHADOW 0x50 25 #define NVCFG_VGA 0x54 26 #define NVCFG_SCHRATCH 0x58 27 #define NVCFG_CFG_10 0x5c 28 #define NVCFG_CFG_11 0x60 29 #define NVCFG_CFG_12 0x64 30 #define NVCFG_CFG_13 0x68 //unknown if used 31 #define NVCFG_CFG_14 0x6c //unknown if used 32 #define NVCFG_CFG_15 0x70 //unknown if used 33 #define NVCFG_CFG_16 0x74 //unknown if used 34 #define NVCFG_CFG_17 0x78 //unknown if used 35 #define NVCFG_GF2IGPU 0x7c //wrong... 36 #define NVCFG_CFG_19 0x80 //unknown if used 37 #define NVCFG_GF4MXIGPU 0x84 //wrong... 38 #define NVCFG_CFG_21 0x88 //unknown if used 39 #define NVCFG_CFG_22 0x8c //unknown if used 40 #define NVCFG_CFG_23 0x90 //unknown if used 41 #define NVCFG_CFG_24 0x94 //unknown if used 42 #define NVCFG_CFG_25 0x98 //unknown if used 43 #define NVCFG_CFG_26 0x9c //unknown if used 44 #define NVCFG_CFG_27 0xa0 //unknown if used 45 #define NVCFG_CFG_28 0xa4 //unknown if used 46 #define NVCFG_CFG_29 0xa8 //unknown if used 47 #define NVCFG_CFG_30 0xac //unknown if used 48 #define NVCFG_CFG_31 0xb0 //unknown if used 49 #define NVCFG_CFG_32 0xb4 //unknown if used 50 #define NVCFG_CFG_33 0xb8 //unknown if used 51 #define NVCFG_CFG_34 0xbc //unknown if used 52 #define NVCFG_CFG_35 0xc0 //unknown if used 53 #define NVCFG_CFG_36 0xc4 //unknown if used 54 #define NVCFG_CFG_37 0xc8 //unknown if used 55 #define NVCFG_CFG_38 0xcc //unknown if used 56 #define NVCFG_CFG_39 0xd0 //unknown if used 57 #define NVCFG_CFG_40 0xd4 //unknown if used 58 #define NVCFG_CFG_41 0xd8 //unknown if used 59 #define NVCFG_CFG_42 0xdc //unknown if used 60 #define NVCFG_CFG_43 0xe0 //unknown if used 61 #define NVCFG_CFG_44 0xe4 //unknown if used 62 #define NVCFG_CFG_45 0xe8 //unknown if used 63 #define NVCFG_CFG_46 0xec //unknown if used 64 #define NVCFG_CFG_47 0xf0 //unknown if used 65 #define NVCFG_CFG_48 0xf4 //unknown if used 66 #define NVCFG_CFG_49 0xf8 //unknown if used 67 #define NVCFG_CFG_50 0xfc //unknown if used 68 69 /* used NV INT registers for vblank */ 70 #define NV32_MAIN_INTE 0x00000140 71 #define NV32_CRTC_INTS 0x00600100 72 #define NV32_CRTC_INTE 0x00600140 73 74 /* NV ACCeleration registers */ 75 /* engine initialisation registers */ 76 #define NVACC_FORMATS 0x00400618 77 #define NVACC_OFFSET0 0x00400640 78 #define NVACC_OFFSET1 0x00400644 79 #define NVACC_OFFSET2 0x00400648 80 #define NVACC_OFFSET3 0x0040064c 81 #define NVACC_OFFSET4 0x00400650 82 #define NVACC_OFFSET5 0x00400654 83 #define NVACC_BBASE0 0x00400658 84 #define NVACC_BBASE1 0x0040065c 85 #define NVACC_BBASE2 0x00400660 86 #define NVACC_BBASE3 0x00400664 87 #define NVACC_NV10_BBASE4 0x00400668 88 #define NVACC_NV10_BBASE5 0x0040066c 89 #define NVACC_PITCH0 0x00400670 90 #define NVACC_PITCH1 0x00400674 91 #define NVACC_PITCH2 0x00400678 92 #define NVACC_PITCH3 0x0040067c 93 #define NVACC_PITCH4 0x00400680 94 #define NVACC_BLIMIT0 0x00400684 95 #define NVACC_BLIMIT1 0x00400688 96 #define NVACC_BLIMIT2 0x0040068c 97 #define NVACC_BLIMIT3 0x00400690 98 #define NVACC_NV10_BLIMIT4 0x00400694 99 #define NVACC_NV10_BLIMIT5 0x00400698 100 #define NVACC_BPIXEL 0x00400724 101 #define NVACC_NV20_OFFSET0 0x00400820 102 #define NVACC_NV20_OFFSET1 0x00400824 103 #define NVACC_NV20_OFFSET2 0x00400828 104 #define NVACC_NV20_OFFSET3 0x0040082c 105 #define NVACC_STRD_FMT 0x00400830 106 #define NVACC_NV20_PITCH0 0x00400850 107 #define NVACC_NV20_PITCH1 0x00400854 108 #define NVACC_NV20_PITCH2 0x00400858 109 #define NVACC_NV20_PITCH3 0x0040085c 110 #define NVACC_NV20_BLIMIT6 0x00400864 111 #define NVACC_NV20_BLIMIT7 0x00400868 112 #define NVACC_NV20_BLIMIT8 0x0040086c 113 #define NVACC_NV20_BLIMIT9 0x00400870 114 #define NVACC_NV30_WHAT 0x00400890 115 116 /* specials */ 117 #define NVACC_DEBUG0 0x00400080 118 #define NVACC_DEBUG1 0x00400084 119 #define NVACC_DEBUG2 0x00400088 120 #define NVACC_DEBUG3 0x0040008c 121 #define NVACC_NV10_DEBUG4 0x00400090 122 #define NVACC_ACC_INTS 0x00400100 123 #define NVACC_ACC_INTE 0x00400140 124 #define NVACC_NV10_CTX_CTRL 0x00400144 125 #define NVACC_STATUS 0x00400700 126 #define NVACC_NV04_SURF_TYP 0x0040070c 127 #define NVACC_NV10_SURF_TYP 0x00400710 128 #define NVACC_NV04_ACC_STAT 0x00400710 129 #define NVACC_NV10_ACC_STAT 0x00400714 130 #define NVACC_FIFO_EN 0x00400720 131 #define NVACC_PAT_SHP 0x00400810 132 #define NVACC_NV10_XFMOD0 0x00400f40 133 #define NVACC_NV10_XFMOD1 0x00400f44 134 #define NVACC_NV10_PIPEADR 0x00400f50 135 #define NVACC_NV10_PIPEDAT 0x00400f54 136 /* PGRAPH cache registers */ 137 #define NVACC_CACHE1_1 0x00400160 138 #define NVACC_CACHE1_2 0x00400180 139 #define NVACC_CACHE1_3 0x004001a0 140 #define NVACC_CACHE1_4 0x004001c0 141 #define NVACC_CACHE1_5 0x004001e0 142 #define NVACC_CACHE2_1 0x00400164 143 #define NVACC_CACHE2_2 0x00400184 144 #define NVACC_CACHE2_3 0x004001a4 145 #define NVACC_CACHE2_4 0x004001c4 146 #define NVACC_CACHE2_5 0x004001e4 147 #define NVACC_CACHE3_1 0x00400168 148 #define NVACC_CACHE3_2 0x00400188 149 #define NVACC_CACHE3_3 0x004001a8 150 #define NVACC_CACHE3_4 0x004001c8 151 #define NVACC_CACHE3_5 0x004001e8 152 #define NVACC_CACHE4_1 0x0040016c 153 #define NVACC_CACHE4_2 0x0040018c 154 #define NVACC_CACHE4_3 0x004001ac 155 #define NVACC_CACHE4_4 0x004001cc 156 #define NVACC_CACHE4_5 0x004001ec 157 #define NVACC_NV10_CACHE5_1 0x00400170 158 #define NVACC_NV04_CTX_CTRL 0x00400170 159 #define NVACC_CACHE5_2 0x00400190 160 #define NVACC_CACHE5_3 0x004001b0 161 #define NVACC_CACHE5_4 0x004001d0 162 #define NVACC_CACHE5_5 0x004001f0 163 #define NVACC_NV10_CACHE6_1 0x00400174 164 #define NVACC_CACHE6_2 0x00400194 165 #define NVACC_CACHE6_3 0x004001b4 166 #define NVACC_CACHE6_4 0x004001d4 167 #define NVACC_CACHE6_5 0x004001f4 168 #define NVACC_NV10_CACHE7_1 0x00400178 169 #define NVACC_CACHE7_2 0x00400198 170 #define NVACC_CACHE7_3 0x004001b8 171 #define NVACC_CACHE7_4 0x004001d8 172 #define NVACC_CACHE7_5 0x004001f8 173 #define NVACC_NV10_CACHE8_1 0x0040017c 174 #define NVACC_CACHE8_2 0x0040019c 175 #define NVACC_CACHE8_3 0x004001bc 176 #define NVACC_CACHE8_4 0x004001dc 177 #define NVACC_CACHE8_5 0x004001fc 178 #define NVACC_NV10_CTX_SW1 0x0040014c 179 #define NVACC_NV10_CTX_SW2 0x00400150 180 #define NVACC_NV10_CTX_SW3 0x00400154 181 #define NVACC_NV10_CTX_SW4 0x00400158 182 #define NVACC_NV10_CTX_SW5 0x0040015c 183 /* engine tile registers src */ 184 #define NVACC_NV20_FBWHAT0 0x00100200 185 #define NVACC_NV20_FBWHAT1 0x00100204 186 #define NVACC_NV10_FBTIL0AD 0x00100240 187 #define NVACC_NV10_FBTIL0ED 0x00100244 188 #define NVACC_NV10_FBTIL0PT 0x00100248 189 #define NVACC_NV10_FBTIL0ST 0x0010024c 190 #define NVACC_NV10_FBTIL1AD 0x00100250 191 #define NVACC_NV10_FBTIL1ED 0x00100254 192 #define NVACC_NV10_FBTIL1PT 0x00100258 193 #define NVACC_NV10_FBTIL1ST 0x0010025c 194 #define NVACC_NV10_FBTIL2AD 0x00100260 195 #define NVACC_NV10_FBTIL2ED 0x00100264 196 #define NVACC_NV10_FBTIL2PT 0x00100268 197 #define NVACC_NV10_FBTIL2ST 0x0010026c 198 #define NVACC_NV10_FBTIL3AD 0x00100270 199 #define NVACC_NV10_FBTIL3ED 0x00100274 200 #define NVACC_NV10_FBTIL3PT 0x00100278 201 #define NVACC_NV10_FBTIL3ST 0x0010027c 202 #define NVACC_NV10_FBTIL4AD 0x00100280 203 #define NVACC_NV10_FBTIL4ED 0x00100284 204 #define NVACC_NV10_FBTIL4PT 0x00100288 205 #define NVACC_NV10_FBTIL4ST 0x0010028c 206 #define NVACC_NV10_FBTIL5AD 0x00100290 207 #define NVACC_NV10_FBTIL5ED 0x00100294 208 #define NVACC_NV10_FBTIL5PT 0x00100298 209 #define NVACC_NV10_FBTIL5ST 0x0010029c 210 #define NVACC_NV10_FBTIL6AD 0x001002a0 211 #define NVACC_NV10_FBTIL6ED 0x001002a4 212 #define NVACC_NV10_FBTIL6PT 0x001002a8 213 #define NVACC_NV10_FBTIL6ST 0x001002ac 214 #define NVACC_NV10_FBTIL7AD 0x001002b0 215 #define NVACC_NV10_FBTIL7ED 0x001002b4 216 #define NVACC_NV10_FBTIL7PT 0x001002b8 217 #define NVACC_NV10_FBTIL7ST 0x001002bc 218 /* engine tile registers dst */ 219 #define NVACC_NV20_WHAT0 0x004009a4 220 #define NVACC_NV20_WHAT1 0x004009a8 221 #define NVACC_NV10_TIL0AD 0x00400b00 222 #define NVACC_NV10_TIL0ED 0x00400b04 223 #define NVACC_NV10_TIL0PT 0x00400b08 224 #define NVACC_NV10_TIL0ST 0x00400b0c 225 #define NVACC_NV10_TIL1AD 0x00400b10 226 #define NVACC_NV10_TIL1ED 0x00400b14 227 #define NVACC_NV10_TIL1PT 0x00400b18 228 #define NVACC_NV10_TIL1ST 0x00400b1c 229 #define NVACC_NV10_TIL2AD 0x00400b20 230 #define NVACC_NV10_TIL2ED 0x00400b24 231 #define NVACC_NV10_TIL2PT 0x00400b28 232 #define NVACC_NV10_TIL2ST 0x00400b2c 233 #define NVACC_NV10_TIL3AD 0x00400b30 234 #define NVACC_NV10_TIL3ED 0x00400b34 235 #define NVACC_NV10_TIL3PT 0x00400b38 236 #define NVACC_NV10_TIL3ST 0x00400b3c 237 #define NVACC_NV10_TIL4AD 0x00400b40 238 #define NVACC_NV10_TIL4ED 0x00400b44 239 #define NVACC_NV10_TIL4PT 0x00400b48 240 #define NVACC_NV10_TIL4ST 0x00400b4c 241 #define NVACC_NV10_TIL5AD 0x00400b50 242 #define NVACC_NV10_TIL5ED 0x00400b54 243 #define NVACC_NV10_TIL5PT 0x00400b58 244 #define NVACC_NV10_TIL5ST 0x00400b5c 245 #define NVACC_NV10_TIL6AD 0x00400b60 246 #define NVACC_NV10_TIL6ED 0x00400b64 247 #define NVACC_NV10_TIL6PT 0x00400b68 248 #define NVACC_NV10_TIL6ST 0x00400b6c 249 #define NVACC_NV10_TIL7AD 0x00400b70 250 #define NVACC_NV10_TIL7ED 0x00400b74 251 #define NVACC_NV10_TIL7PT 0x00400b78 252 #define NVACC_NV10_TIL7ST 0x00400b7c 253 /* cache setup registers */ 254 #define NVACC_PF_INTSTAT 0x00002100 255 #define NVACC_PF_INTEN 0x00002140 256 #define NVACC_PF_RAMHT 0x00002210 257 #define NVACC_PF_RAMFC 0x00002214 258 #define NVACC_PF_RAMRO 0x00002218 259 #define NVACC_PF_CACHES 0x00002500 260 #define NVACC_PF_SIZE 0x0000250c 261 #define NVACC_PF_CACH0_PSH0 0x00003000 262 #define NVACC_PF_CACH0_PUL0 0x00003050 263 #define NVACC_PF_CACH0_PUL1 0x00003054 264 #define NVACC_PF_CACH1_PSH0 0x00003200 265 #define NVACC_PF_CACH1_PSH1 0x00003204 266 #define NVACC_PF_CACH1_DMAI 0x0000322c 267 #define NVACC_PF_CACH1_PUL0 0x00003250 268 #define NVACC_PF_CACH1_PUL1 0x00003254 269 #define NVACC_PF_CACH1_HASH 0x00003258 270 /* Ptimer registers */ 271 #define NVACC_PT_INTSTAT 0x00009100 272 #define NVACC_PT_INTEN 0x00009140 273 #define NVACC_PT_NUMERATOR 0x00009200 274 #define NVACC_PT_DENOMINATR 0x00009210 275 /* used PRAMIN registers */ 276 #define NVACC_PR_CTX0_R 0x00711400 277 #define NVACC_PR_CTX1_R 0x00711404 278 #define NVACC_PR_CTX2_R 0x00711408 279 #define NVACC_PR_CTX3_R 0x0071140c 280 #define NVACC_PR_CTX0_0 0x00711420 281 #define NVACC_PR_CTX1_0 0x00711424 282 #define NVACC_PR_CTX2_0 0x00711428 283 #define NVACC_PR_CTX3_0 0x0071142c 284 #define NVACC_PR_CTX0_1 0x00711430 285 #define NVACC_PR_CTX1_1 0x00711434 286 #define NVACC_PR_CTX2_1 0x00711438 287 #define NVACC_PR_CTX3_1 0x0071143c 288 #define NVACC_PR_CTX0_2 0x00711440 289 #define NVACC_PR_CTX1_2 0x00711444 290 #define NVACC_PR_CTX2_2 0x00711448 291 #define NVACC_PR_CTX3_2 0x0071144c 292 #define NVACC_PR_CTX0_3 0x00711450 293 #define NVACC_PR_CTX1_3 0x00711454 294 #define NVACC_PR_CTX2_3 0x00711458 295 #define NVACC_PR_CTX3_3 0x0071145c 296 #define NVACC_PR_CTX0_4 0x00711460 297 #define NVACC_PR_CTX1_4 0x00711464 298 #define NVACC_PR_CTX2_4 0x00711468 299 #define NVACC_PR_CTX3_4 0x0071146c 300 #define NVACC_PR_CTX0_5 0x00711470 301 #define NVACC_PR_CTX1_5 0x00711474 302 #define NVACC_PR_CTX2_5 0x00711478 303 #define NVACC_PR_CTX3_5 0x0071147c 304 #define NVACC_PR_CTX0_6 0x00711480 305 #define NVACC_PR_CTX1_6 0x00711484 306 #define NVACC_PR_CTX2_6 0x00711488 307 #define NVACC_PR_CTX3_6 0x0071148c 308 #define NVACC_PR_CTX0_7 0x00711490 309 #define NVACC_PR_CTX1_7 0x00711494 310 #define NVACC_PR_CTX2_7 0x00711498 311 #define NVACC_PR_CTX3_7 0x0071149c 312 #define NVACC_PR_CTX0_8 0x007114a0 313 #define NVACC_PR_CTX1_8 0x007114a4 314 #define NVACC_PR_CTX2_8 0x007114a8 315 #define NVACC_PR_CTX3_8 0x007114ac 316 #define NVACC_PR_CTX0_9 0x007114b0 317 #define NVACC_PR_CTX1_9 0x007114b4 318 #define NVACC_PR_CTX2_9 0x007114b8 319 #define NVACC_PR_CTX3_9 0x007114bc 320 #define NVACC_PR_CTX0_A 0x007114c0 321 #define NVACC_PR_CTX1_A 0x007114c4 /* not used */ 322 #define NVACC_PR_CTX2_A 0x007114c8 323 #define NVACC_PR_CTX3_A 0x007114cc 324 #define NVACC_PR_CTX0_B 0x007114d0 325 #define NVACC_PR_CTX1_B 0x007114d4 326 #define NVACC_PR_CTX2_B 0x007114d8 327 #define NVACC_PR_CTX3_B 0x007114dc 328 #define NVACC_PR_CTX0_C 0x007114e0 329 #define NVACC_PR_CTX1_C 0x007114e4 330 #define NVACC_PR_CTX2_C 0x007114e8 331 #define NVACC_PR_CTX3_C 0x007114ec 332 #define NVACC_PR_CTX0_D 0x007114f0 333 #define NVACC_PR_CTX1_D 0x007114f4 334 #define NVACC_PR_CTX2_D 0x007114f8 335 #define NVACC_PR_CTX3_D 0x007114fc 336 #define NVACC_PR_CTX0_E 0x00711500 337 #define NVACC_PR_CTX1_E 0x00711504 338 #define NVACC_PR_CTX2_E 0x00711508 339 #define NVACC_PR_CTX3_E 0x0071150c 340 /* used RAMHT registers (hash-table(?)) */ 341 #define NVACC_HT_HANDL_00 0x00710000 342 #define NVACC_HT_VALUE_00 0x00710004 343 #define NVACC_HT_HANDL_01 0x00710008 344 #define NVACC_HT_VALUE_01 0x0071000c 345 #define NVACC_HT_HANDL_02 0x00710010 346 #define NVACC_HT_VALUE_02 0x00710014 347 #define NVACC_HT_HANDL_03 0x00710018 348 #define NVACC_HT_VALUE_03 0x0071001c 349 #define NVACC_HT_HANDL_04 0x00710020 350 #define NVACC_HT_VALUE_04 0x00710024 351 #define NVACC_HT_HANDL_05 0x00710028 352 #define NVACC_HT_VALUE_05 0x0071002c 353 #define NVACC_HT_HANDL_06 0x00710030 354 #define NVACC_HT_VALUE_06 0x00710034 355 #define NVACC_HT_HANDL_10 0x00710080 356 #define NVACC_HT_VALUE_10 0x00710084 357 #define NVACC_HT_HANDL_11 0x00710088 358 #define NVACC_HT_VALUE_11 0x0071008c 359 #define NVACC_HT_HANDL_12 0x00710090 360 #define NVACC_HT_VALUE_12 0x00710094 361 #define NVACC_HT_HANDL_13 0x00710098 362 #define NVACC_HT_VALUE_13 0x0071009c 363 #define NVACC_HT_HANDL_14 0x007100a0 364 #define NVACC_HT_VALUE_14 0x007100a4 365 #define NVACC_HT_HANDL_15 0x007100a8 366 #define NVACC_HT_VALUE_15 0x007100ac 367 #define NVACC_HT_HANDL_16 0x007100b0 368 #define NVACC_HT_VALUE_16 0x007100b4 369 #define NVACC_HT_HANDL_17 0x007100b8 370 #define NVACC_HT_VALUE_17 0x007100bc 371 372 /* acc engine fifo setup registers (for function_register 'mappings') */ 373 #define NVACC_FIFO_00800000 0x00800000 374 #define NVACC_FIFO_00802000 0x00802000 375 #define NVACC_FIFO_00804000 0x00804000 376 #define NVACC_FIFO_00806000 0x00806000 377 #define NVACC_FIFO_00808000 0x00808000 378 #define NVACC_FIFO_0080a000 0x0080a000 379 #define NVACC_FIFO_0080c000 0x0080c000 380 #define NVACC_FIFO_0080e000 0x0080e000 381 382 /* ROP3 registers (Raster OPeration) */ 383 #define NV16_ROP_FIFOFREE 0x00800010 /* little endian */ 384 #define NVACC_ROP_ROP3 0x00800300 /* 'mapped' from 0x00420300 */ 385 386 /* clip registers */ 387 #define NV16_CLP_FIFOFREE 0x00802010 /* little endian */ 388 #define NVACC_CLP_TOPLEFT 0x00802300 /* 'mapped' from 0x00450300 */ 389 #define NVACC_CLP_WIDHEIGHT 0x00802304 /* 'mapped' from 0x00450304 */ 390 391 /* pattern registers */ 392 #define NV16_PAT_FIFOFREE 0x00804010 /* little endian */ 393 #define NVACC_PAT_SHAPE 0x00804308 /* 'mapped' from 0x00460308 */ 394 #define NVACC_PAT_COLOR0 0x00804310 /* 'mapped' from 0x00460310 */ 395 #define NVACC_PAT_COLOR1 0x00804314 /* 'mapped' from 0x00460314 */ 396 #define NVACC_PAT_MONO1 0x00804318 /* 'mapped' from 0x00460318 */ 397 #define NVACC_PAT_MONO2 0x0080431c /* 'mapped' from 0x0046031c */ 398 399 /* blit registers */ 400 #define NV16_BLT_FIFOFREE 0x00808010 /* little endian */ 401 #define NVACC_BLT_TOPLFTSRC 0x00808300 /* 'mapped' from 0x00500300 */ 402 #define NVACC_BLT_TOPLFTDST 0x00808304 /* 'mapped' from 0x00500304 */ 403 #define NVACC_BLT_SIZE 0x00808308 /* 'mapped' from 0x00500308 */ 404 405 /* used bitmap registers */ 406 #define NV16_BMP_FIFOFREE 0x0080a010 /* little endian */ 407 #define NVACC_BMP_COLOR1A 0x0080a3fc /* 'mapped' from 0x006b03fc */ 408 #define NVACC_BMP_UCRECTL_0 0x0080a400 /* 'mapped' from 0x006b0400 */ 409 #define NVACC_BMP_UCRECSZ_0 0x0080a404 /* 'mapped' from 0x006b0404 */ 410 411 /* Nvidia PCI direct registers */ 412 #define NV32_PWRUPCTRL 0x00000200 413 #define NV8_MISCW 0x000c03c2 414 #define NV8_MISCR 0x000c03cc 415 #define NV8_SEQIND 0x000c03c4 416 #define NV16_SEQIND 0x000c03c4 417 #define NV8_SEQDAT 0x000c03c5 418 #define NV8_GRPHIND 0x000c03ce 419 #define NV16_GRPHIND 0x000c03ce 420 #define NV8_GRPHDAT 0x000c03cf 421 422 /* bootstrap info registers */ 423 #define NV32_NV4STRAPINFO 0x00100000 424 #define NV32_PFB_CONFIG_0 0x00100200 425 #define NV32_NV10STRAPINFO 0x0010020c 426 #define NV32_NVSTRAPINFO2 0x00101000 427 428 /* registers needed for 'coldstart' */ 429 #define NV32_COREPLL 0x00680500 430 #define NV32_MEMPLL 0x00680504 431 #define NV32_COREPLL2 0x00680570 /* NV31, NV36 only */ 432 #define NV32_MEMPLL2 0x00680574 /* NV31, NV36 only */ 433 #define NV32_CONFIG 0x00600804 434 435 /* primary head */ 436 #define NV8_ATTRINDW 0x006013c0 437 #define NV8_ATTRDATW 0x006013c0 438 #define NV8_ATTRDATR 0x006013c1 439 #define NV8_CRTCIND 0x006013d4 440 #define NV16_CRTCIND 0x006013d4 441 #define NV8_CRTCDAT 0x006013d5 442 #define NV8_INSTAT1 0x006013da 443 #define NV32_NV10FBSTADD32 0x00600800 444 #define NV32_RASTER 0x00600808 445 #define NV32_NV10CURADD32 0x0060080c 446 #define NV32_CURCONF 0x00600810 447 #define NV32_FUNCSEL 0x00600860 448 449 /* secondary head */ 450 #define NV8_ATTR2INDW 0x006033c0 451 #define NV8_ATTR2DATW 0x006033c0 452 #define NV8_ATTR2DATR 0x006033c1 453 #define NV8_CRTC2IND 0x006033d4 454 #define NV16_CRTC2IND 0x006033d4 455 #define NV8_CRTC2DAT 0x006033d5 456 #define NV8_2INSTAT1 0x006033da//verify!!! 457 #define NV32_NV10FB2STADD32 0x00602800 458 #define NV32_RASTER2 0x00602808 459 #define NV32_NV10CUR2ADD32 0x0060280c 460 #define NV32_2CURCONF 0x00602810 461 #define NV32_2FUNCSEL 0x00602860 462 463 /* Nvidia DAC direct registers (standard VGA palette RAM registers) */ 464 /* primary head */ 465 #define NV8_PALMASK 0x006813c6 466 #define NV8_PALINDR 0x006813c7 467 #define NV8_PALINDW 0x006813c8 468 #define NV8_PALDATA 0x006813c9 469 /* secondary head */ 470 #define NV8_PAL2MASK 0x006833c6 471 #define NV8_PAL2INDR 0x006833c7 472 #define NV8_PAL2INDW 0x006833c8 473 #define NV8_PAL2DATA 0x006833c9 474 475 /* Nvidia PCI direct DAC registers (32bit) */ 476 /* primary head */ 477 #define NVDAC_CURPOS 0x00680300 478 #define NVDAC_PIXPLLC 0x00680508 479 #define NVDAC_PLLSEL 0x0068050c 480 #define NVDAC_OUTPUT 0x0068052c 481 #define NVDAC_PIXPLLC2 0x00680578 /* NV31, NV36 only */ 482 #define NVDAC_GENCTRL 0x00680600 483 #define NVDAC_TSTCTRL 0x00680608 484 #define NVDAC_TSTDATA 0x00680610 485 /* (flatpanel registers: confirmed for TNT2 and up) */ 486 #define NVDAC_FP_VDISPEND 0x00680800 487 #define NVDAC_FP_VTOTAL 0x00680804 488 #define NVDAC_FP_VCRTC 0x00680808 489 #define NVDAC_FP_VSYNC_S 0x0068080c 490 #define NVDAC_FP_VSYNC_E 0x00680810 491 #define NVDAC_FP_VVALID_S 0x00680814 492 #define NVDAC_FP_VVALID_E 0x00680818 493 #define NVDAC_FP_HDISPEND 0x00680820 494 #define NVDAC_FP_HTOTAL 0x00680824 495 #define NVDAC_FP_HCRTC 0x00680828 496 #define NVDAC_FP_HSYNC_S 0x0068082c 497 #define NVDAC_FP_HSYNC_E 0x00680830 498 #define NVDAC_FP_HVALID_S 0x00680834 499 #define NVDAC_FP_HVALID_E 0x00680838 500 #define NVDAC_FP_CHKSUM 0x00680840 501 #define NVDAC_FP_TST_CTRL 0x00680844 502 #define NVDAC_FP_TG_CTRL 0x00680848 503 #define NVDAC_FP_DEBUG0 0x00680880 504 #define NVDAC_FP_DEBUG1 0x00680884 505 #define NVDAC_FP_DEBUG2 0x00680888 506 #define NVDAC_FP_DEBUG3 0x0068088c 507 /* secondary head */ 508 #define NVDAC2_CURPOS 0x00682300 509 #define NVDAC2_PIXPLLC 0x00680520 510 #define NVDAC2_OUTPUT 0x0068252c 511 #define NVDAC2_PIXPLLC2 0x0068057c /* NV31, NV36 only */ 512 #define NVDAC2_GENCTRL 0x00682600 513 #define NVDAC2_TSTCTRL 0x00682608 514 /* (flatpanel registers) */ 515 #define NVDAC2_FP_VDISPEND 0x00682800 516 #define NVDAC2_FP_VTOTAL 0x00682804 517 #define NVDAC2_FP_VCRTC 0x00682808 518 #define NVDAC2_FP_VSYNC_S 0x0068280c 519 #define NVDAC2_FP_VSYNC_E 0x00682810 520 #define NVDAC2_FP_VVALID_S 0x00682814 521 #define NVDAC2_FP_VVALID_E 0x00682818 522 #define NVDAC2_FP_HDISPEND 0x00682820 523 #define NVDAC2_FP_HTOTAL 0x00682824 524 #define NVDAC2_FP_HCRTC 0x00682828 525 #define NVDAC2_FP_HSYNC_S 0x0068282c 526 #define NVDAC2_FP_HSYNC_E 0x00682830 527 #define NVDAC2_FP_HVALID_S 0x00682834 528 #define NVDAC2_FP_HVALID_E 0x00682838 529 #define NVDAC2_FP_CHKSUM 0x00682840 530 #define NVDAC2_FP_TST_CTRL 0x00682844 531 #define NVDAC2_FP_TG_CTRL 0x00682848 532 #define NVDAC2_FP_DEBUG0 0x00682880 533 #define NVDAC2_FP_DEBUG1 0x00682884 534 #define NVDAC2_FP_DEBUG2 0x00682888 535 #define NVDAC2_FP_DEBUG3 0x0068288c 536 537 /* Nvidia CRTC indexed registers */ 538 /* VGA standard registers: */ 539 #define NVCRTCX_HTOTAL 0x00 540 #define NVCRTCX_HDISPE 0x01 541 #define NVCRTCX_HBLANKS 0x02 542 #define NVCRTCX_HBLANKE 0x03 543 #define NVCRTCX_HSYNCS 0x04 544 #define NVCRTCX_HSYNCE 0x05 545 #define NVCRTCX_VTOTAL 0x06 546 #define NVCRTCX_OVERFLOW 0x07 547 #define NVCRTCX_PRROWSCN 0x08 548 #define NVCRTCX_MAXSCLIN 0x09 549 #define NVCRTCX_VGACURCTRL 0x0a 550 #define NVCRTCX_FBSTADDH 0x0c 551 #define NVCRTCX_FBSTADDL 0x0d 552 #define NVCRTCX_VSYNCS 0x10 553 #define NVCRTCX_VSYNCE 0x11 554 #define NVCRTCX_VDISPE 0x12 555 #define NVCRTCX_PITCHL 0x13 556 #define NVCRTCX_VBLANKS 0x15 557 #define NVCRTCX_VBLANKE 0x16 558 #define NVCRTCX_MODECTL 0x17 559 #define NVCRTCX_LINECOMP 0x18 560 /* Nvidia specific registers: */ 561 #define NVCRTCX_REPAINT0 0x19 562 #define NVCRTCX_REPAINT1 0x1a 563 #define NVCRTCX_LOCK 0x1f 564 #define NVCRTCX_BUFFER 0x21 565 #define NVCRTCX_LSR 0x25 566 #define NVCRTCX_PIXEL 0x28 567 #define NVCRTCX_HEB 0x2d 568 #define NVCRTCX_CURCTL2 0x2f 569 #define NVCRTCX_CURCTL1 0x30 570 #define NVCRTCX_CURCTL0 0x31 571 #define NVCRTCX_LCD 0x33 572 #define NVCRTCX_INTERLACE 0x39 573 #define NVCRTCX_EXTRA 0x41 574 #define NVCRTCX_OWNER 0x44 575 #define NVCRTCX_FP_HTIMING 0x53 576 #define NVCRTCX_FP_VTIMING 0x54 577 #define NVCRTCX_0x59 0x59 578 #define NVCRTCX_0x9f 0x9f 579 580 /* Nvidia ATTRIBUTE indexed registers */ 581 /* VGA standard registers: */ 582 #define NVATBX_MODECTL 0x10 583 #define NVATBX_OSCANCOLOR 0x11 584 #define NVATBX_COLPLANE_EN 0x12 585 #define NVATBX_HORPIXPAN 0x13 586 #define NVATBX_COLSEL 0x14 587 588 /* Nvidia SEQUENCER indexed registers */ 589 /* VGA standard registers: */ 590 #define NVSEQX_RESET 0x00 591 #define NVSEQX_CLKMODE 0x01 592 #define NVSEQX_MEMMODE 0x04 593 594 /* Nvidia GRAPHICS indexed registers */ 595 /* VGA standard registers: */ 596 #define NVGRPHX_ENSETRESET 0x01 597 #define NVGRPHX_DATAROTATE 0x03 598 #define NVGRPHX_READMAPSEL 0x04 599 #define NVGRPHX_MODE 0x05 600 #define NVGRPHX_MISC 0x06 601 #define NVGRPHX_BITMASK 0x08 602 603 /* Nvidia BES (Back End Scaler) registers (< NV10, including NV03, so RIVA128(ZX)) */ 604 #define NVBES_NV04_INTE 0x00680140 605 #define NVBES_NV04_ISCALVH 0x00680200 606 #define NVBES_NV04_CTRL_V 0x00680204 607 #define NVBES_NV04_CTRL_H 0x00680208 608 #define NVBES_NV04_OE_STATE 0x00680224 609 #define NVBES_NV04_SU_STATE 0x00680228 610 #define NVBES_NV04_RM_STATE 0x0068022c 611 #define NVBES_NV04_DSTREF 0x00680230 612 #define NVBES_NV04_DSTSIZE 0x00680234 613 #define NVBES_NV04_FIFOTHRS 0x00680238 614 #define NVBES_NV04_FIFOBURL 0x0068023c 615 #define NVBES_NV04_COLKEY 0x00680240 616 #define NVBES_NV04_GENCTRL 0x00680244 617 #define NVBES_NV04_RED_AMP 0x00680280 618 #define NVBES_NV04_GRN_AMP 0x00680284 619 #define NVBES_NV04_BLU_AMP 0x00680288 620 #define NVBES_NV04_SAT 0x0068028c 621 /* buffer 0 */ 622 #define NVBES_NV04_0BUFADR 0x0068020c 623 #define NVBES_NV04_0SRCPTCH 0x00680214 624 #define NVBES_NV04_0OFFSET 0x0068021c 625 /* buffer 1 */ 626 #define NVBES_NV04_1BUFADR 0x00680210 627 #define NVBES_NV04_1SRCPTCH 0x00680218 628 #define NVBES_NV04_1OFFSET 0x00680220 629 630 /* Nvidia BES (Back End Scaler) registers (>= NV10) */ 631 #define NVBES_NV10_INTE 0x00008140 632 #define NVBES_NV10_BUFSEL 0x00008700 633 #define NVBES_NV10_GENCTRL 0x00008704 634 #define NVBES_NV10_COLKEY 0x00008b00 635 /* buffer 0 */ 636 #define NVBES_NV10_0BUFADR 0x00008900 637 #define NVBES_NV10_0MEMMASK 0x00008908 638 #define NVBES_NV10_0BRICON 0x00008910 639 #define NVBES_NV10_0SAT 0x00008918 640 #define NVBES_NV10_0OFFSET 0x00008920 641 #define NVBES_NV10_0SRCSIZE 0x00008928 642 #define NVBES_NV10_0SRCREF 0x00008930 643 #define NVBES_NV10_0ISCALH 0x00008938 644 #define NVBES_NV10_0ISCALV 0x00008940 645 #define NVBES_NV10_0DSTREF 0x00008948 646 #define NVBES_NV10_0DSTSIZE 0x00008950 647 #define NVBES_NV10_0SRCPTCH 0x00008958 648 /* buffer 1 */ 649 #define NVBES_NV10_1BUFADR 0x00008904 650 #define NVBES_NV10_1MEMMASK 0x0000890c 651 #define NVBES_NV10_1BRICON 0x00008914 652 #define NVBES_NV10_1SAT 0x0000891c 653 #define NVBES_NV10_1OFFSET 0x00008924 654 #define NVBES_NV10_1SRCSIZE 0x0000892c 655 #define NVBES_NV10_1SRCREF 0x00008934 656 #define NVBES_NV10_1ISCALH 0x0000893c 657 #define NVBES_NV10_1ISCALV 0x00008944 658 #define NVBES_NV10_1DSTREF 0x0000894c 659 #define NVBES_NV10_1DSTSIZE 0x00008954 660 #define NVBES_NV10_1SRCPTCH 0x0000895c 661 /* Nvidia MPEG2 hardware decoder (GeForce4MX only) */ 662 #define NVBES_DEC_GENCTRL 0x00001588 663 664 //old: 665 /*MAVEN registers (<= G400) */ 666 #define NVMAV_PGM 0x3E 667 #define NVMAV_PIXPLLM 0x80 668 #define NVMAV_PIXPLLN 0x81 669 #define NVMAV_PIXPLLP 0x82 670 #define NVMAV_GAMMA1 0x83 671 #define NVMAV_GAMMA2 0x84 672 #define NVMAV_GAMMA3 0x85 673 #define NVMAV_GAMMA4 0x86 674 #define NVMAV_GAMMA5 0x87 675 #define NVMAV_GAMMA6 0x88 676 #define NVMAV_GAMMA7 0x89 677 #define NVMAV_GAMMA8 0x8A 678 #define NVMAV_GAMMA9 0x8B 679 #define NVMAV_MONSET 0x8C 680 #define NVMAV_TEST 0x8D 681 #define NVMAV_WREG_0X8E_L 0x8E 682 #define NVMAV_WREG_0X8E_H 0x8F 683 #define NVMAV_HSCALETV 0x90 684 #define NVMAV_TSCALETVL 0x91 685 #define NVMAV_TSCALETVH 0x92 686 #define NVMAV_FFILTER 0x93 687 #define NVMAV_MONEN 0x94 688 #define NVMAV_RESYNC 0x95 689 #define NVMAV_LASTLINEL 0x96 690 #define NVMAV_LASTLINEH 0x97 691 #define NVMAV_WREG_0X98_L 0x98 692 #define NVMAV_WREG_0X98_H 0x99 693 #define NVMAV_HSYNCLENL 0x9A 694 #define NVMAV_HSYNCLENH 0x9B 695 #define NVMAV_HSYNCSTRL 0x9C 696 #define NVMAV_HSYNCSTRH 0x9D 697 #define NVMAV_HDISPLAYL 0x9E 698 #define NVMAV_HDISPLAYH 0x9F 699 #define NVMAV_HTOTALL 0xA0 700 #define NVMAV_HTOTALH 0xA1 701 #define NVMAV_VSYNCLENL 0xA2 702 #define NVMAV_VSYNCLENH 0xA3 703 #define NVMAV_VSYNCSTRL 0xA4 704 #define NVMAV_VSYNCSTRH 0xA5 705 #define NVMAV_VDISPLAYL 0xA6 706 #define NVMAV_VDISPLAYH 0xA7 707 #define NVMAV_VTOTALL 0xA8 708 #define NVMAV_VTOTALH 0xA9 709 #define NVMAV_HVIDRSTL 0xAA 710 #define NVMAV_HVIDRSTH 0xAB 711 #define NVMAV_VVIDRSTL 0xAC 712 #define NVMAV_VVIDRSTH 0xAD 713 #define NVMAV_VSOMETHINGL 0xAE 714 #define NVMAV_VSOMETHINGH 0xAF 715 #define NVMAV_OUTMODE 0xB0 716 #define NVMAV_LOCK 0xB3 717 #define NVMAV_LUMA 0xB9 718 #define NVMAV_VDISPLAYTV 0xBE 719 #define NVMAV_STABLE 0xBF 720 #define NVMAV_HDISPLAYTV 0xC2 721 #define NVMAV_BREG_0XC6 0xC6 722 //end old. 723 724 /* Macros for convenient accesses to the NV chips */ 725 #define NV_REG8(r_) ((vuint8 *)regs)[(r_)] 726 #define NV_REG16(r_) ((vuint16 *)regs)[(r_) >> 1] 727 #define NV_REG32(r_) ((vuint32 *)regs)[(r_) >> 2] 728 729 /* read and write to PCI config space */ 730 #define CFGR(A) (nv_pci_access.offset=NVCFG_##A, ioctl(fd,NV_GET_PCI, &nv_pci_access,sizeof(nv_pci_access)), nv_pci_access.value) 731 #define CFGW(A,B) (nv_pci_access.offset=NVCFG_##A, nv_pci_access.value = B, ioctl(fd,NV_SET_PCI,&nv_pci_access,sizeof(nv_pci_access))) 732 733 /* read and write from the dac registers */ 734 #define DACR(A) (NV_REG32(NVDAC_##A)) 735 #define DACW(A,B) (NV_REG32(NVDAC_##A)=B) 736 737 /* read and write from the secondary dac registers */ 738 #define DAC2R(A) (NV_REG32(NVDAC2_##A)) 739 #define DAC2W(A,B) (NV_REG32(NVDAC2_##A)=B) 740 741 /* read and write from the backend scaler registers */ 742 #define BESR(A) (NV_REG32(NVBES_##A)) 743 #define BESW(A,B) (NV_REG32(NVBES_##A)=B) 744 745 /* read and write from CRTC indexed registers */ 746 #define CRTCW(A,B)(NV_REG16(NV16_CRTCIND) = ((NVCRTCX_##A) | ((B) << 8))) 747 #define CRTCR(A) (NV_REG8(NV8_CRTCIND) = (NVCRTCX_##A), NV_REG8(NV8_CRTCDAT)) 748 749 /* read and write from second CRTC indexed registers */ 750 #define CRTC2W(A,B)(NV_REG16(NV16_CRTC2IND) = ((NVCRTCX_##A) | ((B) << 8))) 751 #define CRTC2R(A) (NV_REG8(NV8_CRTC2IND) = (NVCRTCX_##A), NV_REG8(NV8_CRTC2DAT)) 752 753 /* read and write from ATTRIBUTE indexed registers */ 754 #define ATBW(A,B)(NV_REG8(NV8_INSTAT1), NV_REG8(NV8_ATTRINDW) = ((NVATBX_##A) | 0x20), NV_REG8(NV8_ATTRDATW) = (B)) 755 #define ATBR(A) (NV_REG8(NV8_INSTAT1), NV_REG8(NV8_ATTRINDW) = ((NVATBX_##A) | 0x20), NV_REG8(NV8_ATTRDATR)) 756 757 /* read and write from ATTRIBUTE indexed registers */ 758 #define ATB2W(A,B)(NV_REG8(NV8_INSTAT1), NV_REG8(NV8_ATTR2INDW) = ((NVATBX_##A) | 0x20), NV_REG8(NV8_ATTR2DATW) = (B)) 759 #define ATB2R(A) (NV_REG8(NV8_INSTAT1), NV_REG8(NV8_ATTR2INDW) = ((NVATBX_##A) | 0x20), NV_REG8(NV8_ATTR2DATR)) 760 761 /* read and write from SEQUENCER indexed registers */ 762 #define SEQW(A,B)(NV_REG16(NV16_SEQIND) = ((NVSEQX_##A) | ((B) << 8))) 763 #define SEQR(A) (NV_REG8(NV8_SEQIND) = (NVSEQX_##A), NV_REG8(NV8_SEQDAT)) 764 765 /* read and write from PCI GRAPHICS indexed registers */ 766 #define GRPHW(A,B)(NV_REG16(NV16_GRPHIND) = ((NVGRPHX_##A) | ((B) << 8))) 767 #define GRPHR(A) (NV_REG8(NV8_GRPHIND) = (NVGRPHX_##A), NV_REG8(NV8_GRPHDAT)) 768 769 /* read and write from the acceleration engine registers */ 770 #define ACCR(A) (NV_REG32(NVACC_##A)) 771 #define ACCW(A,B) (NV_REG32(NVACC_##A)=B) 772 773 //old: 774 /* read and write from maven (<= G400) */ 775 #define MAVR(A) (i2c_maven_read (NVMAV_##A )) 776 #define MAVW(A,B) (i2c_maven_write(NVMAV_##A ,B)) 777 #define MAVRW(A) (i2c_maven_read (NVMAV_##A )|(i2c_maven_read(NVMAV_##A +1)<<8)) 778 #define MAVWW(A,B) (i2c_maven_write(NVMAV_##A ,B &0xFF),i2c_maven_write(NVMAV_##A +1,B >>8)) 779