1 /* NV registers definitions and macros for access to them */ 2 3 /* PCI_config_space */ 4 #define NVCFG_DEVID 0x00 5 #define NVCFG_DEVCTRL 0x04 6 #define NVCFG_CLASS 0x08 7 #define NVCFG_HEADER 0x0c 8 #define NVCFG_BASE1REGS 0x10 9 #define NVCFG_BASE2FB 0x14 10 #define NVCFG_BASE3 0x18 11 #define NVCFG_BASE4 0x1c //unknown if used 12 #define NVCFG_BASE5 0x20 //unknown if used 13 #define NVCFG_BASE6 0x24 //unknown if used 14 #define NVCFG_BASE7 0x28 //unknown if used 15 #define NVCFG_SUBSYSID1 0x2c 16 #define NVCFG_ROMBASE 0x30 17 #define NVCFG_CAPPTR 0x34 18 #define NVCFG_CFG_1 0x38 //unknown if used 19 #define NVCFG_INTERRUPT 0x3c 20 #define NVCFG_SUBSYSID2 0x40 21 #define NVCFG_AGPREF 0x44 22 #define NVCFG_AGPSTAT 0x48 23 #define NVCFG_AGPCMD 0x4c 24 #define NVCFG_ROMSHADOW 0x50 25 #define NVCFG_VGA 0x54 26 #define NVCFG_SCHRATCH 0x58 27 #define NVCFG_CFG_10 0x5c 28 #define NVCFG_CFG_11 0x60 29 #define NVCFG_CFG_12 0x64 30 #define NVCFG_CFG_13 0x68 //unknown if used 31 #define NVCFG_CFG_14 0x6c //unknown if used 32 #define NVCFG_CFG_15 0x70 //unknown if used 33 #define NVCFG_CFG_16 0x74 //unknown if used 34 #define NVCFG_PCIEREF 0x78 35 #define NVCFG_PCIEDCAP 0x7c 36 #define NVCFG_PCIEDCTST 0x80 37 #define NVCFG_PCIELCAP 0x84 38 #define NVCFG_PCIELCTST 0x88 39 #define NVCFG_CFG_22 0x8c //unknown if used 40 #define NVCFG_CFG_23 0x90 //unknown if used 41 #define NVCFG_CFG_24 0x94 //unknown if used 42 #define NVCFG_CFG_25 0x98 //unknown if used 43 #define NVCFG_CFG_26 0x9c //unknown if used 44 #define NVCFG_CFG_27 0xa0 //unknown if used 45 #define NVCFG_CFG_28 0xa4 //unknown if used 46 #define NVCFG_CFG_29 0xa8 //unknown if used 47 #define NVCFG_CFG_30 0xac //unknown if used 48 #define NVCFG_CFG_31 0xb0 //unknown if used 49 #define NVCFG_CFG_32 0xb4 //unknown if used 50 #define NVCFG_CFG_33 0xb8 //unknown if used 51 #define NVCFG_CFG_34 0xbc //unknown if used 52 #define NVCFG_CFG_35 0xc0 //unknown if used 53 #define NVCFG_CFG_36 0xc4 //unknown if used 54 #define NVCFG_CFG_37 0xc8 //unknown if used 55 #define NVCFG_CFG_38 0xcc //unknown if used 56 #define NVCFG_CFG_39 0xd0 //unknown if used 57 #define NVCFG_CFG_40 0xd4 //unknown if used 58 #define NVCFG_CFG_41 0xd8 //unknown if used 59 #define NVCFG_CFG_42 0xdc //unknown if used 60 #define NVCFG_CFG_43 0xe0 //unknown if used 61 #define NVCFG_CFG_44 0xe4 //unknown if used 62 #define NVCFG_CFG_45 0xe8 //unknown if used 63 #define NVCFG_CFG_46 0xec //unknown if used 64 #define NVCFG_CFG_47 0xf0 //unknown if used 65 #define NVCFG_CFG_48 0xf4 //unknown if used 66 #define NVCFG_CFG_49 0xf8 //unknown if used 67 #define NVCFG_CFG_50 0xfc //unknown if used 68 69 /* used NV INT registers for vblank */ 70 #define NV32_MAIN_INTE 0x00000140 71 #define NV32_CRTC_INTS 0x00600100 72 #define NV32_CRTC_INTE 0x00600140 73 74 /* NV ACCeleration registers */ 75 /* engine initialisation registers */ 76 #define NVACC_ABS_UCLP_XMIN 0x0040053c 77 #define NVACC_ABS_UCLP_YMIN 0x00400540 78 #define NVACC_ABS_UCLP_XMAX 0x00400544 79 #define NVACC_ABS_UCLP_YMAX 0x00400548 80 #define NVACC_BETA_AND_VAL 0x00400608 81 #define NVACC_FORMATS 0x00400618 82 #define NVACC_OFFSET0 0x00400640 83 #define NVACC_OFFSET1 0x00400644 84 #define NVACC_OFFSET2 0x00400648 85 #define NVACC_OFFSET3 0x0040064c 86 #define NVACC_OFFSET4 0x00400650 87 #define NVACC_OFFSET5 0x00400654 88 #define NVACC_BBASE0 0x00400658 89 #define NVACC_BBASE1 0x0040065c 90 #define NVACC_BBASE2 0x00400660 91 #define NVACC_BBASE3 0x00400664 92 #define NVACC_NV10_BBASE4 0x00400668 93 #define NVACC_NV10_BBASE5 0x0040066c 94 #define NVACC_PITCH0 0x00400670 95 #define NVACC_PITCH1 0x00400674 96 #define NVACC_PITCH2 0x00400678 97 #define NVACC_PITCH3 0x0040067c 98 #define NVACC_PITCH4 0x00400680 99 #define NVACC_BLIMIT0 0x00400684 100 #define NVACC_BLIMIT1 0x00400688 101 #define NVACC_BLIMIT2 0x0040068c 102 #define NVACC_BLIMIT3 0x00400690 103 #define NVACC_NV10_BLIMIT4 0x00400694 104 #define NVACC_NV10_BLIMIT5 0x00400698 105 #define NVACC_BPIXEL 0x00400724 106 #define NVACC_NV20_OFFSET0 0x00400820 107 #define NVACC_NV20_OFFSET1 0x00400824 108 #define NVACC_NV20_OFFSET2 0x00400828 109 #define NVACC_NV20_OFFSET3 0x0040082c 110 #define NVACC_STRD_FMT 0x00400830 111 #define NVACC_NV20_PITCH0 0x00400850 112 #define NVACC_NV20_PITCH1 0x00400854 113 #define NVACC_NV20_PITCH2 0x00400858 114 #define NVACC_NV20_PITCH3 0x0040085c 115 #define NVACC_NV20_BLIMIT6 0x00400864 116 #define NVACC_NV20_BLIMIT7 0x00400868 117 #define NVACC_NV20_BLIMIT8 0x0040086c 118 #define NVACC_NV20_BLIMIT9 0x00400870 119 #define NVACC_NV25_WHAT1 0x00400890 120 121 /* specials */ 122 #define NVACC_DEBUG0 0x00400080 123 #define NVACC_DEBUG1 0x00400084 124 #define NVACC_DEBUG2 0x00400088 125 #define NVACC_DEBUG3 0x0040008c 126 #define NVACC_NV10_DEBUG4 0x00400090 127 #define NVACC_NV10_DEBUG5 0x00400094 128 #define NVACC_NV20_WHAT5 0x00400098 129 #define NVACC_NV20_WHAT1 0x0040009c 130 #define NVACC_ACC_INTS 0x00400100 131 #define NVACC_ACC_INTE 0x00400140 132 #define NVACC_NV10_CTX_CTRL 0x00400144 133 #define NVACC_NV4X_DMA_SRC 0x00400220 134 #define NVACC_NV4X_WHAT1 0x0040032c 135 #define NVACC_NV25_WHAT0 0x00400610 136 #define NVACC_STATUS 0x00400700 137 #define NVACC_NV04_SURF_TYP 0x0040070c 138 #define NVACC_NV10_SURF_TYP 0x00400710 139 #define NVACC_NV04_ACC_STAT 0x00400710 140 #define NVACC_NV10_ACC_STAT 0x00400714 141 #define NVACC_FIFO_EN 0x00400720 142 #define NVACC_RDI_INDEX 0x00400750 143 #define NVACC_RDI_DATA 0x00400754 144 #define NVACC_PAT_SHP 0x00400810 145 #define NVACC_NV40P_WHAT0 0x00400820 146 #define NVACC_NV40P_WHAT1 0x00400824 147 #define NVACC_NV40P_WHAT2 0x00400828 148 #define NVACC_NV40P_WHAT3 0x0040082c 149 #define NVACC_NV40P_OFFSET0 0x00400840 150 #define NVACC_NV40P_OFFSET1 0x00400844 151 #define NVACC_NV44_WHAT2 0x00400860 152 #define NVACC_NV44_WHAT3 0x00400864 153 //fixme? (guessed) 154 #define NVACC_NV40P_PITCH0 0x00400870 155 #define NVACC_NV40P_PITCH1 0x00400874 156 #define NVACC_NV20_WHAT2 0x00400880 157 //end fixme. 158 #define NVACC_NV40P_BLIMIT6 0x004008a0 159 #define NVACC_NV40P_BLIMIT7 0x004008a4 160 #define NVACC_NV20_WHAT0 0x00400900 161 #define NVACC_NV40_WHAT0 0x004009b0 162 #define NVACC_NV40_WHAT1 0x004009b4 163 #define NVACC_NV40_WHAT2 0x004009b8 164 #define NVACC_NV40_WHAT3 0x004009bc 165 #define NVACC_NV20_WHAT3 0x00400b80 166 #define NVACC_NV20_WHAT4 0x00400b84 167 #define NVACC_NV25_WHAT2 0x00400b88 168 #define NVACC_WINCLIP_H_0 0x00400f00 169 #define NVACC_WINCLIP_H_1 0x00400f04 170 #define NVACC_WINCLIP_H_2 0x00400f08 171 #define NVACC_WINCLIP_H_3 0x00400f0c 172 #define NVACC_WINCLIP_H_4 0x00400f10 173 #define NVACC_WINCLIP_H_5 0x00400f14 174 #define NVACC_WINCLIP_H_6 0x00400f18 175 #define NVACC_WINCLIP_H_7 0x00400f1c 176 #define NVACC_WINCLIP_V_0 0x00400f20 177 #define NVACC_WINCLIP_V_1 0x00400f24 178 #define NVACC_WINCLIP_V_2 0x00400f28 179 #define NVACC_WINCLIP_V_3 0x00400f2c 180 #define NVACC_WINCLIP_V_4 0x00400f30 181 #define NVACC_WINCLIP_V_5 0x00400f34 182 #define NVACC_WINCLIP_V_6 0x00400f38 183 #define NVACC_WINCLIP_V_7 0x00400f3c 184 #define NVACC_NV10_XFMOD0 0x00400f40 185 #define NVACC_NV10_XFMOD1 0x00400f44 186 #define NVACC_GLOB_STAT_0 0x00400f48 187 #define NVACC_GLOB_STAT_1 0x00400f4c 188 #define NVACC_NV10_PIPEADR 0x00400f50 189 #define NVACC_NV10_PIPEDAT 0x00400f54 190 /* PGRAPH unknown registers */ 191 #define NVACC_PGWHAT_00 0x00400e00 192 #define NVACC_PGWHAT_01 0x00400e04 193 #define NVACC_PGWHAT_02 0x00400e08 194 #define NVACC_PGWHAT_03 0x00400e0c 195 #define NVACC_PGWHAT_04 0x00400e10 196 #define NVACC_PGWHAT_05 0x00400e14 197 #define NVACC_PGWHAT_06 0x00400e18 198 #define NVACC_PGWHAT_07 0x00400e1c 199 #define NVACC_PGWHAT_08 0x00400e20 200 #define NVACC_PGWHAT_09 0x00400e24 201 #define NVACC_PGWHAT_0A 0x00400e28 202 #define NVACC_PGWHAT_0B 0x00400e2c 203 #define NVACC_PGWHAT_0C 0x00400e30 204 #define NVACC_PGWHAT_0D 0x00400e34 205 #define NVACC_PGWHAT_0E 0x00400e38 206 #define NVACC_PGWHAT_0F 0x00400e3c 207 #define NVACC_PGWHAT_10 0x00400e40 208 #define NVACC_PGWHAT_11 0x00400e44 209 #define NVACC_PGWHAT_12 0x00400e48 210 #define NVACC_PGWHAT_13 0x00400e4c 211 #define NVACC_PGWHAT_14 0x00400e50 212 #define NVACC_PGWHAT_15 0x00400e54 213 #define NVACC_PGWHAT_16 0x00400e58 214 #define NVACC_PGWHAT_17 0x00400e5c 215 #define NVACC_PGWHAT_18 0x00400e60 216 #define NVACC_PGWHAT_19 0x00400e64 217 #define NVACC_PGWHAT_1A 0x00400e68 218 #define NVACC_PGWHAT_1B 0x00400e6c 219 #define NVACC_PGWHAT_1C 0x00400e70 220 #define NVACC_PGWHAT_1D 0x00400e74 221 #define NVACC_PGWHAT_1E 0x00400e78 222 #define NVACC_PGWHAT_1F 0x00400e7c 223 #define NVACC_PGWHAT_20 0x00400e80 224 #define NVACC_PGWHAT_21 0x00400e84 225 #define NVACC_PGWHAT_22 0x00400e88 226 #define NVACC_PGWHAT_23 0x00400e8c 227 #define NVACC_PGWHAT_24 0x00400e90 228 #define NVACC_PGWHAT_25 0x00400e94 229 #define NVACC_PGWHAT_26 0x00400e98 230 #define NVACC_PGWHAT_27 0x00400e9c 231 #define NVACC_PGWHAT_28 0x00400ea0 232 #define NVACC_PGWHAT_29 0x00400ea4 233 #define NVACC_PGWHAT_2A 0x00400ea8 234 /* PGRAPH cache registers */ 235 #define NVACC_CACHE1_1 0x00400160 236 #define NVACC_CACHE1_2 0x00400180 237 #define NVACC_CACHE1_3 0x004001a0 238 #define NVACC_CACHE1_4 0x004001c0 239 #define NVACC_CACHE1_5 0x004001e0 240 #define NVACC_CACHE2_1 0x00400164 241 #define NVACC_CACHE2_2 0x00400184 242 #define NVACC_CACHE2_3 0x004001a4 243 #define NVACC_CACHE2_4 0x004001c4 244 #define NVACC_CACHE2_5 0x004001e4 245 #define NVACC_CACHE3_1 0x00400168 246 #define NVACC_CACHE3_2 0x00400188 247 #define NVACC_CACHE3_3 0x004001a8 248 #define NVACC_CACHE3_4 0x004001c8 249 #define NVACC_CACHE3_5 0x004001e8 250 #define NVACC_CACHE4_1 0x0040016c 251 #define NVACC_CACHE4_2 0x0040018c 252 #define NVACC_CACHE4_3 0x004001ac 253 #define NVACC_CACHE4_4 0x004001cc 254 #define NVACC_CACHE4_5 0x004001ec 255 #define NVACC_NV10_CACHE5_1 0x00400170 256 #define NVACC_NV04_CTX_CTRL 0x00400170 257 #define NVACC_CACHE5_2 0x00400190 258 #define NVACC_CACHE5_3 0x004001b0 259 #define NVACC_CACHE5_4 0x004001d0 260 #define NVACC_CACHE5_5 0x004001f0 261 #define NVACC_NV10_CACHE6_1 0x00400174 262 #define NVACC_CACHE6_2 0x00400194 263 #define NVACC_CACHE6_3 0x004001b4 264 #define NVACC_CACHE6_4 0x004001d4 265 #define NVACC_CACHE6_5 0x004001f4 266 #define NVACC_NV10_CACHE7_1 0x00400178 267 #define NVACC_CACHE7_2 0x00400198 268 #define NVACC_CACHE7_3 0x004001b8 269 #define NVACC_CACHE7_4 0x004001d8 270 #define NVACC_CACHE7_5 0x004001f8 271 #define NVACC_NV10_CACHE8_1 0x0040017c 272 #define NVACC_CACHE8_2 0x0040019c 273 #define NVACC_CACHE8_3 0x004001bc 274 #define NVACC_CACHE8_4 0x004001dc 275 #define NVACC_CACHE8_5 0x004001fc 276 #define NVACC_NV10_CTX_SW1 0x0040014c 277 #define NVACC_NV10_CTX_SW2 0x00400150 278 #define NVACC_NV10_CTX_SW3 0x00400154 279 #define NVACC_NV10_CTX_SW4 0x00400158 280 #define NVACC_NV10_CTX_SW5 0x0040015c 281 /* engine tile registers src */ 282 #define NVACC_NV10_FBTIL0AD 0x00100240 283 #define NVACC_NV10_FBTIL0ED 0x00100244 284 #define NVACC_NV10_FBTIL0PT 0x00100248 285 #define NVACC_NV10_FBTIL0ST 0x0010024c 286 #define NVACC_NV10_FBTIL1AD 0x00100250 287 #define NVACC_NV10_FBTIL1ED 0x00100254 288 #define NVACC_NV10_FBTIL1PT 0x00100258 289 #define NVACC_NV10_FBTIL1ST 0x0010025c 290 #define NVACC_NV10_FBTIL2AD 0x00100260 291 #define NVACC_NV10_FBTIL2ED 0x00100264 292 #define NVACC_NV10_FBTIL2PT 0x00100268 293 #define NVACC_NV10_FBTIL2ST 0x0010026c 294 #define NVACC_NV10_FBTIL3AD 0x00100270 295 #define NVACC_NV10_FBTIL3ED 0x00100274 296 #define NVACC_NV10_FBTIL3PT 0x00100278 297 #define NVACC_NV10_FBTIL3ST 0x0010027c 298 #define NVACC_NV10_FBTIL4AD 0x00100280 299 #define NVACC_NV10_FBTIL4ED 0x00100284 300 #define NVACC_NV10_FBTIL4PT 0x00100288 301 #define NVACC_NV10_FBTIL4ST 0x0010028c 302 #define NVACC_NV10_FBTIL5AD 0x00100290 303 #define NVACC_NV10_FBTIL5ED 0x00100294 304 #define NVACC_NV10_FBTIL5PT 0x00100298 305 #define NVACC_NV10_FBTIL5ST 0x0010029c 306 #define NVACC_NV10_FBTIL6AD 0x001002a0 307 #define NVACC_NV10_FBTIL6ED 0x001002a4 308 #define NVACC_NV10_FBTIL6PT 0x001002a8 309 #define NVACC_NV10_FBTIL6ST 0x001002ac 310 #define NVACC_NV10_FBTIL7AD 0x001002b0 311 #define NVACC_NV10_FBTIL7ED 0x001002b4 312 #define NVACC_NV10_FBTIL7PT 0x001002b8 313 #define NVACC_NV10_FBTIL7ST 0x001002bc 314 /* engine tile registers dst */ 315 #define NVACC_NV20_WHAT_T0 0x004009a4 316 #define NVACC_NV20_WHAT_T1 0x004009a8 317 #define NVACC_NV40_WHAT_T2 0x004069a4 318 #define NVACC_NV40_WHAT_T3 0x004069a8 319 #define NVACC_NV40P_WHAT_T0 0x004009f0 320 #define NVACC_NV40P_WHAT_T1 0x004009f4 321 #define NVACC_NV40P_WHAT_T2 0x004069f0 322 #define NVACC_NV40P_WHAT_T3 0x004069f4 323 #define NVACC_NV10_TIL0AD 0x00400b00 324 #define NVACC_NV10_TIL0ED 0x00400b04 325 #define NVACC_NV10_TIL0PT 0x00400b08 326 #define NVACC_NV10_TIL0ST 0x00400b0c 327 #define NVACC_NV10_TIL1AD 0x00400b10 328 #define NVACC_NV10_TIL1ED 0x00400b14 329 #define NVACC_NV10_TIL1PT 0x00400b18 330 #define NVACC_NV10_TIL1ST 0x00400b1c 331 #define NVACC_NV10_TIL2AD 0x00400b20 332 #define NVACC_NV10_TIL2ED 0x00400b24 333 #define NVACC_NV10_TIL2PT 0x00400b28 334 #define NVACC_NV10_TIL2ST 0x00400b2c 335 #define NVACC_NV10_TIL3AD 0x00400b30 336 #define NVACC_NV10_TIL3ED 0x00400b34 337 #define NVACC_NV10_TIL3PT 0x00400b38 338 #define NVACC_NV10_TIL3ST 0x00400b3c 339 #define NVACC_NV10_TIL4AD 0x00400b40 340 #define NVACC_NV10_TIL4ED 0x00400b44 341 #define NVACC_NV10_TIL4PT 0x00400b48 342 #define NVACC_NV10_TIL4ST 0x00400b4c 343 #define NVACC_NV10_TIL5AD 0x00400b50 344 #define NVACC_NV10_TIL5ED 0x00400b54 345 #define NVACC_NV10_TIL5PT 0x00400b58 346 #define NVACC_NV10_TIL5ST 0x00400b5c 347 #define NVACC_NV10_TIL6AD 0x00400b60 348 #define NVACC_NV10_TIL6ED 0x00400b64 349 #define NVACC_NV10_TIL6PT 0x00400b68 350 #define NVACC_NV10_TIL6ST 0x00400b6c 351 #define NVACC_NV10_TIL7AD 0x00400b70 352 #define NVACC_NV10_TIL7ED 0x00400b74 353 #define NVACC_NV10_TIL7PT 0x00400b78 354 #define NVACC_NV10_TIL7ST 0x00400b7c 355 /* cache setup registers */ 356 #define NVACC_PF_INTSTAT 0x00002100 357 #define NVACC_PF_INTEN 0x00002140 358 #define NVACC_PF_RAMHT 0x00002210 359 #define NVACC_PF_RAMFC 0x00002214 360 #define NVACC_PF_RAMRO 0x00002218 361 #define NVACC_PF_CACHES 0x00002500 362 #define NVACC_PF_MODE 0x00002504 363 #define NVACC_PF_SIZE 0x0000250c 364 #define NVACC_PF_CACH0_PSH0 0x00003000 365 #define NVACC_PF_CACH0_PUL0 0x00003050 366 #define NVACC_PF_CACH0_PUL1 0x00003054 367 #define NVACC_PF_CACH1_PSH0 0x00003200 368 #define NVACC_PF_CACH1_PSH1 0x00003204 369 #define NVACC_PF_CACH1_DMAS 0x00003220 370 #define NVACC_PF_CACH1_DMAF 0x00003224 371 #define NVACC_PF_CACH1_DMAI 0x0000322c 372 #define NVACC_PF_CACH1_DMAC 0x00003230 373 #define NVACC_PF_CACH1_DMAP 0x00003240 374 #define NVACC_PF_CACH1_DMAG 0x00003244 375 #define NVACC_PF_CACH1_PUL0 0x00003250 376 #define NVACC_PF_CACH1_PUL1 0x00003254 377 #define NVACC_PF_CACH1_HASH 0x00003258 378 #define NVACC_PF_CACH1_ENG 0x00003280 379 /* Ptimer registers */ 380 #define NVACC_PT_INTSTAT 0x00009100 381 #define NVACC_PT_INTEN 0x00009140 382 #define NVACC_PT_NUMERATOR 0x00009200 383 #define NVACC_PT_DENOMINATR 0x00009210 384 /* used PRAMIN registers */ 385 #define NVACC_PR_CTX0_R 0x00711400 386 #define NVACC_PR_CTX1_R 0x00711404 387 #define NVACC_PR_CTX2_R 0x00711408 388 #define NVACC_PR_CTX3_R 0x0071140c 389 #define NVACC_PR_CTX0_0 0x00711420 390 #define NVACC_PR_CTX1_0 0x00711424 391 #define NVACC_PR_CTX2_0 0x00711428 392 #define NVACC_PR_CTX3_0 0x0071142c 393 #define NVACC_PR_CTX0_1 0x00711430 394 #define NVACC_PR_CTX1_1 0x00711434 395 #define NVACC_PR_CTX2_1 0x00711438 396 #define NVACC_PR_CTX3_1 0x0071143c 397 #define NVACC_PR_CTX0_2 0x00711440 398 #define NVACC_PR_CTX1_2 0x00711444 399 #define NVACC_PR_CTX2_2 0x00711448 400 #define NVACC_PR_CTX3_2 0x0071144c 401 #define NVACC_PR_CTX0_3 0x00711450 402 #define NVACC_PR_CTX1_3 0x00711454 403 #define NVACC_PR_CTX2_3 0x00711458 404 #define NVACC_PR_CTX3_3 0x0071145c 405 #define NVACC_PR_CTX0_4 0x00711460 406 #define NVACC_PR_CTX1_4 0x00711464 407 #define NVACC_PR_CTX2_4 0x00711468 408 #define NVACC_PR_CTX3_4 0x0071146c 409 #define NVACC_PR_CTX0_5 0x00711470 410 #define NVACC_PR_CTX1_5 0x00711474 411 #define NVACC_PR_CTX2_5 0x00711478 412 #define NVACC_PR_CTX3_5 0x0071147c 413 #define NVACC_PR_CTX0_6 0x00711480 414 #define NVACC_PR_CTX1_6 0x00711484 415 #define NVACC_PR_CTX2_6 0x00711488 416 #define NVACC_PR_CTX3_6 0x0071148c 417 #define NVACC_PR_CTX0_7 0x00711490 418 #define NVACC_PR_CTX1_7 0x00711494 419 #define NVACC_PR_CTX2_7 0x00711498 420 #define NVACC_PR_CTX3_7 0x0071149c 421 #define NVACC_PR_CTX0_8 0x007114a0 422 #define NVACC_PR_CTX1_8 0x007114a4 423 #define NVACC_PR_CTX2_8 0x007114a8 424 #define NVACC_PR_CTX3_8 0x007114ac 425 #define NVACC_PR_CTX0_9 0x007114b0 426 #define NVACC_PR_CTX1_9 0x007114b4 427 #define NVACC_PR_CTX2_9 0x007114b8 428 #define NVACC_PR_CTX3_9 0x007114bc 429 #define NVACC_PR_CTX0_A 0x007114c0 430 #define NVACC_PR_CTX1_A 0x007114c4 /* not used */ 431 #define NVACC_PR_CTX2_A 0x007114c8 432 #define NVACC_PR_CTX3_A 0x007114cc 433 #define NVACC_PR_CTX0_B 0x007114d0 434 #define NVACC_PR_CTX1_B 0x007114d4 435 #define NVACC_PR_CTX2_B 0x007114d8 436 #define NVACC_PR_CTX3_B 0x007114dc 437 #define NVACC_PR_CTX0_C 0x007114e0 438 #define NVACC_PR_CTX1_C 0x007114e4 439 #define NVACC_PR_CTX2_C 0x007114e8 440 #define NVACC_PR_CTX3_C 0x007114ec 441 #define NVACC_PR_CTX0_D 0x007114f0 442 #define NVACC_PR_CTX1_D 0x007114f4 443 #define NVACC_PR_CTX2_D 0x007114f8 444 #define NVACC_PR_CTX3_D 0x007114fc 445 #define NVACC_PR_CTX0_E 0x00711500 446 #define NVACC_PR_CTX1_E 0x00711504 447 #define NVACC_PR_CTX2_E 0x00711508 448 #define NVACC_PR_CTX3_E 0x0071150c 449 #define NVACC_PR_CTX0_F 0x00711510 450 #define NVACC_PR_CTX1_F 0x00711514 451 #define NVACC_PR_CTX2_F 0x00711518 452 #define NVACC_PR_CTX3_F 0x0071151c 453 #define NVACC_PR_CTX0_10 0x00711520 454 #define NVACC_PR_CTX1_10 0x00711524 455 #define NVACC_PR_CTX2_10 0x00711528 456 #define NVACC_PR_CTX3_10 0x0071152c 457 /* used RAMHT registers (hash-table) */ 458 #define NVACC_HT_HANDL_00 0x00710000 459 #define NVACC_HT_VALUE_00 0x00710004 460 #define NVACC_HT_HANDL_01 0x00710008 461 #define NVACC_HT_VALUE_01 0x0071000c 462 #define NVACC_HT_HANDL_02 0x00710010 463 #define NVACC_HT_VALUE_02 0x00710014 464 #define NVACC_HT_HANDL_03 0x00710018 465 #define NVACC_HT_VALUE_03 0x0071001c 466 #define NVACC_HT_HANDL_04 0x00710020 467 #define NVACC_HT_VALUE_04 0x00710024 468 #define NVACC_HT_HANDL_05 0x00710028 469 #define NVACC_HT_VALUE_05 0x0071002c 470 #define NVACC_HT_HANDL_06 0x00710030 471 #define NVACC_HT_VALUE_06 0x00710034 472 #define NVACC_HT_HANDL_10 0x00710080 473 #define NVACC_HT_VALUE_10 0x00710084 474 #define NVACC_HT_HANDL_11 0x00710088 475 #define NVACC_HT_VALUE_11 0x0071008c 476 #define NVACC_HT_HANDL_12 0x00710090 477 #define NVACC_HT_VALUE_12 0x00710094 478 #define NVACC_HT_HANDL_13 0x00710098 479 #define NVACC_HT_VALUE_13 0x0071009c 480 #define NVACC_HT_HANDL_14 0x007100a0 481 #define NVACC_HT_VALUE_14 0x007100a4 482 #define NVACC_HT_HANDL_15 0x007100a8 483 #define NVACC_HT_VALUE_15 0x007100ac 484 #define NVACC_HT_HANDL_16 0x007100b0 485 #define NVACC_HT_VALUE_16 0x007100b4 486 #define NVACC_HT_HANDL_17 0x007100b8 487 #define NVACC_HT_VALUE_17 0x007100bc 488 489 /* acc engine fifo setup registers (for function_register 'mappings') */ 490 #define NVACC_FIFO 0x00800000 491 #define NVACC_FIFO_CH0 0x00800000 492 #define NVACC_FIFO_CH1 0x00802000 493 #define NVACC_FIFO_CH2 0x00804000 494 #define NVACC_FIFO_CH3 0x00806000 495 #define NVACC_FIFO_CH4 0x00808000 496 #define NVACC_FIFO_CH5 0x0080a000 497 #define NVACC_FIFO_CH6 0x0080c000 498 #define NVACC_FIFO_CH7 0x0080e000 499 500 /* Nvidia PCI direct registers */ 501 #define NV32_PWRUPCTRL 0x00000200 502 #define NV32_DUALHEAD_CTRL 0x000010f0//verify!!! 503 #define NV8_MISCW 0x000c03c2 504 #define NV8_MISCR 0x000c03cc 505 #define NV8_VSE2 0x000c03c3 506 #define NV8_SEQIND 0x000c03c4 507 #define NV16_SEQIND 0x000c03c4 508 #define NV8_SEQDAT 0x000c03c5 509 #define NV8_GRPHIND 0x000c03ce 510 #define NV16_GRPHIND 0x000c03ce 511 #define NV8_GRPHDAT 0x000c03cf 512 513 /* bootstrap info registers */ 514 #define NV32_NV4STRAPINFO 0x00100000 515 #define NV32_PFB_CONFIG_0 0x00100200 516 #define NV32_PFB_CONFIG_1 0x00100204 517 #define NV32_NV10STRAPINFO 0x0010020c 518 #define NV32_FB_MRS1 0x001002c0 519 #define NV32_FB_MRS2 0x001002c8 520 #define NV32_PFB_CLS_PAGE2 0x0010033c 521 #define NV32_NVSTRAPINFO2 0x00101000 522 523 /* registers needed for 'coldstart' */ 524 #define NV32_PFB_DEBUG_0 0x00100080 525 #define NV32_PFB_REFCTRL 0x00100210 526 #define NV32_COREPLL 0x00680500 527 #define NV32_MEMPLL 0x00680504 528 #define NV32_PLL_CTRL 0x00680510 529 #define NV32_COREPLL2 0x00680570 /* NV31, NV36 only */ 530 #define NV32_MEMPLL2 0x00680574 /* NV31, NV36 only */ 531 #define NV32_CONFIG 0x00600804 532 533 /* primary head */ 534 #define NV8_ATTRINDW 0x006013c0 535 #define NV8_ATTRDATW 0x006013c0 536 #define NV8_ATTRDATR 0x006013c1 537 #define NV8_CRTCIND 0x006013d4 538 #define NV16_CRTCIND 0x006013d4 539 #define NV8_CRTCDAT 0x006013d5 540 #define NV8_INSTAT1 0x006013da 541 #define NV32_NV10FBSTADD32 0x00600800 542 #define NV32_RASTER 0x00600808 543 #define NV32_NV10CURADD32 0x0060080c 544 #define NV32_CURCONF 0x00600810 545 #define NV32_PANEL_PWR 0x0060081c 546 #define NV32_FUNCSEL 0x00600860 547 548 /* secondary head */ 549 #define NV8_ATTR2INDW 0x006033c0 550 #define NV8_ATTR2DATW 0x006033c0 551 #define NV8_ATTR2DATR 0x006033c1 552 #define NV8_CRTC2IND 0x006033d4 553 #define NV16_CRTC2IND 0x006033d4 554 #define NV8_CRTC2DAT 0x006033d5 555 #define NV8_2INSTAT1 0x006033da//verify!!! 556 #define NV32_NV10FB2STADD32 0x00602800 557 #define NV32_RASTER2 0x00602808 558 #define NV32_NV10CUR2ADD32 0x0060280c 559 #define NV32_2CURCONF 0x00602810 560 #define NV32_2PANEL_PWR 0x0060281c//verify!!! 561 #define NV32_2FUNCSEL 0x00602860 562 563 /* Nvidia DAC direct registers (standard VGA palette RAM registers) */ 564 /* primary head */ 565 #define NV8_PALMASK 0x006813c6 566 #define NV8_PALINDR 0x006813c7 567 #define NV8_PALINDW 0x006813c8 568 #define NV8_PALDATA 0x006813c9 569 /* secondary head */ 570 #define NV8_PAL2MASK 0x006833c6 571 #define NV8_PAL2INDR 0x006833c7 572 #define NV8_PAL2INDW 0x006833c8 573 #define NV8_PAL2DATA 0x006833c9 574 575 /* Nvidia PCI direct DAC registers (32bit) */ 576 /* primary head */ 577 #define NVDAC_CURPOS 0x00680300 578 #define NVDAC_NV10_CURSYNC 0x00680404 579 #define NVDAC_PIXPLLC 0x00680508 580 #define NVDAC_PLLSEL 0x0068050c 581 #define NVDAC_OUTPUT 0x0068052c 582 #define NVDAC_PIXPLLC2 0x00680578 583 #define NVDAC_GENCTRL 0x00680600 584 #define NVDAC_TSTCTRL 0x00680608 585 #define NVDAC_TSTDATA 0x00680610 586 #define NVDAC_TV_SETUP 0x00680700 587 /* (flatpanel registers: confirmed for TNT2 and up) */ 588 #define NVDAC_FP_VDISPEND 0x00680800 589 #define NVDAC_FP_VTOTAL 0x00680804 590 #define NVDAC_FP_VCRTC 0x00680808 591 #define NVDAC_FP_VSYNC_S 0x0068080c 592 #define NVDAC_FP_VSYNC_E 0x00680810 593 #define NVDAC_FP_VVALID_S 0x00680814 594 #define NVDAC_FP_VVALID_E 0x00680818 595 #define NVDAC_FP_HDISPEND 0x00680820 596 #define NVDAC_FP_HTOTAL 0x00680824 597 #define NVDAC_FP_HCRTC 0x00680828 598 #define NVDAC_FP_HSYNC_S 0x0068082c 599 #define NVDAC_FP_HSYNC_E 0x00680830 600 #define NVDAC_FP_HVALID_S 0x00680834 601 #define NVDAC_FP_HVALID_E 0x00680838 602 #define NVDAC_FP_CHKSUM 0x00680840 603 #define NVDAC_FP_TST_CTRL 0x00680844 604 #define NVDAC_FP_TG_CTRL 0x00680848 605 #define NVDAC_FP_DEBUG0 0x00680880 606 #define NVDAC_FP_DEBUG1 0x00680884 607 #define NVDAC_FP_DEBUG2 0x00680888 608 #define NVDAC_FP_DEBUG3 0x0068088c 609 /* secondary head */ 610 #define NVDAC2_CURPOS 0x00682300 611 #define NVDAC2_NV10_CURSYNC 0x00682404 612 #define NVDAC2_PIXPLLC 0x00680520 613 #define NVDAC2_OUTPUT 0x0068252c 614 #define NVDAC2_PIXPLLC2 0x0068057c 615 #define NVDAC2_GENCTRL 0x00682600 616 #define NVDAC2_TSTCTRL 0x00682608 617 #define NVDAC2_TV_SETUP 0x00682700 618 /* (flatpanel registers) */ 619 #define NVDAC2_FP_VDISPEND 0x00682800 620 #define NVDAC2_FP_VTOTAL 0x00682804 621 #define NVDAC2_FP_VCRTC 0x00682808 622 #define NVDAC2_FP_VSYNC_S 0x0068280c 623 #define NVDAC2_FP_VSYNC_E 0x00682810 624 #define NVDAC2_FP_VVALID_S 0x00682814 625 #define NVDAC2_FP_VVALID_E 0x00682818 626 #define NVDAC2_FP_HDISPEND 0x00682820 627 #define NVDAC2_FP_HTOTAL 0x00682824 628 #define NVDAC2_FP_HCRTC 0x00682828 629 #define NVDAC2_FP_HSYNC_S 0x0068282c 630 #define NVDAC2_FP_HSYNC_E 0x00682830 631 #define NVDAC2_FP_HVALID_S 0x00682834 632 #define NVDAC2_FP_HVALID_E 0x00682838 633 #define NVDAC2_FP_CHKSUM 0x00682840 634 #define NVDAC2_FP_TST_CTRL 0x00682844 635 #define NVDAC2_FP_TG_CTRL 0x00682848 636 #define NVDAC2_FP_DEBUG0 0x00682880 637 #define NVDAC2_FP_DEBUG1 0x00682884 638 #define NVDAC2_FP_DEBUG2 0x00682888 639 #define NVDAC2_FP_DEBUG3 0x0068288c 640 641 /* Nvidia CRTC indexed registers */ 642 /* VGA standard registers: */ 643 #define NVCRTCX_HTOTAL 0x00 644 #define NVCRTCX_HDISPE 0x01 645 #define NVCRTCX_HBLANKS 0x02 646 #define NVCRTCX_HBLANKE 0x03 647 #define NVCRTCX_HSYNCS 0x04 648 #define NVCRTCX_HSYNCE 0x05 649 #define NVCRTCX_VTOTAL 0x06 650 #define NVCRTCX_OVERFLOW 0x07 651 #define NVCRTCX_PRROWSCN 0x08 652 #define NVCRTCX_MAXSCLIN 0x09 653 #define NVCRTCX_VGACURCTRL 0x0a 654 #define NVCRTCX_FBSTADDH 0x0c 655 #define NVCRTCX_FBSTADDL 0x0d 656 #define NVCRTCX_VSYNCS 0x10 657 #define NVCRTCX_VSYNCE 0x11 658 #define NVCRTCX_VDISPE 0x12 659 #define NVCRTCX_PITCHL 0x13 660 #define NVCRTCX_VBLANKS 0x15 661 #define NVCRTCX_VBLANKE 0x16 662 #define NVCRTCX_MODECTL 0x17 663 #define NVCRTCX_LINECOMP 0x18 664 /* Nvidia specific registers: */ 665 #define NVCRTCX_REPAINT0 0x19 666 #define NVCRTCX_REPAINT1 0x1a 667 #define NVCRTCX_FIFO 0x1b 668 #define NVCRTCX_LOCK 0x1f 669 #define NVCRTCX_FIFO_LWM 0x20 670 #define NVCRTCX_BUFFER 0x21 671 #define NVCRTCX_LSR 0x25 672 #define NVCRTCX_PIXEL 0x28 673 #define NVCRTCX_HEB 0x2d 674 #define NVCRTCX_CURCTL2 0x2f 675 #define NVCRTCX_CURCTL1 0x30 676 #define NVCRTCX_CURCTL0 0x31 677 #define NVCRTCX_LCD 0x33 678 #define NVCRTCX_RD_I2CBUS_1 0x36 679 #define NVCRTCX_WR_I2CBUS_1 0x37 680 #define NVCRTCX_RMA 0x38 681 #define NVCRTCX_INTERLACE 0x39 682 #define NVCRTCX_TREG 0x3d 683 #define NVCRTCX_RD_I2CBUS_0 0x3e 684 #define NVCRTCX_WR_I2CBUS_0 0x3f 685 #define NVCRTCX_EXTRA 0x41 686 #define NVCRTCX_OWNER 0x44 687 #define NVCRTCX_FP_HTIMING 0x53 688 #define NVCRTCX_FP_VTIMING 0x54 689 #define NVCRTCX_0x59 0x59 690 #define NVCRTCX_0x9f 0x9f 691 692 /* Nvidia ATTRIBUTE indexed registers */ 693 /* VGA standard registers: */ 694 #define NVATBX_MODECTL 0x10 695 #define NVATBX_OSCANCOLOR 0x11 696 #define NVATBX_COLPLANE_EN 0x12 697 #define NVATBX_HORPIXPAN 0x13 698 #define NVATBX_COLSEL 0x14 699 700 /* Nvidia SEQUENCER indexed registers */ 701 /* VGA standard registers: */ 702 #define NVSEQX_RESET 0x00 703 #define NVSEQX_CLKMODE 0x01 704 #define NVSEQX_MEMMODE 0x04 705 706 /* Nvidia GRAPHICS indexed registers */ 707 /* VGA standard registers: */ 708 #define NVGRPHX_ENSETRESET 0x01 709 #define NVGRPHX_DATAROTATE 0x03 710 #define NVGRPHX_READMAPSEL 0x04 711 #define NVGRPHX_MODE 0x05 712 #define NVGRPHX_MISC 0x06 713 #define NVGRPHX_BITMASK 0x08 714 715 /* Nvidia BES (Back End Scaler) registers (< NV10, including NV03, so RIVA128(ZX)) */ 716 #define NVBES_NV04_INTE 0x00680140 717 #define NVBES_NV04_ISCALVH 0x00680200 718 #define NVBES_NV04_CTRL_V 0x00680204 719 #define NVBES_NV04_CTRL_H 0x00680208 720 #define NVBES_NV04_OE_STATE 0x00680224 721 #define NVBES_NV04_SU_STATE 0x00680228 722 #define NVBES_NV04_RM_STATE 0x0068022c 723 #define NVBES_NV04_DSTREF 0x00680230 724 #define NVBES_NV04_DSTSIZE 0x00680234 725 #define NVBES_NV04_FIFOTHRS 0x00680238 726 #define NVBES_NV04_FIFOBURL 0x0068023c 727 #define NVBES_NV04_COLKEY 0x00680240 728 #define NVBES_NV04_GENCTRL 0x00680244 729 #define NVBES_NV04_RED_AMP 0x00680280 730 #define NVBES_NV04_GRN_AMP 0x00680284 731 #define NVBES_NV04_BLU_AMP 0x00680288 732 #define NVBES_NV04_SAT 0x0068028c 733 /* buffer 0 */ 734 #define NVBES_NV04_0BUFADR 0x0068020c 735 #define NVBES_NV04_0SRCPTCH 0x00680214 736 #define NVBES_NV04_0OFFSET 0x0068021c 737 /* buffer 1 */ 738 #define NVBES_NV04_1BUFADR 0x00680210 739 #define NVBES_NV04_1SRCPTCH 0x00680218 740 #define NVBES_NV04_1OFFSET 0x00680220 741 742 /* Nvidia BES (Back End Scaler) registers (>= NV10) */ 743 #define NVBES_NV10_INTE 0x00008140 744 #define NVBES_NV10_BUFSEL 0x00008700 745 #define NVBES_NV10_GENCTRL 0x00008704 746 #define NVBES_NV10_COLKEY 0x00008b00 747 /* buffer 0 */ 748 #define NVBES_NV10_0BUFADR 0x00008900 749 #define NVBES_NV10_0MEMMASK 0x00008908 750 #define NVBES_NV10_0BRICON 0x00008910 751 #define NVBES_NV10_0SAT 0x00008918 752 #define NVBES_NV10_0OFFSET 0x00008920 753 #define NVBES_NV10_0SRCSIZE 0x00008928 754 #define NVBES_NV10_0SRCREF 0x00008930 755 #define NVBES_NV10_0ISCALH 0x00008938 756 #define NVBES_NV10_0ISCALV 0x00008940 757 #define NVBES_NV10_0DSTREF 0x00008948 758 #define NVBES_NV10_0DSTSIZE 0x00008950 759 #define NVBES_NV10_0SRCPTCH 0x00008958 760 /* buffer 1 */ 761 #define NVBES_NV10_1BUFADR 0x00008904 762 #define NVBES_NV10_1MEMMASK 0x0000890c 763 #define NVBES_NV10_1BRICON 0x00008914 764 #define NVBES_NV10_1SAT 0x0000891c 765 #define NVBES_NV10_1OFFSET 0x00008924 766 #define NVBES_NV10_1SRCSIZE 0x0000892c 767 #define NVBES_NV10_1SRCREF 0x00008934 768 #define NVBES_NV10_1ISCALH 0x0000893c 769 #define NVBES_NV10_1ISCALV 0x00008944 770 #define NVBES_NV10_1DSTREF 0x0000894c 771 #define NVBES_NV10_1DSTSIZE 0x00008954 772 #define NVBES_NV10_1SRCPTCH 0x0000895c 773 /* Nvidia MPEG2 hardware decoder (GeForce4MX only) */ 774 #define NVBES_DEC_GENCTRL 0x00001588 775 /* unknown registers */ 776 #define NV32_NV44_WHAT10 0x00001700 777 #define NV32_NV44_WHAT11 0x00001704 778 #define NV32_NV44_WHAT12 0x00001708 779 #define NV32_NV44_WHAT13 0x0000170c 780 781 /* Macros for convenient accesses to the NV chips */ 782 #define NV_REG8(r_) ((vuint8 *)regs)[(r_)] 783 #define NV_REG16(r_) ((vuint16 *)regs)[(r_) >> 1] 784 #define NV_REG32(r_) ((vuint32 *)regs)[(r_) >> 2] 785 786 /* read and write to PCI config space */ 787 #define CFGR(A) (*(nv_pci_access.offset=NVCFG_##A, ioctl(fd,NV_GET_PCI, &nv_pci_access,sizeof(nv_pci_access)), &nv_pci_access.value)) 788 #define CFGW(A,B) (nv_pci_access.offset=NVCFG_##A, nv_pci_access.value = B, ioctl(fd,NV_SET_PCI,&nv_pci_access,sizeof(nv_pci_access))) 789 790 /* read and write from ISA I/O space */ 791 #define ISAWB(A,B)(nv_isa_access.adress=A, nv_isa_access.data = (uint8)B, nv_isa_access.size = 1, ioctl(fd,NV_ISA_OUT, &nv_isa_access,sizeof(nv_isa_access))) 792 #define ISAWW(A,B)(nv_isa_access.adress=A, nv_isa_access.data = B, nv_isa_access.size = 2, ioctl(fd,NV_ISA_OUT, &nv_isa_access,sizeof(nv_isa_access))) 793 #define ISARB(A) (nv_isa_access.adress=A, ioctl(fd,NV_ISA_IN, &nv_isa_access,sizeof(nv_isa_access)), (uint8)nv_isa_access.data) 794 #define ISARW(A) (nv_isa_access.adress=A, ioctl(fd,NV_ISA_IN, &nv_isa_access,sizeof(nv_isa_access)), nv_isa_access.data) 795 796 /* read and write from the dac registers */ 797 #define DACR(A) (NV_REG32(NVDAC_##A)) 798 #define DACW(A,B) (NV_REG32(NVDAC_##A)=B) 799 800 /* read and write from the secondary dac registers */ 801 #define DAC2R(A) (NV_REG32(NVDAC2_##A)) 802 #define DAC2W(A,B) (NV_REG32(NVDAC2_##A)=B) 803 804 /* read and write from the backend scaler registers */ 805 #define BESR(A) (NV_REG32(NVBES_##A)) 806 #define BESW(A,B) (NV_REG32(NVBES_##A)=B) 807 808 /* read and write from CRTC indexed registers */ 809 #define CRTCW(A,B)(NV_REG16(NV16_CRTCIND) = ((NVCRTCX_##A) | ((B) << 8))) 810 #define CRTCR(A) (NV_REG8(NV8_CRTCIND) = (NVCRTCX_##A), NV_REG8(NV8_CRTCDAT)) 811 812 /* read and write from second CRTC indexed registers */ 813 #define CRTC2W(A,B)(NV_REG16(NV16_CRTC2IND) = ((NVCRTCX_##A) | ((B) << 8))) 814 #define CRTC2R(A) (NV_REG8(NV8_CRTC2IND) = (NVCRTCX_##A), NV_REG8(NV8_CRTC2DAT)) 815 816 /* read and write from ATTRIBUTE indexed registers */ 817 #define ATBW(A,B)(NV_REG8(NV8_INSTAT1), NV_REG8(NV8_ATTRINDW) = ((NVATBX_##A) | 0x20), NV_REG8(NV8_ATTRDATW) = (B)) 818 #define ATBR(A) (NV_REG8(NV8_INSTAT1), NV_REG8(NV8_ATTRINDW) = ((NVATBX_##A) | 0x20), NV_REG8(NV8_ATTRDATR)) 819 820 /* read and write from ATTRIBUTE indexed registers */ 821 #define ATB2W(A,B)(NV_REG8(NV8_INSTAT1), NV_REG8(NV8_ATTR2INDW) = ((NVATBX_##A) | 0x20), NV_REG8(NV8_ATTR2DATW) = (B)) 822 #define ATB2R(A) (NV_REG8(NV8_INSTAT1), NV_REG8(NV8_ATTR2INDW) = ((NVATBX_##A) | 0x20), NV_REG8(NV8_ATTR2DATR)) 823 824 /* read and write from SEQUENCER indexed registers */ 825 #define SEQW(A,B)(NV_REG16(NV16_SEQIND) = ((NVSEQX_##A) | ((B) << 8))) 826 #define SEQR(A) (NV_REG8(NV8_SEQIND) = (NVSEQX_##A), NV_REG8(NV8_SEQDAT)) 827 828 /* read and write from PCI GRAPHICS indexed registers */ 829 #define GRPHW(A,B)(NV_REG16(NV16_GRPHIND) = ((NVGRPHX_##A) | ((B) << 8))) 830 #define GRPHR(A) (NV_REG8(NV8_GRPHIND) = (NVGRPHX_##A), NV_REG8(NV8_GRPHDAT)) 831 832 /* read and write from the acceleration engine registers */ 833 #define ACCR(A) (NV_REG32(NVACC_##A)) 834 #define ACCW(A,B) (NV_REG32(NVACC_##A)=B) 835