1 /* 2 Copyright 1999, Be Incorporated. All Rights Reserved. 3 This file may be used under the terms of the Be Sample Code License. 4 5 Other authors: 6 Mark Watson; 7 Apsed; 8 Rudolf Cornelissen 10/2002-4/2006. 9 */ 10 11 #ifndef DRIVERINTERFACE_H 12 #define DRIVERINTERFACE_H 13 14 #include <Accelerant.h> 15 #include "video_overlay.h" 16 #include <Drivers.h> 17 #include <PCI.h> 18 #include <OS.h> 19 #include "AGP.h" 20 21 #define DRIVER_PREFIX "nv" // apsed 22 #define DEVICE_FORMAT "%04x_%04x_%02x%02x%02x" // apsed 23 24 /* 25 Internal driver state (also for sharing info between driver and accelerant) 26 */ 27 #if defined(__cplusplus) 28 extern "C" { 29 #endif 30 31 typedef struct { 32 sem_id sem; 33 int32 ben; 34 } benaphore; 35 36 #define INIT_BEN(x) x.sem = create_sem(0, "NV "#x" benaphore"); x.ben = 0; 37 #define AQUIRE_BEN(x) if((atomic_add(&(x.ben), 1)) >= 1) acquire_sem(x.sem); 38 #define RELEASE_BEN(x) if((atomic_add(&(x.ben), -1)) > 1) release_sem(x.sem); 39 #define DELETE_BEN(x) delete_sem(x.sem); 40 41 42 #define NV_PRIVATE_DATA_MAGIC 0x0009 /* a private driver rev, of sorts */ 43 44 /* dualhead extensions to flags */ 45 #define DUALHEAD_OFF (0<<6) 46 #define DUALHEAD_CLONE (1<<6) 47 #define DUALHEAD_ON (2<<6) 48 #define DUALHEAD_SWITCH (3<<6) 49 #define DUALHEAD_BITS (3<<6) 50 #define DUALHEAD_CAPABLE (1<<8) 51 #define TV_BITS (3<<9) 52 #define TV_MON (0<<9 53 #define TV_PAL (1<<9) 54 #define TV_NTSC (2<<9) 55 #define TV_CAPABLE (1<<11) 56 #define TV_VIDEO (1<<12) 57 #define TV_PRIMARY (1<<13) 58 59 #define SKD_MOVE_CURSOR 0x00000001 60 #define SKD_PROGRAM_CLUT 0x00000002 61 #define SKD_SET_START_ADDR 0x00000004 62 #define SKD_SET_CURSOR 0x00000008 63 #define SKD_HANDLER_INSTALLED 0x80000000 64 65 enum { 66 NV_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1, 67 NV_GET_PCI, 68 NV_SET_PCI, 69 NV_DEVICE_NAME, 70 NV_RUN_INTERRUPTS, 71 NV_GET_NTH_AGP_INFO, 72 NV_ENABLE_AGP, 73 NV_ISA_OUT, 74 NV_ISA_IN 75 }; 76 77 /* card_type in order of date of NV chip design */ 78 enum { 79 NV04 = 0, 80 NV05, 81 NV05M64, 82 NV06, 83 NV10, 84 NV11, 85 NV11M, 86 NV15, 87 NV17, 88 NV17M, 89 NV18, 90 NV18M, 91 NV20, 92 NV25, 93 NV28, 94 NV30, 95 NV31, 96 NV34, 97 NV35, 98 NV36, 99 NV38, 100 NV40, 101 NV41, 102 NV43, 103 NV44, 104 NV45, 105 G70, 106 G71, 107 G72, 108 G73 109 }; 110 111 /* card_arch in order of date of NV chip design */ 112 enum { 113 NV04A = 0, 114 NV10A, 115 NV20A, 116 NV30A, 117 NV40A 118 }; 119 120 /* handles to pre-defined engine commands */ 121 #define NV_ROP5_SOLID 0x00000000 /* 2D */ 122 #define NV_IMAGE_BLACK_RECTANGLE 0x00000001 /* 2D/3D */ 123 #define NV_IMAGE_PATTERN 0x00000002 /* 2D */ 124 #define NV_SCALED_IMAGE_FROM_MEMORY 0x00000003 /* 2D */ 125 #define NV4_SURFACE 0x00000010 /* 2D */ 126 #define NV10_CONTEXT_SURFACES_2D 0x00000010 /* 2D */ 127 #define NV_IMAGE_BLIT 0x00000011 /* 2D */ 128 #define NV12_IMAGE_BLIT 0x00000011 /* 2D */ 129 /* fixme: 130 * never use NV3_GDI_RECTANGLE_TEXT for DMA acceleration: 131 * There's a hardware fault in the input->output colorspace conversion here. 132 * Besides, in NV40 and up this command nolonger exists. Both 'facts' are confirmed 133 * by testing. 134 */ 135 //#define NV3_GDI_RECTANGLE_TEXT 0x00000012 /* 2D */ 136 #define NV4_GDI_RECTANGLE_TEXT 0x00000012 /* 2D */ 137 #define NV4_CONTEXT_SURFACES_ARGB_ZS 0x00000013 /* 3D */ 138 #define NV10_CONTEXT_SURFACES_ARGB_ZS 0x00000013 /* 3D */ 139 #define NV4_DX5_TEXTURE_TRIANGLE 0x00000014 /* 3D */ 140 #define NV10_DX5_TEXTURE_TRIANGLE 0x00000014 /* 3D */ 141 #define NV4_DX6_MULTI_TEXTURE_TRIANGLE 0x00000015 /* unused (yet?) */ 142 #define NV10_DX6_MULTI_TEXTURE_TRIANGLE 0x00000015 /* unused (yet?) */ 143 #define NV1_RENDER_SOLID_LIN 0x00000016 /* 2D: unused */ 144 145 /* max. number of overlay buffers */ 146 #define MAXBUFFERS 3 147 148 //----------------------------------------------------------------------------------- 149 /* safety byte-offset from end of cardRAM for preventing acceleration engine crashes 150 * caused by the existance of DMA engine command buffers in cardRAM and/or fifo 151 * channel engine command re-assigning on-the-fly */ 152 153 /* pre-NV40 notes: 154 * - we need at least 70kB distance from the end of RAM for fifo-reassigning 'bug' 155 * (confirmed on a TNT1); 156 * - keep extra failsafe room to prevent malfunctioning apps from crashing engine. */ 157 #define PRE_NV40_OFFSET 80 * 1024 158 159 /* NV40 and higher notes: 160 * - we need at least 416kB distance from the DMA command buffer: 161 * If you get too close to the DMA command buffer on NV40 and NV43 at least (both 162 * confirmed), the source DMA instance will mess-up for at least engine command 163 * NV_IMAGE_BLIT and NV12_IMAGE_BLIT; 164 * - we need at least ???kB distance from the end of RAM for fifo-reassigning 'bug' 165 * (fixme: unknown yet because fifo assignment switching isn't used here atm); 166 * - keep extra failsafe room to prevent malfunctioning apps from crashing engine. */ 167 #define NV40_PLUS_OFFSET 512 * 1024 168 169 /* fifo re-assigning bug definition: 170 * if the fifo assignment is changed while at the same time card memory in the 171 * dangerous region is being accessed by some application, the engine will crash. 172 * This bug applies for both PIO and DMA mode acceleration! */ 173 174 /* source-DMA instance bug definition: 175 * if card memory in the dangerous region is being accessed by some application while 176 * a DMA command buffer exists in the same memory (though in a different place), 177 * the engine will crash. */ 178 //----------------------------------------------------------------------------------- 179 180 /* internal used info on overlay buffers */ 181 typedef struct { 182 uint16 slopspace; 183 uint32 size; 184 } int_buf_info; 185 186 typedef struct { // apsed, see comments in nv.settings 187 // for driver 188 char accelerant[B_FILE_NAME_LENGTH]; 189 char primary[B_FILE_NAME_LENGTH]; 190 bool dumprom; 191 // for accelerant 192 uint32 logmask; 193 uint32 memory; 194 uint32 tv_output; 195 bool usebios; 196 bool hardcursor; 197 bool switchhead; 198 bool force_pci; 199 bool unhide_fw; 200 bool pgm_panel; 201 bool dma_acc; 202 bool vga_on_tv; 203 bool force_sync; 204 bool force_ws; 205 uint32 gpu_clk; 206 uint32 ram_clk; 207 } nv_settings; 208 209 /* shared info */ 210 typedef struct { 211 /* a few ID things */ 212 uint16 vendor_id; /* PCI vendor ID, from pci_info */ 213 uint16 device_id; /* PCI device ID, from pci_info */ 214 uint8 revision; /* PCI device revsion, from pci_info */ 215 uint8 bus; /* PCI bus number, from pci_info */ 216 uint8 device; /* PCI device number on bus, from pci_info */ 217 uint8 function; /* PCI function number in device, from pci_info */ 218 219 /* used to return status for INIT_ACCELERANT and CLONE_ACCELERANT */ 220 bool accelerant_in_use; 221 222 /* bug workaround for 4.5.0 */ 223 uint32 use_clone_bugfix; /*for 4.5.0, cloning of physical memory does not work*/ 224 uint32 * clone_bugfix_regs; 225 226 /*memory mappings*/ 227 area_id regs_area; /* Kernel's area_id for the memory mapped registers. 228 It will be cloned into the accelerant's address 229 space. */ 230 231 area_id fb_area; /* Frame buffer's area_id. The addresses are shared with all teams. */ 232 area_id unaligned_dma_area; /* Area assigned for DMA. It will be (partially) mapped to an 233 aligned area using MTRR-WC. */ 234 area_id dma_area; /* Aligned area assigned for DMA. The addresses are shared with all teams. */ 235 236 void *framebuffer; /* As viewed from virtual memory */ 237 void *framebuffer_pci; /* As viewed from the PCI bus (for DMA) */ 238 void *dma_buffer; /* As viewed from virtual memory */ 239 void *dma_buffer_pci; /* As viewed from the PCI bus (for DMA) */ 240 241 /*screenmode list*/ 242 area_id mode_area; /* Contains the list of display modes the driver supports */ 243 uint32 mode_count; /* Number of display modes in the list */ 244 245 /*flags - used by driver*/ 246 uint32 flags; 247 248 /*vblank semaphore*/ 249 sem_id vblank; /* The vertical blank semaphore. Ownership will be 250 transfered to the team opening the device first */ 251 /*cursor information*/ 252 struct { 253 uint16 hot_x; /* Cursor hot spot. The top left corner of the cursor */ 254 uint16 hot_y; /* is 0,0 */ 255 uint16 x; /* The location of the cursor hot spot on the */ 256 uint16 y; /* desktop */ 257 uint16 width; /* Width and height of the cursor shape (always 16!) */ 258 uint16 height; 259 bool is_visible; /* Is the cursor currently displayed? */ 260 bool dh_right; /* Is cursor on right side of stretched screen? */ 261 } cursor; 262 263 /*colour lookup table*/ 264 uint8 color_data[3 * 256]; /* Colour lookup table - as used by DAC */ 265 266 /*more display mode stuff*/ 267 display_mode dm; /* current display mode configuration: head1 */ 268 uint32 dpms_flags; /* current DPMS mode */ 269 bool acc_mode; /* signals (non)accelerated mode */ 270 bool interlaced_tv_mode;/* signals interlaced CRTC TV output mode */ 271 bool crtc_switch_mode; /* signals dualhead switch mode if panels are used */ 272 273 /*frame buffer config - for BDirectScreen*/ 274 frame_buffer_config fbc; /* bytes_per_row and start of frame buffer: head1 */ 275 accelerant_device_info adi; /* as returned by hook GET_ACCELERANT_DEVICE_INFO */ 276 277 /*acceleration engine*/ 278 struct { 279 uint32 count; /* last dwgsync slot used */ 280 uint32 last_idle; /* last dwgsync slot we *know* the engine was idle after */ 281 benaphore lock; /* for serializing access to the acc engine */ 282 struct { 283 uint32 handle[0x08]; /* FIFO channel's cmd handle for the owning cmd */ 284 uint32 ch_ptr[0x20]; /* cmd handle's ptr to it's assigned FIFO ch (if any) */ 285 } fifo; 286 struct { 287 uint32 put; /* last 32-bit-word adress given to engine to exec. to */ 288 uint32 current; /* first free 32-bit-word adress in buffer */ 289 uint32 free; /* nr. of useable free 32-bit words remaining in buffer */ 290 uint32 max; /* command buffer's useable size in 32-bit words */ 291 } dma; 292 bool agp_mode; /* card is running in AGP mode */ 293 struct { 294 uint32 clones; /* clone 'number' (mask, slot) (one bit per clone) */ 295 uint32 reload; /* reload state and surfaces (one bit per clone) */ 296 uint32 newmode; /* re-allocate all buffers (one bit per clone) */ 297 //fixme: memory stuff needs to be expanded (shared texture allocation?) 298 uint32 mem_low; /* ptr to first free mem adress: cardmem local offset */ 299 uint32 mem_high; /* ptr to last free mem adress: cardmem local offset */ 300 bool mode_changing; /* a mode-change is in progress (set/clear by 2D drv) */ 301 } threeD; 302 } engine; 303 304 /* card info - information gathered from PINS (and other sources) */ 305 enum 306 { // tv_encoder_type in order of capability (more or less) 307 NONE = 0, 308 CH7003, 309 CH7004, 310 CH7005, 311 CH7006, 312 CH7007, 313 CH7008, 314 SAA7102, 315 SAA7103, 316 SAA7104, 317 SAA7105, 318 BT868, 319 BT869, 320 CX25870, 321 CX25871, 322 NVIDIA 323 }; 324 325 struct 326 { 327 /* specialised registers for card initialisation read from NV BIOS (pins) */ 328 329 /* general card information */ 330 uint32 card_type; /* see card_type enum above */ 331 uint32 card_arch; /* see card_arch enum above */ 332 bool laptop; /* mobile chipset or not ('internal' flatpanel!) */ 333 bool slaved_tmds1; /* external TMDS encoder active on CRTC1 */ 334 bool slaved_tmds2; /* external TMDS encoder active on CRTC2 */ 335 bool master_tmds1; /* on die TMDS encoder active on CRTC1 */ 336 bool master_tmds2; /* on die TMDS encoder active on CRTC2 */ 337 bool tmds1_active; /* found panel on CRTC1 that is active */ 338 bool tmds2_active; /* found panel on CRTC2 that is active */ 339 display_timing p1_timing; /* 'modeline' fetched for panel 1 */ 340 display_timing p2_timing; /* 'modeline' fetched for panel 2 */ 341 float panel1_aspect; /* panel's aspect ratio */ 342 float panel2_aspect; /* panel's aspect ratio */ 343 bool crtc2_prim; /* using CRTC2 as primary CRTC */ 344 bool i2c_bus0; /* we have a wired I2C bus 0 on board */ 345 bool i2c_bus1; /* we have a wired I2C bus 1 on board */ 346 bool i2c_bus2; /* we have a wired I2C bus 2 on board */ 347 bool i2c_bus3; /* we have a wired I2C bus 3 on board */ 348 struct 349 { 350 uint32 type; /* see tvchip_type enum above */ 351 uint8 version; /* chip silicon version */ 352 uint8 bus; /* I2C bus on which TVout chip resides */ 353 uint8 adress; /* I2C adress on which TVout chip resides */ 354 } tv_encoder; 355 uint8 monitors; /* output devices connection matrix */ 356 bool int_assigned; /* card has a useable INT assigned to it */ 357 status_t pins_status; /* B_OK if read correctly, B_ERROR if faked */ 358 359 /* PINS */ 360 float f_ref; /* PLL reference-oscillator frequency (Mhz) */ 361 bool ext_pll; /* the extended PLL contains more dividers */ 362 uint32 max_system_vco; /* graphics engine PLL VCO limits (Mhz) */ 363 uint32 min_system_vco; 364 uint32 max_pixel_vco; /* dac1 PLL VCO limits (Mhz) */ 365 uint32 min_pixel_vco; 366 uint32 max_video_vco; /* dac2 PLL VCO limits (Mhz) */ 367 uint32 min_video_vco; 368 uint32 std_engine_clock; /* graphics engine clock speed needed (Mhz) */ 369 uint32 std_memory_clock; /* card memory clock speed needed (Mhz) */ 370 uint32 max_dac1_clock; /* dac1 limits (Mhz) */ 371 uint32 max_dac1_clock_8; /* dac1 limits correlated to RAMspeed limits (Mhz) */ 372 uint32 max_dac1_clock_16; 373 uint32 max_dac1_clock_24; 374 uint32 max_dac1_clock_32; 375 uint32 max_dac1_clock_32dh; 376 uint32 max_dac2_clock; /* dac2 limits (Mhz) */ 377 uint32 max_dac2_clock_8; /* dac2, maven limits correlated to RAMspeed limits (Mhz) */ 378 uint32 max_dac2_clock_16; 379 uint32 max_dac2_clock_24; 380 uint32 max_dac2_clock_32; 381 uint32 max_dac2_clock_32dh; 382 bool secondary_head; /* presence of functions */ 383 bool tvout; 384 bool primary_dvi; 385 bool secondary_dvi; 386 uint32 memory_size; /* memory (in bytes) */ 387 } ps; 388 389 /* mirror of the ROM (copied in driver, because may not be mapped permanently) */ 390 uint8 rom_mirror[65536]; 391 392 /* some configuration settings from ~/config/settings/kernel/drivers/nv.settings if exists */ 393 nv_settings settings; 394 395 struct 396 { 397 overlay_buffer myBuffer[MAXBUFFERS];/* scaler input buffers */ 398 int_buf_info myBufInfo[MAXBUFFERS]; /* extra info on scaler input buffers */ 399 overlay_token myToken; /* scaler is free/in use */ 400 benaphore lock; /* for creating buffers and aquiring overlay unit routines */ 401 bool crtc; /* location of overlay unit */ 402 /* variables needed for virtualscreens (move_overlay()): */ 403 bool active; /* true is overlay currently in use */ 404 overlay_window ow; /* current position of overlay output window */ 405 overlay_buffer ob; /* current inputbuffer in use */ 406 overlay_view my_ov; /* current corrected view in inputbuffer */ 407 uint32 h_ifactor; /* current 'unclipped' horizontal inverse scaling factor */ 408 uint32 v_ifactor; /* current 'unclipped' vertical inverse scaling factor */ 409 } overlay; 410 411 } shared_info; 412 413 /* Read or write a value in PCI configuration space */ 414 typedef struct { 415 uint32 magic; /* magic number to make sure the caller groks us */ 416 uint32 offset; /* Offset to read/write */ 417 uint32 size; /* Number of bytes to transfer */ 418 uint32 value; /* The value read or written */ 419 } nv_get_set_pci; 420 421 /* Enable or Disable CRTC (1,2) interrupts */ 422 typedef struct { 423 uint32 magic; /* magic number to make sure the caller groks us */ 424 bool crtc; /* adressed CRTC */ 425 bool do_it; /* state to set */ 426 } nv_set_vblank_int; 427 428 /* Retrieve the area_id of the kernel/accelerant shared info */ 429 typedef struct { 430 uint32 magic; /* magic number to make sure the caller groks us */ 431 area_id shared_info_area; /* area_id containing the shared information */ 432 } nv_get_private_data; 433 434 /* Retrieve the device name. Usefull for when we have a file handle, but want 435 to know the device name (like when we are cloning the accelerant) */ 436 typedef struct { 437 uint32 magic; /* magic number to make sure the caller groks us */ 438 char *name; /* The name of the device, less the /dev root */ 439 } nv_device_name; 440 441 /* Retrieve an AGP device interface if there. Usefull to find the AGP speed scheme 442 used (pre 3.x or 3.x) */ 443 typedef struct { 444 uint32 magic; /* magic number to make sure the caller groks us */ 445 bool agp_bus;/* indicates if we have access to the AGP busmanager */ 446 uint8 index; /* device index in list of devices found */ 447 bool exist; /* we got AGP device info */ 448 agp_info agpi; /* AGP interface info of a device */ 449 } nv_nth_agp_info; 450 451 /* Execute an AGP command */ 452 typedef struct { 453 uint32 magic; /* magic number to make sure the caller groks us */ 454 bool agp_bus;/* indicates if we have access to the AGP busmanager */ 455 uint32 cmd; /* actual command to execute */ 456 } nv_cmd_agp; 457 458 /* Read or write a value in ISA I/O space */ 459 typedef struct { 460 uint32 magic; /* magic number to make sure the caller groks us */ 461 uint16 adress; /* Offset to read/write */ 462 uint8 size; /* Number of bytes to transfer */ 463 uint16 data; /* The value read or written */ 464 } nv_in_out_isa; 465 466 enum { 467 468 _WAIT_FOR_VBLANK = (1 << 0) 469 }; 470 471 #if defined(__cplusplus) 472 } 473 #endif 474 475 476 #endif 477