1 /* 2 Copyright 1999, Be Incorporated. All Rights Reserved. 3 This file may be used under the terms of the Be Sample Code License. 4 5 Other authors: 6 Mark Watson; 7 Apsed; 8 Rudolf Cornelissen 10/2002-8/2009. 9 */ 10 11 #ifndef DRIVERINTERFACE_H 12 #define DRIVERINTERFACE_H 13 14 #include <Accelerant.h> 15 #include <video_overlay.h> 16 #include <Drivers.h> 17 #include <PCI.h> 18 #include <OS.h> 19 #include <edid.h> 20 #include <AGP.h> 21 22 #define DRIVER_PREFIX "nvidia" 23 #define DEVICE_FORMAT "%04x_%04x_%02x%02x%02x" 24 25 /* 26 Internal driver state (also for sharing info between driver and accelerant) 27 */ 28 #if defined(__cplusplus) 29 extern "C" { 30 #endif 31 32 typedef struct { 33 sem_id sem; 34 int32 ben; 35 } benaphore; 36 37 #define INIT_BEN(x) x.sem = create_sem(0, "NV "#x" benaphore"); x.ben = 0; 38 #define AQUIRE_BEN(x) if((atomic_add(&(x.ben), 1)) >= 1) acquire_sem(x.sem); 39 #define RELEASE_BEN(x) if((atomic_add(&(x.ben), -1)) > 1) release_sem(x.sem); 40 #define DELETE_BEN(x) delete_sem(x.sem); 41 42 43 #define NV_PRIVATE_DATA_MAGIC 0x0009 /* a private driver rev, of sorts */ 44 45 /* monitor setup */ 46 #define CRTC1_TMDS 0x01 47 #define CRTC2_TMDS 0x10 48 #define CRTC1_VGA 0x02 49 #define CRTC2_VGA 0x20 50 51 /* dualhead extensions to flags */ 52 #define DUALHEAD_OFF (0<<6) 53 #define DUALHEAD_CLONE (1<<6) 54 #define DUALHEAD_ON (2<<6) 55 #define DUALHEAD_SWITCH (3<<6) 56 #define DUALHEAD_BITS (3<<6) 57 #define DUALHEAD_CAPABLE (1<<8) 58 #define TV_BITS (3<<9) 59 #define TV_MON (0<<9 60 #define TV_PAL (1<<9) 61 #define TV_NTSC (2<<9) 62 #define TV_CAPABLE (1<<11) 63 #define TV_VIDEO (1<<12) 64 #define TV_PRIMARY (1<<13) 65 66 #define SKD_MOVE_CURSOR 0x00000001 67 #define SKD_PROGRAM_CLUT 0x00000002 68 #define SKD_SET_START_ADDR 0x00000004 69 #define SKD_SET_CURSOR 0x00000008 70 #define SKD_HANDLER_INSTALLED 0x80000000 71 72 enum { 73 NV_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1, 74 NV_GET_PCI, 75 NV_SET_PCI, 76 NV_DEVICE_NAME, 77 NV_RUN_INTERRUPTS, 78 NV_GET_NTH_AGP_INFO, 79 NV_ENABLE_AGP, 80 NV_ISA_OUT, 81 NV_ISA_IN 82 }; 83 84 /* card_type in order of date of NV chip design */ 85 enum { 86 NV04 = 0, 87 NV05, 88 NV05M64, 89 NV06, 90 NV10, 91 NV11, 92 NV11M, 93 NV15, 94 NV17, 95 NV17M, 96 NV18, 97 NV18M, 98 NV20, 99 NV25, 100 NV28, 101 NV30, 102 NV31, 103 NV34, 104 NV35, 105 NV36, 106 NV38, 107 NV40, 108 NV41, 109 NV43, 110 NV44, 111 NV45, 112 G70, 113 G71, 114 G72, 115 G73 116 }; 117 118 /* card_arch in order of date of NV chip design */ 119 enum { 120 NV04A = 0, 121 NV10A, 122 NV20A, 123 NV30A, 124 NV40A 125 }; 126 127 /* card info - information gathered from PINS (and other sources) */ 128 enum 129 { // tv_encoder_type in order of capability (more or less) 130 NONE = 0, 131 CH7003, 132 CH7004, 133 CH7005, 134 CH7006, 135 CH7007, 136 CH7008, 137 SAA7102, 138 SAA7103, 139 SAA7104, 140 SAA7105, 141 BT868, 142 BT869, 143 CX25870, 144 CX25871, 145 NVIDIA 146 }; 147 148 /* handles to pre-defined engine commands */ 149 #define NV_ROP5_SOLID 0x00000000 /* 2D */ 150 #define NV_IMAGE_BLACK_RECTANGLE 0x00000001 /* 2D/3D */ 151 #define NV_IMAGE_PATTERN 0x00000002 /* 2D */ 152 #define NV_SCALED_IMAGE_FROM_MEMORY 0x00000003 /* 2D */ 153 #define NV_TCL_PRIMITIVE_3D 0x00000004 /* 3D */ //2007 154 #define NV4_SURFACE 0x00000010 /* 2D */ 155 #define NV10_CONTEXT_SURFACES_2D 0x00000010 /* 2D */ 156 #define NV_IMAGE_BLIT 0x00000011 /* 2D */ 157 #define NV12_IMAGE_BLIT 0x00000011 /* 2D */ 158 /* fixme: 159 * never use NV3_GDI_RECTANGLE_TEXT for DMA acceleration: 160 * There's a hardware fault in the input->output colorspace conversion here. 161 * Besides, in NV40 and up this command nolonger exists. Both 'facts' are confirmed 162 * by testing. 163 */ 164 //#define NV3_GDI_RECTANGLE_TEXT 0x00000012 /* 2D */ 165 #define NV4_GDI_RECTANGLE_TEXT 0x00000012 /* 2D */ 166 #define NV4_CONTEXT_SURFACES_ARGB_ZS 0x00000013 /* 3D */ 167 #define NV10_CONTEXT_SURFACES_ARGB_ZS 0x00000013 /* 3D */ 168 #define NV4_DX5_TEXTURE_TRIANGLE 0x00000014 /* 3D */ 169 #define NV10_DX5_TEXTURE_TRIANGLE 0x00000014 /* 3D */ 170 #define NV4_DX6_MULTI_TEXTURE_TRIANGLE 0x00000015 /* unused (yet?) */ 171 #define NV10_DX6_MULTI_TEXTURE_TRIANGLE 0x00000015 /* unused (yet?) */ 172 #define NV1_RENDER_SOLID_LIN 0x00000016 /* 2D: unused */ 173 174 /* max. number of overlay buffers */ 175 #define MAXBUFFERS 3 176 177 //----------------------------------------------------------------------------------- 178 /* safety byte-offset from end of cardRAM for preventing acceleration engine crashes 179 * caused by the existance of DMA engine command buffers in cardRAM and/or fifo 180 * channel engine command re-assigning on-the-fly */ 181 182 /* pre-NV40 notes: 183 * - we need at least 70kB distance from the end of RAM for fifo-reassigning 'bug' 184 * (confirmed on a TNT1); 185 * - keep extra failsafe room to prevent malfunctioning apps from crashing engine. */ 186 #define PRE_NV40_OFFSET 80 * 1024 187 188 /* NV40 and higher notes: 189 * - we need at least 416kB distance from the DMA command buffer: 190 * If you get too close to the DMA command buffer on NV40 and NV43 at least (both 191 * confirmed), the source DMA instance will mess-up for at least engine command 192 * NV_IMAGE_BLIT and NV12_IMAGE_BLIT; 193 * - we need at least ???kB distance from the end of RAM for fifo-reassigning 'bug' 194 * (fixme: unknown yet because fifo assignment switching isn't used here atm); 195 * - keep extra failsafe room to prevent malfunctioning apps from crashing engine. */ 196 #define NV40_PLUS_OFFSET 512 * 1024 197 198 /* fifo re-assigning bug definition: 199 * if the fifo assignment is changed while at the same time card memory in the 200 * dangerous region is being accessed by some application, the engine will crash. 201 * This bug applies for both PIO and DMA mode acceleration! */ 202 203 /* source-DMA instance bug definition: 204 * if card memory in the dangerous region is being accessed by some application while 205 * a DMA command buffer exists in the same memory (though in a different place), 206 * the engine will crash. */ 207 //----------------------------------------------------------------------------------- 208 209 /* internal used info on overlay buffers */ 210 typedef struct { 211 uint16 slopspace; 212 uint32 size; 213 } int_buf_info; 214 215 typedef struct { // apsed, see comments in nvidia.settings 216 // for driver 217 char accelerant[B_FILE_NAME_LENGTH]; 218 char primary[B_FILE_NAME_LENGTH]; 219 bool dumprom; 220 // for accelerant 221 uint32 logmask; 222 uint32 memory; 223 uint32 tv_output; 224 bool usebios; 225 bool hardcursor; 226 bool switchhead; 227 bool force_pci; 228 bool unhide_fw; 229 bool pgm_panel; 230 bool dma_acc; 231 bool vga_on_tv; 232 bool force_sync; 233 bool force_ws; 234 bool block_acc; 235 uint32 gpu_clk; 236 uint32 ram_clk; 237 } nv_settings; 238 239 /* monitor info gathered via EDID */ 240 typedef struct { 241 bool have_native_edid; /* gathered 'native' EDID either via DDC or via GPU */ 242 bool digital; /* screen connection type: analog (VGA) or digital (DVI) */ 243 display_timing timing; /* 'native modeline' fetched for screen */ 244 float aspect; /* screen's aspect ratio */ 245 bool have_full_edid; /* EDID read succesfully via DDC */ 246 edid1_info full_edid; /* complete EDID info as fetched via DDC */ 247 } edid_specs; 248 249 /* shared info */ 250 typedef struct { 251 /* a few ID things */ 252 uint16 vendor_id; /* PCI vendor ID, from pci_info */ 253 uint16 device_id; /* PCI device ID, from pci_info */ 254 uint8 revision; /* PCI device revsion, from pci_info */ 255 uint8 bus; /* PCI bus number, from pci_info */ 256 uint8 device; /* PCI device number on bus, from pci_info */ 257 uint8 function; /* PCI function number in device, from pci_info */ 258 259 /* used to return status for INIT_ACCELERANT and CLONE_ACCELERANT */ 260 bool accelerant_in_use; 261 262 /* bug workaround for 4.5.0 */ 263 uint32 use_clone_bugfix; /*for 4.5.0, cloning of physical memory does not work*/ 264 uint32 * clone_bugfix_regs; 265 266 /*memory mappings*/ 267 area_id regs_area; /* Kernel's area_id for the memory mapped registers. 268 It will be cloned into the accelerant's address 269 space. */ 270 271 area_id fb_area; /* Frame buffer's area_id. The addresses are shared with all teams. */ 272 area_id unaligned_dma_area; /* Area assigned for DMA. It will be (partially) mapped to an 273 aligned area using MTRR-WC. */ 274 area_id dma_area; /* Aligned area assigned for DMA. The addresses are shared with all teams. */ 275 276 void *framebuffer; /* As viewed from virtual memory */ 277 void *framebuffer_pci; /* As viewed from the PCI bus (for DMA) */ 278 void *dma_buffer; /* As viewed from virtual memory */ 279 void *dma_buffer_pci; /* As viewed from the PCI bus (for DMA) */ 280 281 /*screenmode list*/ 282 area_id mode_area; /* Contains the list of display modes the driver supports */ 283 uint32 mode_count; /* Number of display modes in the list */ 284 285 /*flags - used by driver*/ 286 uint32 flags; 287 288 /*vblank semaphore*/ 289 sem_id vblank; /* The vertical blank semaphore. Ownership will be 290 transfered to the team opening the device first */ 291 /*cursor information*/ 292 struct { 293 uint16 hot_x; /* Cursor hot spot. The top left corner of the cursor */ 294 uint16 hot_y; /* is 0,0 */ 295 uint16 x; /* The location of the cursor hot spot on the */ 296 uint16 y; /* desktop */ 297 uint16 width; /* Width and height of the cursor shape (always 16!) */ 298 uint16 height; 299 bool is_visible; /* Is the cursor currently displayed? */ 300 bool dh_right; /* Is cursor on right side of stretched screen? */ 301 } cursor; 302 303 /*colour lookup table*/ 304 uint8 color_data[3 * 256]; /* Colour lookup table - as used by DAC */ 305 306 /*more display mode stuff*/ 307 display_mode dm; /* current display mode configuration: head1 */ 308 uint32 dpms_flags; /* current DPMS mode */ 309 bool acc_mode; /* signals (non)accelerated mode */ 310 bool interlaced_tv_mode;/* signals interlaced CRTC TV output mode */ 311 bool crtc_switch_mode; /* signals dualhead switch mode if panels are used */ 312 313 /*frame buffer config - for BDirectScreen*/ 314 frame_buffer_config fbc; /* bytes_per_row and start of frame buffer: head1 */ 315 accelerant_device_info adi; /* as returned by hook GET_ACCELERANT_DEVICE_INFO */ 316 317 /*acceleration engine*/ 318 struct { 319 uint32 count; /* last dwgsync slot used */ 320 uint32 last_idle; /* last dwgsync slot we *know* the engine was idle after */ 321 benaphore lock; /* for serializing access to the acc engine */ 322 struct { 323 uint32 handle[0x08]; /* FIFO channel's cmd handle for the owning cmd */ 324 uint32 ch_ptr[0x20]; /* cmd handle's ptr to it's assigned FIFO ch (if any) */ 325 } fifo; 326 struct { 327 uint32 put; /* last 32-bit-word adress given to engine to exec. to */ 328 uint32 current; /* first free 32-bit-word adress in buffer */ 329 uint32 free; /* nr. of useable free 32-bit words remaining in buffer */ 330 uint32 max; /* command buffer's useable size in 32-bit words */ 331 } dma; 332 bool agp_mode; /* card is running in AGP mode */ 333 struct { 334 uint32 clones; /* clone 'number' (mask, slot) (one bit per clone) */ 335 uint32 reload; /* reload state and surfaces (one bit per clone) */ 336 uint32 newmode; /* re-allocate all buffers (one bit per clone) */ 337 //fixme: memory stuff needs to be expanded (shared texture allocation?) 338 uint32 mem_low; /* ptr to first free mem adress: cardmem local offset */ 339 uint32 mem_high; /* ptr to last free mem adress: cardmem local offset */ 340 bool mode_changing; /* a mode-change is in progress (set/clear by 2D drv) */ 341 } threeD; 342 } engine; 343 344 struct 345 { 346 /* specialised registers for card initialisation read from NV BIOS (pins) */ 347 348 /* general card information */ 349 uint32 card_type; /* see card_type enum above */ 350 uint32 card_arch; /* see card_arch enum above */ 351 bool laptop; /* mobile chipset or not ('internal' flatpanel!) */ 352 bool slaved_tmds1; /* external TMDS encoder active on CRTC1 */ 353 bool slaved_tmds2; /* external TMDS encoder active on CRTC2 */ 354 bool master_tmds1; /* on die TMDS encoder active on CRTC1 */ 355 bool master_tmds2; /* on die TMDS encoder active on CRTC2 */ 356 display_timing p1_timing; /* 'modeline' fetched for panel at CRTC1 */ 357 display_timing p2_timing; /* 'modeline' fetched for panel at CRTC2 */ 358 edid_specs con1_screen; /* EDID properties of the screen connected to connector 1 */ 359 edid_specs con2_screen; /* EDID properties of the screen connected to connector 2 */ 360 edid_specs crtc1_screen; /* EDID properties of the screen connected to CRTC1 */ 361 edid_specs crtc2_screen; /* EDID properties of the screen connected to CRTC2 */ 362 bool crtc2_prim; /* using CRTC2 as primary CRTC */ 363 bool i2c_bus0; /* we have a wired I2C bus 0 on board */ 364 bool i2c_bus1; /* we have a wired I2C bus 1 on board */ 365 bool i2c_bus2; /* we have a wired I2C bus 2 on board */ 366 struct 367 { 368 uint32 type; /* see tvchip_type enum above */ 369 uint8 version; /* chip silicon version */ 370 uint8 bus; /* I2C bus on which TVout chip resides */ 371 uint8 adress; /* I2C adress on which TVout chip resides */ 372 } tv_encoder; 373 uint8 monitors; /* output devices connection matrix */ 374 bool int_assigned; /* card has a useable INT assigned to it */ 375 status_t pins_status; /* B_OK if read correctly, B_ERROR if faked */ 376 377 /* PINS */ 378 float f_ref; /* PLL reference-oscillator frequency (Mhz) */ 379 bool ext_pll; /* the extended PLL contains more dividers */ 380 uint32 max_system_vco; /* graphics engine PLL VCO limits (Mhz) */ 381 uint32 min_system_vco; 382 uint32 max_pixel_vco; /* dac1 PLL VCO limits (Mhz) */ 383 uint32 min_pixel_vco; 384 uint32 max_video_vco; /* dac2 PLL VCO limits (Mhz) */ 385 uint32 min_video_vco; 386 uint32 std_engine_clock; /* graphics engine clock speed needed (Mhz) */ 387 uint32 std_memory_clock; /* card memory clock speed needed (Mhz) */ 388 uint32 max_dac1_clock; /* dac1 limits (Mhz) */ 389 uint32 max_dac1_clock_8; /* dac1 limits correlated to RAMspeed limits (Mhz) */ 390 uint32 max_dac1_clock_16; 391 uint32 max_dac1_clock_24; 392 uint32 max_dac1_clock_32; 393 uint32 max_dac1_clock_32dh; 394 uint32 max_dac2_clock; /* dac2 limits (Mhz) */ 395 uint32 max_dac2_clock_8; /* dac2, maven limits correlated to RAMspeed limits (Mhz) */ 396 uint32 max_dac2_clock_16; 397 uint32 max_dac2_clock_24; 398 uint32 max_dac2_clock_32; 399 uint32 max_dac2_clock_32dh; 400 bool secondary_head; /* presence of functions */ 401 bool tvout; 402 bool primary_dvi; 403 bool secondary_dvi; 404 uint32 memory_size; /* memory (in bytes) */ 405 } ps; 406 407 /* mirror of the ROM (copied in driver, because may not be mapped permanently) */ 408 uint8 rom_mirror[65536]; 409 410 /* some configuration settings from ~/config/settings/kernel/drivers/nv.settings if exists */ 411 nv_settings settings; 412 413 struct 414 { 415 overlay_buffer myBuffer[MAXBUFFERS];/* scaler input buffers */ 416 int_buf_info myBufInfo[MAXBUFFERS]; /* extra info on scaler input buffers */ 417 overlay_token myToken; /* scaler is free/in use */ 418 benaphore lock; /* for creating buffers and aquiring overlay unit routines */ 419 bool crtc; /* location of overlay unit */ 420 /* variables needed for virtualscreens (move_overlay()): */ 421 bool active; /* true is overlay currently in use */ 422 overlay_window ow; /* current position of overlay output window */ 423 overlay_buffer ob; /* current inputbuffer in use */ 424 overlay_view my_ov; /* current corrected view in inputbuffer */ 425 uint32 h_ifactor; /* current 'unclipped' horizontal inverse scaling factor */ 426 uint32 v_ifactor; /* current 'unclipped' vertical inverse scaling factor */ 427 } overlay; 428 429 } shared_info; 430 431 /* Read or write a value in PCI configuration space */ 432 typedef struct { 433 uint32 magic; /* magic number to make sure the caller groks us */ 434 uint32 offset; /* Offset to read/write */ 435 uint32 size; /* Number of bytes to transfer */ 436 uint32 value; /* The value read or written */ 437 } nv_get_set_pci; 438 439 /* Enable or Disable CRTC (1,2) interrupts */ 440 typedef struct { 441 uint32 magic; /* magic number to make sure the caller groks us */ 442 bool crtc; /* adressed CRTC */ 443 bool do_it; /* state to set */ 444 } nv_set_vblank_int; 445 446 /* Retrieve the area_id of the kernel/accelerant shared info */ 447 typedef struct { 448 uint32 magic; /* magic number to make sure the caller groks us */ 449 area_id shared_info_area; /* area_id containing the shared information */ 450 } nv_get_private_data; 451 452 /* Retrieve the device name. Usefull for when we have a file handle, but want 453 to know the device name (like when we are cloning the accelerant) */ 454 typedef struct { 455 uint32 magic; /* magic number to make sure the caller groks us */ 456 char *name; /* The name of the device, less the /dev root */ 457 } nv_device_name; 458 459 /* Retrieve an AGP device interface if there. Usefull to find the AGP speed scheme 460 used (pre 3.x or 3.x) */ 461 typedef struct { 462 uint32 magic; /* magic number to make sure the caller groks us */ 463 bool agp_bus;/* indicates if we have access to the AGP busmanager */ 464 uint8 index; /* device index in list of devices found */ 465 bool exist; /* we got AGP device info */ 466 agp_info agpi; /* AGP interface info of a device */ 467 } nv_nth_agp_info; 468 469 /* Execute an AGP command */ 470 typedef struct { 471 uint32 magic; /* magic number to make sure the caller groks us */ 472 bool agp_bus;/* indicates if we have access to the AGP busmanager */ 473 uint32 cmd; /* actual command to execute */ 474 } nv_cmd_agp; 475 476 /* Read or write a value in ISA I/O space */ 477 typedef struct { 478 uint32 magic; /* magic number to make sure the caller groks us */ 479 uint16 adress; /* Offset to read/write */ 480 uint8 size; /* Number of bytes to transfer */ 481 uint16 data; /* The value read or written */ 482 } nv_in_out_isa; 483 484 enum { 485 486 _WAIT_FOR_VBLANK = (1 << 0) 487 }; 488 489 #if defined(__cplusplus) 490 } 491 #endif 492 493 494 #endif 495