1 /* 2 Copyright 1999, Be Incorporated. All Rights Reserved. 3 This file may be used under the terms of the Be Sample Code License. 4 5 Other authors: 6 Mark Watson; 7 Apsed; 8 Rudolf Cornelissen 10/2002-6/2008. 9 */ 10 11 #ifndef DRIVERINTERFACE_H 12 #define DRIVERINTERFACE_H 13 14 #include <Accelerant.h> 15 #include "video_overlay.h" 16 #include <Drivers.h> 17 #include <PCI.h> 18 #include <OS.h> 19 #include "AGP.h" 20 21 #define DRIVER_PREFIX "nvidia" 22 #define DEVICE_FORMAT "%04x_%04x_%02x%02x%02x" 23 24 /* 25 Internal driver state (also for sharing info between driver and accelerant) 26 */ 27 #if defined(__cplusplus) 28 extern "C" { 29 #endif 30 31 typedef struct { 32 sem_id sem; 33 int32 ben; 34 } benaphore; 35 36 #define INIT_BEN(x) x.sem = create_sem(0, "NV "#x" benaphore"); x.ben = 0; 37 #define AQUIRE_BEN(x) if((atomic_add(&(x.ben), 1)) >= 1) acquire_sem(x.sem); 38 #define RELEASE_BEN(x) if((atomic_add(&(x.ben), -1)) > 1) release_sem(x.sem); 39 #define DELETE_BEN(x) delete_sem(x.sem); 40 41 42 #define NV_PRIVATE_DATA_MAGIC 0x0009 /* a private driver rev, of sorts */ 43 44 /* dualhead extensions to flags */ 45 #define DUALHEAD_OFF (0<<6) 46 #define DUALHEAD_CLONE (1<<6) 47 #define DUALHEAD_ON (2<<6) 48 #define DUALHEAD_SWITCH (3<<6) 49 #define DUALHEAD_BITS (3<<6) 50 #define DUALHEAD_CAPABLE (1<<8) 51 #define TV_BITS (3<<9) 52 #define TV_MON (0<<9 53 #define TV_PAL (1<<9) 54 #define TV_NTSC (2<<9) 55 #define TV_CAPABLE (1<<11) 56 #define TV_VIDEO (1<<12) 57 #define TV_PRIMARY (1<<13) 58 59 #define SKD_MOVE_CURSOR 0x00000001 60 #define SKD_PROGRAM_CLUT 0x00000002 61 #define SKD_SET_START_ADDR 0x00000004 62 #define SKD_SET_CURSOR 0x00000008 63 #define SKD_HANDLER_INSTALLED 0x80000000 64 65 enum { 66 NV_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1, 67 NV_GET_PCI, 68 NV_SET_PCI, 69 NV_DEVICE_NAME, 70 NV_RUN_INTERRUPTS, 71 NV_GET_NTH_AGP_INFO, 72 NV_ENABLE_AGP, 73 NV_ISA_OUT, 74 NV_ISA_IN 75 }; 76 77 /* card_type in order of date of NV chip design */ 78 enum { 79 NV04 = 0, 80 NV05, 81 NV05M64, 82 NV06, 83 NV10, 84 NV11, 85 NV11M, 86 NV15, 87 NV17, 88 NV17M, 89 NV18, 90 NV18M, 91 NV20, 92 NV25, 93 NV28, 94 NV30, 95 NV31, 96 NV34, 97 NV35, 98 NV36, 99 NV38, 100 NV40, 101 NV41, 102 NV43, 103 NV44, 104 NV45, 105 G70, 106 G71, 107 G72, 108 G73 109 }; 110 111 /* card_arch in order of date of NV chip design */ 112 enum { 113 NV04A = 0, 114 NV10A, 115 NV20A, 116 NV30A, 117 NV40A 118 }; 119 120 /* card info - information gathered from PINS (and other sources) */ 121 enum 122 { // tv_encoder_type in order of capability (more or less) 123 NONE = 0, 124 CH7003, 125 CH7004, 126 CH7005, 127 CH7006, 128 CH7007, 129 CH7008, 130 SAA7102, 131 SAA7103, 132 SAA7104, 133 SAA7105, 134 BT868, 135 BT869, 136 CX25870, 137 CX25871, 138 NVIDIA 139 }; 140 141 /* handles to pre-defined engine commands */ 142 #define NV_ROP5_SOLID 0x00000000 /* 2D */ 143 #define NV_IMAGE_BLACK_RECTANGLE 0x00000001 /* 2D/3D */ 144 #define NV_IMAGE_PATTERN 0x00000002 /* 2D */ 145 #define NV_SCALED_IMAGE_FROM_MEMORY 0x00000003 /* 2D */ 146 #define NV_TCL_PRIMITIVE_3D 0x00000004 /* 3D */ //2007 147 #define NV4_SURFACE 0x00000010 /* 2D */ 148 #define NV10_CONTEXT_SURFACES_2D 0x00000010 /* 2D */ 149 #define NV_IMAGE_BLIT 0x00000011 /* 2D */ 150 #define NV12_IMAGE_BLIT 0x00000011 /* 2D */ 151 /* fixme: 152 * never use NV3_GDI_RECTANGLE_TEXT for DMA acceleration: 153 * There's a hardware fault in the input->output colorspace conversion here. 154 * Besides, in NV40 and up this command nolonger exists. Both 'facts' are confirmed 155 * by testing. 156 */ 157 //#define NV3_GDI_RECTANGLE_TEXT 0x00000012 /* 2D */ 158 #define NV4_GDI_RECTANGLE_TEXT 0x00000012 /* 2D */ 159 #define NV4_CONTEXT_SURFACES_ARGB_ZS 0x00000013 /* 3D */ 160 #define NV10_CONTEXT_SURFACES_ARGB_ZS 0x00000013 /* 3D */ 161 #define NV4_DX5_TEXTURE_TRIANGLE 0x00000014 /* 3D */ 162 #define NV10_DX5_TEXTURE_TRIANGLE 0x00000014 /* 3D */ 163 #define NV4_DX6_MULTI_TEXTURE_TRIANGLE 0x00000015 /* unused (yet?) */ 164 #define NV10_DX6_MULTI_TEXTURE_TRIANGLE 0x00000015 /* unused (yet?) */ 165 #define NV1_RENDER_SOLID_LIN 0x00000016 /* 2D: unused */ 166 167 /* max. number of overlay buffers */ 168 #define MAXBUFFERS 3 169 170 //----------------------------------------------------------------------------------- 171 /* safety byte-offset from end of cardRAM for preventing acceleration engine crashes 172 * caused by the existance of DMA engine command buffers in cardRAM and/or fifo 173 * channel engine command re-assigning on-the-fly */ 174 175 /* pre-NV40 notes: 176 * - we need at least 70kB distance from the end of RAM for fifo-reassigning 'bug' 177 * (confirmed on a TNT1); 178 * - keep extra failsafe room to prevent malfunctioning apps from crashing engine. */ 179 #define PRE_NV40_OFFSET 80 * 1024 180 181 /* NV40 and higher notes: 182 * - we need at least 416kB distance from the DMA command buffer: 183 * If you get too close to the DMA command buffer on NV40 and NV43 at least (both 184 * confirmed), the source DMA instance will mess-up for at least engine command 185 * NV_IMAGE_BLIT and NV12_IMAGE_BLIT; 186 * - we need at least ???kB distance from the end of RAM for fifo-reassigning 'bug' 187 * (fixme: unknown yet because fifo assignment switching isn't used here atm); 188 * - keep extra failsafe room to prevent malfunctioning apps from crashing engine. */ 189 #define NV40_PLUS_OFFSET 512 * 1024 190 191 /* fifo re-assigning bug definition: 192 * if the fifo assignment is changed while at the same time card memory in the 193 * dangerous region is being accessed by some application, the engine will crash. 194 * This bug applies for both PIO and DMA mode acceleration! */ 195 196 /* source-DMA instance bug definition: 197 * if card memory in the dangerous region is being accessed by some application while 198 * a DMA command buffer exists in the same memory (though in a different place), 199 * the engine will crash. */ 200 //----------------------------------------------------------------------------------- 201 202 /* internal used info on overlay buffers */ 203 typedef struct { 204 uint16 slopspace; 205 uint32 size; 206 } int_buf_info; 207 208 typedef struct { // apsed, see comments in nv.settings 209 // for driver 210 char accelerant[B_FILE_NAME_LENGTH]; 211 char primary[B_FILE_NAME_LENGTH]; 212 bool dumprom; 213 // for accelerant 214 uint32 logmask; 215 uint32 memory; 216 uint32 tv_output; 217 bool usebios; 218 bool hardcursor; 219 bool switchhead; 220 bool force_pci; 221 bool unhide_fw; 222 bool pgm_panel; 223 bool dma_acc; 224 bool vga_on_tv; 225 bool force_sync; 226 bool force_ws; 227 uint32 gpu_clk; 228 uint32 ram_clk; 229 } nv_settings; 230 231 /* shared info */ 232 typedef struct { 233 /* a few ID things */ 234 uint16 vendor_id; /* PCI vendor ID, from pci_info */ 235 uint16 device_id; /* PCI device ID, from pci_info */ 236 uint8 revision; /* PCI device revsion, from pci_info */ 237 uint8 bus; /* PCI bus number, from pci_info */ 238 uint8 device; /* PCI device number on bus, from pci_info */ 239 uint8 function; /* PCI function number in device, from pci_info */ 240 241 /* used to return status for INIT_ACCELERANT and CLONE_ACCELERANT */ 242 bool accelerant_in_use; 243 244 /* bug workaround for 4.5.0 */ 245 uint32 use_clone_bugfix; /*for 4.5.0, cloning of physical memory does not work*/ 246 uint32 * clone_bugfix_regs; 247 248 /*memory mappings*/ 249 area_id regs_area; /* Kernel's area_id for the memory mapped registers. 250 It will be cloned into the accelerant's address 251 space. */ 252 253 area_id fb_area; /* Frame buffer's area_id. The addresses are shared with all teams. */ 254 area_id unaligned_dma_area; /* Area assigned for DMA. It will be (partially) mapped to an 255 aligned area using MTRR-WC. */ 256 area_id dma_area; /* Aligned area assigned for DMA. The addresses are shared with all teams. */ 257 258 void *framebuffer; /* As viewed from virtual memory */ 259 void *framebuffer_pci; /* As viewed from the PCI bus (for DMA) */ 260 void *dma_buffer; /* As viewed from virtual memory */ 261 void *dma_buffer_pci; /* As viewed from the PCI bus (for DMA) */ 262 263 /*screenmode list*/ 264 area_id mode_area; /* Contains the list of display modes the driver supports */ 265 uint32 mode_count; /* Number of display modes in the list */ 266 267 /*flags - used by driver*/ 268 uint32 flags; 269 270 /*vblank semaphore*/ 271 sem_id vblank; /* The vertical blank semaphore. Ownership will be 272 transfered to the team opening the device first */ 273 /*cursor information*/ 274 struct { 275 uint16 hot_x; /* Cursor hot spot. The top left corner of the cursor */ 276 uint16 hot_y; /* is 0,0 */ 277 uint16 x; /* The location of the cursor hot spot on the */ 278 uint16 y; /* desktop */ 279 uint16 width; /* Width and height of the cursor shape (always 16!) */ 280 uint16 height; 281 bool is_visible; /* Is the cursor currently displayed? */ 282 bool dh_right; /* Is cursor on right side of stretched screen? */ 283 } cursor; 284 285 /*colour lookup table*/ 286 uint8 color_data[3 * 256]; /* Colour lookup table - as used by DAC */ 287 288 /*more display mode stuff*/ 289 display_mode dm; /* current display mode configuration: head1 */ 290 uint32 dpms_flags; /* current DPMS mode */ 291 bool acc_mode; /* signals (non)accelerated mode */ 292 bool interlaced_tv_mode;/* signals interlaced CRTC TV output mode */ 293 bool crtc_switch_mode; /* signals dualhead switch mode if panels are used */ 294 295 /*frame buffer config - for BDirectScreen*/ 296 frame_buffer_config fbc; /* bytes_per_row and start of frame buffer: head1 */ 297 accelerant_device_info adi; /* as returned by hook GET_ACCELERANT_DEVICE_INFO */ 298 299 /*acceleration engine*/ 300 struct { 301 uint32 count; /* last dwgsync slot used */ 302 uint32 last_idle; /* last dwgsync slot we *know* the engine was idle after */ 303 benaphore lock; /* for serializing access to the acc engine */ 304 struct { 305 uint32 handle[0x08]; /* FIFO channel's cmd handle for the owning cmd */ 306 uint32 ch_ptr[0x20]; /* cmd handle's ptr to it's assigned FIFO ch (if any) */ 307 } fifo; 308 struct { 309 uint32 put; /* last 32-bit-word adress given to engine to exec. to */ 310 uint32 current; /* first free 32-bit-word adress in buffer */ 311 uint32 free; /* nr. of useable free 32-bit words remaining in buffer */ 312 uint32 max; /* command buffer's useable size in 32-bit words */ 313 } dma; 314 bool agp_mode; /* card is running in AGP mode */ 315 struct { 316 uint32 clones; /* clone 'number' (mask, slot) (one bit per clone) */ 317 uint32 reload; /* reload state and surfaces (one bit per clone) */ 318 uint32 newmode; /* re-allocate all buffers (one bit per clone) */ 319 //fixme: memory stuff needs to be expanded (shared texture allocation?) 320 uint32 mem_low; /* ptr to first free mem adress: cardmem local offset */ 321 uint32 mem_high; /* ptr to last free mem adress: cardmem local offset */ 322 bool mode_changing; /* a mode-change is in progress (set/clear by 2D drv) */ 323 } threeD; 324 } engine; 325 326 struct 327 { 328 /* specialised registers for card initialisation read from NV BIOS (pins) */ 329 330 /* general card information */ 331 uint32 card_type; /* see card_type enum above */ 332 uint32 card_arch; /* see card_arch enum above */ 333 bool laptop; /* mobile chipset or not ('internal' flatpanel!) */ 334 bool slaved_tmds1; /* external TMDS encoder active on CRTC1 */ 335 bool slaved_tmds2; /* external TMDS encoder active on CRTC2 */ 336 bool master_tmds1; /* on die TMDS encoder active on CRTC1 */ 337 bool master_tmds2; /* on die TMDS encoder active on CRTC2 */ 338 bool tmds1_active; /* found panel on CRTC1 that is active */ 339 bool tmds2_active; /* found panel on CRTC2 that is active */ 340 display_timing p1_timing; /* 'modeline' fetched for panel 1 */ 341 display_timing p2_timing; /* 'modeline' fetched for panel 2 */ 342 float panel1_aspect; /* panel's aspect ratio */ 343 float panel2_aspect; /* panel's aspect ratio */ 344 bool crtc2_prim; /* using CRTC2 as primary CRTC */ 345 bool i2c_bus0; /* we have a wired I2C bus 0 on board */ 346 bool i2c_bus1; /* we have a wired I2C bus 1 on board */ 347 bool i2c_bus2; /* we have a wired I2C bus 2 on board */ 348 bool i2c_bus3; /* we have a wired I2C bus 3 on board */ 349 struct 350 { 351 uint32 type; /* see tvchip_type enum above */ 352 uint8 version; /* chip silicon version */ 353 uint8 bus; /* I2C bus on which TVout chip resides */ 354 uint8 adress; /* I2C adress on which TVout chip resides */ 355 } tv_encoder; 356 uint8 monitors; /* output devices connection matrix */ 357 bool int_assigned; /* card has a useable INT assigned to it */ 358 status_t pins_status; /* B_OK if read correctly, B_ERROR if faked */ 359 360 /* PINS */ 361 float f_ref; /* PLL reference-oscillator frequency (Mhz) */ 362 bool ext_pll; /* the extended PLL contains more dividers */ 363 uint32 max_system_vco; /* graphics engine PLL VCO limits (Mhz) */ 364 uint32 min_system_vco; 365 uint32 max_pixel_vco; /* dac1 PLL VCO limits (Mhz) */ 366 uint32 min_pixel_vco; 367 uint32 max_video_vco; /* dac2 PLL VCO limits (Mhz) */ 368 uint32 min_video_vco; 369 uint32 std_engine_clock; /* graphics engine clock speed needed (Mhz) */ 370 uint32 std_memory_clock; /* card memory clock speed needed (Mhz) */ 371 uint32 max_dac1_clock; /* dac1 limits (Mhz) */ 372 uint32 max_dac1_clock_8; /* dac1 limits correlated to RAMspeed limits (Mhz) */ 373 uint32 max_dac1_clock_16; 374 uint32 max_dac1_clock_24; 375 uint32 max_dac1_clock_32; 376 uint32 max_dac1_clock_32dh; 377 uint32 max_dac2_clock; /* dac2 limits (Mhz) */ 378 uint32 max_dac2_clock_8; /* dac2, maven limits correlated to RAMspeed limits (Mhz) */ 379 uint32 max_dac2_clock_16; 380 uint32 max_dac2_clock_24; 381 uint32 max_dac2_clock_32; 382 uint32 max_dac2_clock_32dh; 383 bool secondary_head; /* presence of functions */ 384 bool tvout; 385 bool primary_dvi; 386 bool secondary_dvi; 387 uint32 memory_size; /* memory (in bytes) */ 388 } ps; 389 390 /* mirror of the ROM (copied in driver, because may not be mapped permanently) */ 391 uint8 rom_mirror[65536]; 392 393 /* some configuration settings from ~/config/settings/kernel/drivers/nv.settings if exists */ 394 nv_settings settings; 395 396 struct 397 { 398 overlay_buffer myBuffer[MAXBUFFERS];/* scaler input buffers */ 399 int_buf_info myBufInfo[MAXBUFFERS]; /* extra info on scaler input buffers */ 400 overlay_token myToken; /* scaler is free/in use */ 401 benaphore lock; /* for creating buffers and aquiring overlay unit routines */ 402 bool crtc; /* location of overlay unit */ 403 /* variables needed for virtualscreens (move_overlay()): */ 404 bool active; /* true is overlay currently in use */ 405 overlay_window ow; /* current position of overlay output window */ 406 overlay_buffer ob; /* current inputbuffer in use */ 407 overlay_view my_ov; /* current corrected view in inputbuffer */ 408 uint32 h_ifactor; /* current 'unclipped' horizontal inverse scaling factor */ 409 uint32 v_ifactor; /* current 'unclipped' vertical inverse scaling factor */ 410 } overlay; 411 412 } shared_info; 413 414 /* Read or write a value in PCI configuration space */ 415 typedef struct { 416 uint32 magic; /* magic number to make sure the caller groks us */ 417 uint32 offset; /* Offset to read/write */ 418 uint32 size; /* Number of bytes to transfer */ 419 uint32 value; /* The value read or written */ 420 } nv_get_set_pci; 421 422 /* Enable or Disable CRTC (1,2) interrupts */ 423 typedef struct { 424 uint32 magic; /* magic number to make sure the caller groks us */ 425 bool crtc; /* adressed CRTC */ 426 bool do_it; /* state to set */ 427 } nv_set_vblank_int; 428 429 /* Retrieve the area_id of the kernel/accelerant shared info */ 430 typedef struct { 431 uint32 magic; /* magic number to make sure the caller groks us */ 432 area_id shared_info_area; /* area_id containing the shared information */ 433 } nv_get_private_data; 434 435 /* Retrieve the device name. Usefull for when we have a file handle, but want 436 to know the device name (like when we are cloning the accelerant) */ 437 typedef struct { 438 uint32 magic; /* magic number to make sure the caller groks us */ 439 char *name; /* The name of the device, less the /dev root */ 440 } nv_device_name; 441 442 /* Retrieve an AGP device interface if there. Usefull to find the AGP speed scheme 443 used (pre 3.x or 3.x) */ 444 typedef struct { 445 uint32 magic; /* magic number to make sure the caller groks us */ 446 bool agp_bus;/* indicates if we have access to the AGP busmanager */ 447 uint8 index; /* device index in list of devices found */ 448 bool exist; /* we got AGP device info */ 449 agp_info agpi; /* AGP interface info of a device */ 450 } nv_nth_agp_info; 451 452 /* Execute an AGP command */ 453 typedef struct { 454 uint32 magic; /* magic number to make sure the caller groks us */ 455 bool agp_bus;/* indicates if we have access to the AGP busmanager */ 456 uint32 cmd; /* actual command to execute */ 457 } nv_cmd_agp; 458 459 /* Read or write a value in ISA I/O space */ 460 typedef struct { 461 uint32 magic; /* magic number to make sure the caller groks us */ 462 uint16 adress; /* Offset to read/write */ 463 uint8 size; /* Number of bytes to transfer */ 464 uint16 data; /* The value read or written */ 465 } nv_in_out_isa; 466 467 enum { 468 469 _WAIT_FOR_VBLANK = (1 << 0) 470 }; 471 472 #if defined(__cplusplus) 473 } 474 #endif 475 476 477 #endif 478