1 /* 2 Copyright 1999, Be Incorporated. All Rights Reserved. 3 This file may be used under the terms of the Be Sample Code License. 4 5 Other authors: 6 Mark Watson; 7 Apsed; 8 Rudolf Cornelissen 10/2002-2/2006. 9 */ 10 11 #ifndef DRIVERINTERFACE_H 12 #define DRIVERINTERFACE_H 13 14 #include <Accelerant.h> 15 #include "video_overlay.h" 16 #include <Drivers.h> 17 #include <PCI.h> 18 #include <OS.h> 19 #include "AGP.h" 20 21 #define DRIVER_PREFIX "nv" // apsed 22 #define DEVICE_FORMAT "%04X_%04X_%02X%02X%02X" // apsed 23 24 /* 25 Internal driver state (also for sharing info between driver and accelerant) 26 */ 27 #if defined(__cplusplus) 28 extern "C" { 29 #endif 30 31 typedef struct { 32 sem_id sem; 33 int32 ben; 34 } benaphore; 35 36 #define INIT_BEN(x) x.sem = create_sem(0, "NV "#x" benaphore"); x.ben = 0; 37 #define AQUIRE_BEN(x) if((atomic_add(&(x.ben), 1)) >= 1) acquire_sem(x.sem); 38 #define RELEASE_BEN(x) if((atomic_add(&(x.ben), -1)) > 1) release_sem(x.sem); 39 #define DELETE_BEN(x) delete_sem(x.sem); 40 41 42 #define NV_PRIVATE_DATA_MAGIC 0x0009 /* a private driver rev, of sorts */ 43 44 /*dualhead extensions to flags*/ 45 #define DUALHEAD_OFF (0<<6) 46 #define DUALHEAD_CLONE (1<<6) 47 #define DUALHEAD_ON (2<<6) 48 #define DUALHEAD_SWITCH (3<<6) 49 #define DUALHEAD_BITS (3<<6) 50 #define DUALHEAD_CAPABLE (1<<8) 51 #define TV_BITS (3<<9) 52 #define TV_MON (0<<9 53 #define TV_PAL (1<<9) 54 #define TV_NTSC (2<<9) 55 #define TV_CAPABLE (1<<11) 56 #define TV_VIDEO (1<<12) 57 #define TV_PRIMARY (1<<13) 58 59 #define SKD_MOVE_CURSOR 0x00000001 60 #define SKD_PROGRAM_CLUT 0x00000002 61 #define SKD_SET_START_ADDR 0x00000004 62 #define SKD_SET_CURSOR 0x00000008 63 #define SKD_HANDLER_INSTALLED 0x80000000 64 65 enum { 66 NV_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1, 67 NV_GET_PCI, 68 NV_SET_PCI, 69 NV_DEVICE_NAME, 70 NV_RUN_INTERRUPTS, 71 NV_GET_NTH_AGP_INFO, 72 NV_ENABLE_AGP, 73 NV_ISA_OUT, 74 NV_ISA_IN 75 }; 76 77 /* handles to pre-defined engine commands */ 78 #define NV_ROP5_SOLID 0x00000000 /* 2D */ 79 #define NV_IMAGE_BLACK_RECTANGLE 0x00000001 /* 2D/3D */ 80 #define NV_IMAGE_PATTERN 0x00000002 /* 2D */ 81 #define NV_SCALED_IMAGE_FROM_MEMORY 0x00000003 /* 2D */ 82 #define NV4_SURFACE 0x00000010 /* 2D */ 83 #define NV10_CONTEXT_SURFACES_2D 0x00000010 /* 2D */ 84 #define NV_IMAGE_BLIT 0x00000011 /* 2D */ 85 /* fixme: 86 * never use NV3_GDI_RECTANGLE_TEXT for DMA acceleration: 87 * There's a hardware fault in the input->output colorspace conversion here. 88 * Besides, in NV40 and up this command nolonger exists. Both 'facts' are confirmed 89 * by testing. 90 */ 91 //#define NV3_GDI_RECTANGLE_TEXT 0x00000012 /* 2D */ 92 #define NV4_GDI_RECTANGLE_TEXT 0x00000012 /* 2D */ 93 #define NV4_CONTEXT_SURFACES_ARGB_ZS 0x00000013 /* 3D */ 94 #define NV10_CONTEXT_SURFACES_ARGB_ZS 0x00000013 /* 3D */ 95 #define NV4_DX5_TEXTURE_TRIANGLE 0x00000014 /* 3D */ 96 #define NV10_DX5_TEXTURE_TRIANGLE 0x00000014 /* 3D */ 97 #define NV4_DX6_MULTI_TEXTURE_TRIANGLE 0x00000015 /* unused (yet?) */ 98 #define NV10_DX6_MULTI_TEXTURE_TRIANGLE 0x00000015 /* unused (yet?) */ 99 #define NV1_RENDER_SOLID_LIN 0x00000016 /* 2D: unused */ 100 101 /* max. number of overlay buffers */ 102 #define MAXBUFFERS 3 103 104 //----------------------------------------------------------------------------------- 105 /* safety byte-offset from end of cardRAM for preventing acceleration engine crashes 106 * caused by the existance of DMA engine command buffers in cardRAM and/or fifo 107 * channel engine command re-assigning on-the-fly */ 108 109 /* pre-NV40 notes: 110 * - we need at least 70kB distance from the end of RAM for fifo-reassigning 'bug' 111 * (confirmed on a TNT1); 112 * - keep extra failsafe room to prevent malfunctioning apps from crashing engine. */ 113 #define PRE_NV40_OFFSET 80 * 1024 114 115 /* NV40 and higher notes: 116 * - we need at least 416kB distance from the DMA command buffer: 117 * If you get too close to the DMA command buffer on NV40 and NV43 at least (both 118 * confirmed), the source DMA instance will mess-up for at least engine command 119 * NV_IMAGE_BLIT and NV12_IMAGE_BLIT; 120 * - we need at least ???kB distance from the end of RAM for fifo-reassigning 'bug' 121 * (fixme: unknown yet because fifo assignment switching isn't used here atm); 122 * - keep extra failsafe room to prevent malfunctioning apps from crashing engine. */ 123 #define NV40_PLUS_OFFSET 512 * 1024 124 125 /* fifo re-assigning bug definition: 126 * if the fifo assignment is changed while at the same time card memory in the 127 * dangerous region is being accessed by some application, the engine will crash. 128 * This bug applies for both PIO and DMA mode acceleration! */ 129 130 /* source-DMA instance bug definition: 131 * if card memory in the dangerous region is being accessed by some application while 132 * a DMA command buffer exists in the same memory (though in a different place), 133 * the engine will crash. */ 134 //----------------------------------------------------------------------------------- 135 136 /* internal used info on overlay buffers */ 137 typedef struct { 138 uint16 slopspace; 139 uint32 size; 140 } int_buf_info; 141 142 typedef struct { // apsed, see comments in nv.settings 143 // for driver 144 char accelerant[B_FILE_NAME_LENGTH]; 145 char primary[B_FILE_NAME_LENGTH]; 146 bool dumprom; 147 // for accelerant 148 uint32 logmask; 149 uint32 memory; 150 uint32 tv_output; 151 bool usebios; 152 bool hardcursor; 153 bool switchhead; 154 bool force_pci; 155 bool unhide_fw; 156 bool pgm_panel; 157 bool dma_acc; 158 bool vga_on_tv; 159 } nv_settings; 160 161 /* shared info */ 162 typedef struct { 163 /* a few ID things */ 164 uint16 vendor_id; /* PCI vendor ID, from pci_info */ 165 uint16 device_id; /* PCI device ID, from pci_info */ 166 uint8 revision; /* PCI device revsion, from pci_info */ 167 uint8 bus; /* PCI bus number, from pci_info */ 168 uint8 device; /* PCI device number on bus, from pci_info */ 169 uint8 function; /* PCI function number in device, from pci_info */ 170 171 /* used to return status for INIT_ACCELERANT and CLONE_ACCELERANT */ 172 bool accelerant_in_use; 173 174 /* bug workaround for 4.5.0 */ 175 uint32 use_clone_bugfix; /*for 4.5.0, cloning of physical memory does not work*/ 176 uint32 * clone_bugfix_regs; 177 178 /*memory mappings*/ 179 area_id regs_area; /* Kernel's area_id for the memory mapped registers. 180 It will be cloned into the accelerant's address 181 space. */ 182 183 area_id fb_area; /* Frame buffer's area_id. The addresses are shared with all teams. */ 184 area_id unaligned_dma_area; /* Area assigned for DMA. It will be (partially) mapped to an 185 aligned area using MTRR-WC. */ 186 area_id dma_area; /* Aligned area assigned for DMA. The addresses are shared with all teams. */ 187 188 void *framebuffer; /* As viewed from virtual memory */ 189 void *framebuffer_pci; /* As viewed from the PCI bus (for DMA) */ 190 void *dma_buffer; /* As viewed from virtual memory */ 191 void *dma_buffer_pci; /* As viewed from the PCI bus (for DMA) */ 192 193 /*screenmode list*/ 194 area_id mode_area; /* Contains the list of display modes the driver supports */ 195 uint32 mode_count; /* Number of display modes in the list */ 196 197 /*flags - used by driver*/ 198 uint32 flags; 199 200 /*vblank semaphore*/ 201 sem_id vblank; /* The vertical blank semaphore. Ownership will be 202 transfered to the team opening the device first */ 203 /*cursor information*/ 204 struct { 205 uint16 hot_x; /* Cursor hot spot. The top left corner of the cursor */ 206 uint16 hot_y; /* is 0,0 */ 207 uint16 x; /* The location of the cursor hot spot on the */ 208 uint16 y; /* desktop */ 209 uint16 width; /* Width and height of the cursor shape (always 16!) */ 210 uint16 height; 211 bool is_visible; /* Is the cursor currently displayed? */ 212 bool dh_right; /* Is cursor on right side of stretched screen? */ 213 } cursor; 214 215 /*colour lookup table*/ 216 uint8 color_data[3 * 256]; /* Colour lookup table - as used by DAC */ 217 218 /*more display mode stuff*/ 219 display_mode dm; /* current display mode configuration: head1 */ 220 uint32 dpms_flags; /* current DPMS mode */ 221 bool acc_mode; /* signals (non)accelerated mode */ 222 bool interlaced_tv_mode;/* signals interlaced CRTC TV output mode */ 223 bool crtc_switch_mode; /* signals dualhead switch mode if panels are used */ 224 225 /*frame buffer config - for BDirectScreen*/ 226 frame_buffer_config fbc; /* bytes_per_row and start of frame buffer: head1 */ 227 accelerant_device_info adi; /* as returned by hook GET_ACCELERANT_DEVICE_INFO */ 228 229 /*acceleration engine*/ 230 struct { 231 uint32 count; /* last dwgsync slot used */ 232 uint32 last_idle; /* last dwgsync slot we *know* the engine was idle after */ 233 benaphore lock; /* for serializing access to the acc engine */ 234 struct { 235 uint32 handle[0x08]; /* FIFO channel's cmd handle for the owning cmd */ 236 uint32 ch_ptr[0x20]; /* cmd handle's ptr to it's assigned FIFO ch (if any) */ 237 } fifo; 238 struct { 239 uint32 put; /* last 32-bit-word adress given to engine to exec. to */ 240 uint32 current; /* first free 32-bit-word adress in buffer */ 241 uint32 free; /* nr. of useable free 32-bit words remaining in buffer */ 242 uint32 max; /* command buffer's useable size in 32-bit words */ 243 } dma; 244 bool agp_mode; /* card is running in AGP mode */ 245 struct { 246 uint32 clones; /* clone 'number' (mask, slot) (one bit per clone) */ 247 uint32 reload; /* reload state and surfaces (one bit per clone) */ 248 uint32 newmode; /* re-allocate all buffers (one bit per clone) */ 249 //fixme: memory stuff needs to be expanded (shared texture allocation?) 250 uint32 mem_low; /* ptr to first free mem adress: cardmem local offset */ 251 uint32 mem_high; /* ptr to last free mem adress: cardmem local offset */ 252 bool mode_changing; /* a mode-change is in progress (set/clear by 2D drv) */ 253 } threeD; 254 } engine; 255 256 /* card info - information gathered from PINS (and other sources) */ 257 enum 258 { // card_type in order of date of NV chip design 259 NV04 = 0, 260 NV05, 261 NV05M64, 262 NV06, 263 NV10, 264 NV11, 265 NV11M, 266 NV15, 267 NV17, 268 NV17M, 269 NV18, 270 NV18M, 271 NV20, 272 NV25, 273 NV28, 274 NV30, 275 NV31, 276 NV34, 277 NV35, 278 NV36, 279 NV38, 280 NV40, 281 NV41, 282 NV43, 283 NV44, 284 NV45, 285 NV47 286 }; 287 enum 288 { // card_arch in order of date of NV chip design 289 NV04A = 0, 290 NV10A, 291 NV20A, 292 NV30A, 293 NV40A 294 }; 295 enum 296 { // tv_encoder_type in order of capability (more or less) 297 NONE = 0, 298 CH7003, 299 CH7004, 300 CH7005, 301 CH7006, 302 CH7007, 303 CH7008, 304 SAA7102, 305 SAA7103, 306 SAA7104, 307 SAA7105, 308 BT868, 309 BT869, 310 CX25870, 311 CX25871, 312 NVIDIA 313 }; 314 315 struct 316 { 317 /* specialised registers for card initialisation read from NV BIOS (pins) */ 318 319 /* general card information */ 320 uint32 card_type; /* see card_type enum above */ 321 uint32 card_arch; /* see card_arch enum above */ 322 bool laptop; /* mobile chipset or not ('internal' flatpanel!) */ 323 bool slaved_tmds1; /* external TMDS encoder active on CRTC1 */ 324 bool slaved_tmds2; /* external TMDS encoder active on CRTC2 */ 325 bool master_tmds1; /* on die TMDS encoder active on CRTC1 */ 326 bool master_tmds2; /* on die TMDS encoder active on CRTC2 */ 327 bool tmds1_active; /* found panel on CRTC1 that is active */ 328 bool tmds2_active; /* found panel on CRTC2 that is active */ 329 display_timing p1_timing; /* 'modeline' fetched for panel 1 */ 330 display_timing p2_timing; /* 'modeline' fetched for panel 2 */ 331 float panel1_aspect; /* panel's aspect ratio */ 332 float panel2_aspect; /* panel's aspect ratio */ 333 bool crtc2_prim; /* using CRTC2 as primary CRTC */ 334 bool i2c_bus0; /* we have a wired I2C bus 0 on board */ 335 bool i2c_bus1; /* we have a wired I2C bus 1 on board */ 336 bool i2c_bus2; /* we have a wired I2C bus 2 on board */ 337 bool i2c_bus3; /* we have a wired I2C bus 3 on board */ 338 struct 339 { 340 uint32 type; /* see tvchip_type enum above */ 341 uint8 version; /* chip silicon version */ 342 uint8 bus; /* I2C bus on which TVout chip resides */ 343 uint8 adress; /* I2C adress on which TVout chip resides */ 344 } tv_encoder; 345 uint8 monitors; /* output devices connection matrix */ 346 bool int_assigned; /* card has a useable INT assigned to it */ 347 status_t pins_status; /* B_OK if read correctly, B_ERROR if faked */ 348 349 /* PINS */ 350 float f_ref; /* PLL reference-oscillator frequency (Mhz) */ 351 bool ext_pll; /* the extended PLL contains more dividers */ 352 uint32 max_system_vco; /* graphics engine PLL VCO limits (Mhz) */ 353 uint32 min_system_vco; 354 uint32 max_pixel_vco; /* dac1 PLL VCO limits (Mhz) */ 355 uint32 min_pixel_vco; 356 uint32 max_video_vco; /* dac2 PLL VCO limits (Mhz) */ 357 uint32 min_video_vco; 358 uint32 std_engine_clock; /* graphics engine clock speed needed (Mhz) */ 359 uint32 std_memory_clock; /* card memory clock speed needed (Mhz) */ 360 uint32 max_dac1_clock; /* dac1 limits (Mhz) */ 361 uint32 max_dac1_clock_8; /* dac1 limits correlated to RAMspeed limits (Mhz) */ 362 uint32 max_dac1_clock_16; 363 uint32 max_dac1_clock_24; 364 uint32 max_dac1_clock_32; 365 uint32 max_dac1_clock_32dh; 366 uint32 max_dac2_clock; /* dac2 limits (Mhz) */ 367 uint32 max_dac2_clock_8; /* dac2, maven limits correlated to RAMspeed limits (Mhz) */ 368 uint32 max_dac2_clock_16; 369 uint32 max_dac2_clock_24; 370 uint32 max_dac2_clock_32; 371 uint32 max_dac2_clock_32dh; 372 bool secondary_head; /* presence of functions */ 373 bool tvout; 374 bool primary_dvi; 375 bool secondary_dvi; 376 uint32 memory_size; /* memory (in bytes) */ 377 } ps; 378 379 /* mirror of the ROM (copied in driver, because may not be mapped permanently) */ 380 uint8 rom_mirror[65536]; 381 382 /* some configuration settings from ~/config/settings/kernel/drivers/nv.settings if exists */ 383 nv_settings settings; 384 385 struct 386 { 387 overlay_buffer myBuffer[MAXBUFFERS];/* scaler input buffers */ 388 int_buf_info myBufInfo[MAXBUFFERS]; /* extra info on scaler input buffers */ 389 overlay_token myToken; /* scaler is free/in use */ 390 benaphore lock; /* for creating buffers and aquiring overlay unit routines */ 391 bool crtc; /* location of overlay unit */ 392 /* variables needed for virtualscreens (move_overlay()): */ 393 bool active; /* true is overlay currently in use */ 394 overlay_window ow; /* current position of overlay output window */ 395 overlay_buffer ob; /* current inputbuffer in use */ 396 overlay_view my_ov; /* current corrected view in inputbuffer */ 397 uint32 h_ifactor; /* current 'unclipped' horizontal inverse scaling factor */ 398 uint32 v_ifactor; /* current 'unclipped' vertical inverse scaling factor */ 399 } overlay; 400 401 } shared_info; 402 403 /* Read or write a value in PCI configuration space */ 404 typedef struct { 405 uint32 magic; /* magic number to make sure the caller groks us */ 406 uint32 offset; /* Offset to read/write */ 407 uint32 size; /* Number of bytes to transfer */ 408 uint32 value; /* The value read or written */ 409 } nv_get_set_pci; 410 411 /* Set some boolean condition (like enabling or disabling interrupts) */ 412 typedef struct { 413 uint32 magic; /* magic number to make sure the caller groks us */ 414 bool do_it; /* state to set */ 415 } nv_set_bool_state; 416 417 /* Retrieve the area_id of the kernel/accelerant shared info */ 418 typedef struct { 419 uint32 magic; /* magic number to make sure the caller groks us */ 420 area_id shared_info_area; /* area_id containing the shared information */ 421 } nv_get_private_data; 422 423 /* Retrieve the device name. Usefull for when we have a file handle, but want 424 to know the device name (like when we are cloning the accelerant) */ 425 typedef struct { 426 uint32 magic; /* magic number to make sure the caller groks us */ 427 char *name; /* The name of the device, less the /dev root */ 428 } nv_device_name; 429 430 /* Retrieve an AGP device interface if there. Usefull to find the AGP speed scheme 431 used (pre 3.x or 3.x) */ 432 typedef struct { 433 uint32 magic; /* magic number to make sure the caller groks us */ 434 bool agp_bus;/* indicates if we have access to the AGP busmanager */ 435 uint8 index; /* device index in list of devices found */ 436 bool exist; /* we got AGP device info */ 437 agp_info agpi; /* AGP interface info of a device */ 438 } nv_nth_agp_info; 439 440 /* Execute an AGP command */ 441 typedef struct { 442 uint32 magic; /* magic number to make sure the caller groks us */ 443 bool agp_bus;/* indicates if we have access to the AGP busmanager */ 444 uint32 cmd; /* actual command to execute */ 445 } nv_cmd_agp; 446 447 /* Read or write a value in ISA I/O space */ 448 typedef struct { 449 uint32 magic; /* magic number to make sure the caller groks us */ 450 uint16 adress; /* Offset to read/write */ 451 uint8 size; /* Number of bytes to transfer */ 452 uint16 data; /* The value read or written */ 453 } nv_in_out_isa; 454 455 enum { 456 457 _WAIT_FOR_VBLANK = (1 << 0) 458 }; 459 460 #if defined(__cplusplus) 461 } 462 #endif 463 464 465 #endif 466