1 /* 2 Copyright 1999, Be Incorporated. All Rights Reserved. 3 This file may be used under the terms of the Be Sample Code License. 4 5 Other authors: 6 Mark Watson; 7 Apsed; 8 Rudolf Cornelissen 10/2002-6/2009. 9 */ 10 11 #ifndef DRIVERINTERFACE_H 12 #define DRIVERINTERFACE_H 13 14 #include <Accelerant.h> 15 #include "video_overlay.h" 16 #include <Drivers.h> 17 #include <PCI.h> 18 #include <OS.h> 19 #include "AGP.h" 20 21 #define DRIVER_PREFIX "nvidia" 22 #define DEVICE_FORMAT "%04x_%04x_%02x%02x%02x" 23 24 /* 25 Internal driver state (also for sharing info between driver and accelerant) 26 */ 27 #if defined(__cplusplus) 28 extern "C" { 29 #endif 30 31 typedef struct { 32 sem_id sem; 33 int32 ben; 34 } benaphore; 35 36 #define INIT_BEN(x) x.sem = create_sem(0, "NV "#x" benaphore"); x.ben = 0; 37 #define AQUIRE_BEN(x) if((atomic_add(&(x.ben), 1)) >= 1) acquire_sem(x.sem); 38 #define RELEASE_BEN(x) if((atomic_add(&(x.ben), -1)) > 1) release_sem(x.sem); 39 #define DELETE_BEN(x) delete_sem(x.sem); 40 41 42 #define NV_PRIVATE_DATA_MAGIC 0x0009 /* a private driver rev, of sorts */ 43 44 /* dualhead extensions to flags */ 45 #define DUALHEAD_OFF (0<<6) 46 #define DUALHEAD_CLONE (1<<6) 47 #define DUALHEAD_ON (2<<6) 48 #define DUALHEAD_SWITCH (3<<6) 49 #define DUALHEAD_BITS (3<<6) 50 #define DUALHEAD_CAPABLE (1<<8) 51 #define TV_BITS (3<<9) 52 #define TV_MON (0<<9 53 #define TV_PAL (1<<9) 54 #define TV_NTSC (2<<9) 55 #define TV_CAPABLE (1<<11) 56 #define TV_VIDEO (1<<12) 57 #define TV_PRIMARY (1<<13) 58 59 #define SKD_MOVE_CURSOR 0x00000001 60 #define SKD_PROGRAM_CLUT 0x00000002 61 #define SKD_SET_START_ADDR 0x00000004 62 #define SKD_SET_CURSOR 0x00000008 63 #define SKD_HANDLER_INSTALLED 0x80000000 64 65 enum { 66 NV_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1, 67 NV_GET_PCI, 68 NV_SET_PCI, 69 NV_DEVICE_NAME, 70 NV_RUN_INTERRUPTS, 71 NV_GET_NTH_AGP_INFO, 72 NV_ENABLE_AGP, 73 NV_ISA_OUT, 74 NV_ISA_IN 75 }; 76 77 /* card_type in order of date of NV chip design */ 78 enum { 79 NV04 = 0, 80 NV05, 81 NV05M64, 82 NV06, 83 NV10, 84 NV11, 85 NV11M, 86 NV15, 87 NV17, 88 NV17M, 89 NV18, 90 NV18M, 91 NV20, 92 NV25, 93 NV28, 94 NV30, 95 NV31, 96 NV34, 97 NV35, 98 NV36, 99 NV38, 100 NV40, 101 NV41, 102 NV43, 103 NV44, 104 NV45, 105 G70, 106 G71, 107 G72, 108 G73 109 }; 110 111 /* card_arch in order of date of NV chip design */ 112 enum { 113 NV04A = 0, 114 NV10A, 115 NV20A, 116 NV30A, 117 NV40A 118 }; 119 120 /* card info - information gathered from PINS (and other sources) */ 121 enum 122 { // tv_encoder_type in order of capability (more or less) 123 NONE = 0, 124 CH7003, 125 CH7004, 126 CH7005, 127 CH7006, 128 CH7007, 129 CH7008, 130 SAA7102, 131 SAA7103, 132 SAA7104, 133 SAA7105, 134 BT868, 135 BT869, 136 CX25870, 137 CX25871, 138 NVIDIA 139 }; 140 141 /* handles to pre-defined engine commands */ 142 #define NV_ROP5_SOLID 0x00000000 /* 2D */ 143 #define NV_IMAGE_BLACK_RECTANGLE 0x00000001 /* 2D/3D */ 144 #define NV_IMAGE_PATTERN 0x00000002 /* 2D */ 145 #define NV_SCALED_IMAGE_FROM_MEMORY 0x00000003 /* 2D */ 146 #define NV_TCL_PRIMITIVE_3D 0x00000004 /* 3D */ //2007 147 #define NV4_SURFACE 0x00000010 /* 2D */ 148 #define NV10_CONTEXT_SURFACES_2D 0x00000010 /* 2D */ 149 #define NV_IMAGE_BLIT 0x00000011 /* 2D */ 150 #define NV12_IMAGE_BLIT 0x00000011 /* 2D */ 151 /* fixme: 152 * never use NV3_GDI_RECTANGLE_TEXT for DMA acceleration: 153 * There's a hardware fault in the input->output colorspace conversion here. 154 * Besides, in NV40 and up this command nolonger exists. Both 'facts' are confirmed 155 * by testing. 156 */ 157 //#define NV3_GDI_RECTANGLE_TEXT 0x00000012 /* 2D */ 158 #define NV4_GDI_RECTANGLE_TEXT 0x00000012 /* 2D */ 159 #define NV4_CONTEXT_SURFACES_ARGB_ZS 0x00000013 /* 3D */ 160 #define NV10_CONTEXT_SURFACES_ARGB_ZS 0x00000013 /* 3D */ 161 #define NV4_DX5_TEXTURE_TRIANGLE 0x00000014 /* 3D */ 162 #define NV10_DX5_TEXTURE_TRIANGLE 0x00000014 /* 3D */ 163 #define NV4_DX6_MULTI_TEXTURE_TRIANGLE 0x00000015 /* unused (yet?) */ 164 #define NV10_DX6_MULTI_TEXTURE_TRIANGLE 0x00000015 /* unused (yet?) */ 165 #define NV1_RENDER_SOLID_LIN 0x00000016 /* 2D: unused */ 166 167 /* max. number of overlay buffers */ 168 #define MAXBUFFERS 3 169 170 //----------------------------------------------------------------------------------- 171 /* safety byte-offset from end of cardRAM for preventing acceleration engine crashes 172 * caused by the existance of DMA engine command buffers in cardRAM and/or fifo 173 * channel engine command re-assigning on-the-fly */ 174 175 /* pre-NV40 notes: 176 * - we need at least 70kB distance from the end of RAM for fifo-reassigning 'bug' 177 * (confirmed on a TNT1); 178 * - keep extra failsafe room to prevent malfunctioning apps from crashing engine. */ 179 #define PRE_NV40_OFFSET 80 * 1024 180 181 /* NV40 and higher notes: 182 * - we need at least 416kB distance from the DMA command buffer: 183 * If you get too close to the DMA command buffer on NV40 and NV43 at least (both 184 * confirmed), the source DMA instance will mess-up for at least engine command 185 * NV_IMAGE_BLIT and NV12_IMAGE_BLIT; 186 * - we need at least ???kB distance from the end of RAM for fifo-reassigning 'bug' 187 * (fixme: unknown yet because fifo assignment switching isn't used here atm); 188 * - keep extra failsafe room to prevent malfunctioning apps from crashing engine. */ 189 #define NV40_PLUS_OFFSET 512 * 1024 190 191 /* fifo re-assigning bug definition: 192 * if the fifo assignment is changed while at the same time card memory in the 193 * dangerous region is being accessed by some application, the engine will crash. 194 * This bug applies for both PIO and DMA mode acceleration! */ 195 196 /* source-DMA instance bug definition: 197 * if card memory in the dangerous region is being accessed by some application while 198 * a DMA command buffer exists in the same memory (though in a different place), 199 * the engine will crash. */ 200 //----------------------------------------------------------------------------------- 201 202 /* internal used info on overlay buffers */ 203 typedef struct { 204 uint16 slopspace; 205 uint32 size; 206 } int_buf_info; 207 208 typedef struct { // apsed, see comments in nvidia.settings 209 // for driver 210 char accelerant[B_FILE_NAME_LENGTH]; 211 char primary[B_FILE_NAME_LENGTH]; 212 bool dumprom; 213 // for accelerant 214 uint32 logmask; 215 uint32 memory; 216 uint32 tv_output; 217 bool usebios; 218 bool hardcursor; 219 bool switchhead; 220 bool force_pci; 221 bool unhide_fw; 222 bool pgm_panel; 223 bool dma_acc; 224 bool vga_on_tv; 225 bool force_sync; 226 bool force_ws; 227 bool block_acc; 228 uint32 gpu_clk; 229 uint32 ram_clk; 230 } nv_settings; 231 232 /* monitor info gathered via EDID */ 233 typedef struct { 234 bool have_edid; /* have read useable edid info from screen */ 235 bool digital; /* screen connection type: analog (VGA) or digital (DVI) */ 236 display_timing timing; /* 'native modeline' fetched for screen */ 237 float aspect; /* screen's aspect ratio */ 238 } edid_specs; 239 240 /* shared info */ 241 typedef struct { 242 /* a few ID things */ 243 uint16 vendor_id; /* PCI vendor ID, from pci_info */ 244 uint16 device_id; /* PCI device ID, from pci_info */ 245 uint8 revision; /* PCI device revsion, from pci_info */ 246 uint8 bus; /* PCI bus number, from pci_info */ 247 uint8 device; /* PCI device number on bus, from pci_info */ 248 uint8 function; /* PCI function number in device, from pci_info */ 249 250 /* used to return status for INIT_ACCELERANT and CLONE_ACCELERANT */ 251 bool accelerant_in_use; 252 253 /* bug workaround for 4.5.0 */ 254 uint32 use_clone_bugfix; /*for 4.5.0, cloning of physical memory does not work*/ 255 uint32 * clone_bugfix_regs; 256 257 /*memory mappings*/ 258 area_id regs_area; /* Kernel's area_id for the memory mapped registers. 259 It will be cloned into the accelerant's address 260 space. */ 261 262 area_id fb_area; /* Frame buffer's area_id. The addresses are shared with all teams. */ 263 area_id unaligned_dma_area; /* Area assigned for DMA. It will be (partially) mapped to an 264 aligned area using MTRR-WC. */ 265 area_id dma_area; /* Aligned area assigned for DMA. The addresses are shared with all teams. */ 266 267 void *framebuffer; /* As viewed from virtual memory */ 268 void *framebuffer_pci; /* As viewed from the PCI bus (for DMA) */ 269 void *dma_buffer; /* As viewed from virtual memory */ 270 void *dma_buffer_pci; /* As viewed from the PCI bus (for DMA) */ 271 272 /*screenmode list*/ 273 area_id mode_area; /* Contains the list of display modes the driver supports */ 274 uint32 mode_count; /* Number of display modes in the list */ 275 276 /*flags - used by driver*/ 277 uint32 flags; 278 279 /*vblank semaphore*/ 280 sem_id vblank; /* The vertical blank semaphore. Ownership will be 281 transfered to the team opening the device first */ 282 /*cursor information*/ 283 struct { 284 uint16 hot_x; /* Cursor hot spot. The top left corner of the cursor */ 285 uint16 hot_y; /* is 0,0 */ 286 uint16 x; /* The location of the cursor hot spot on the */ 287 uint16 y; /* desktop */ 288 uint16 width; /* Width and height of the cursor shape (always 16!) */ 289 uint16 height; 290 bool is_visible; /* Is the cursor currently displayed? */ 291 bool dh_right; /* Is cursor on right side of stretched screen? */ 292 } cursor; 293 294 /*colour lookup table*/ 295 uint8 color_data[3 * 256]; /* Colour lookup table - as used by DAC */ 296 297 /*more display mode stuff*/ 298 display_mode dm; /* current display mode configuration: head1 */ 299 uint32 dpms_flags; /* current DPMS mode */ 300 bool acc_mode; /* signals (non)accelerated mode */ 301 bool interlaced_tv_mode;/* signals interlaced CRTC TV output mode */ 302 bool crtc_switch_mode; /* signals dualhead switch mode if panels are used */ 303 304 /*frame buffer config - for BDirectScreen*/ 305 frame_buffer_config fbc; /* bytes_per_row and start of frame buffer: head1 */ 306 accelerant_device_info adi; /* as returned by hook GET_ACCELERANT_DEVICE_INFO */ 307 308 /*acceleration engine*/ 309 struct { 310 uint32 count; /* last dwgsync slot used */ 311 uint32 last_idle; /* last dwgsync slot we *know* the engine was idle after */ 312 benaphore lock; /* for serializing access to the acc engine */ 313 struct { 314 uint32 handle[0x08]; /* FIFO channel's cmd handle for the owning cmd */ 315 uint32 ch_ptr[0x20]; /* cmd handle's ptr to it's assigned FIFO ch (if any) */ 316 } fifo; 317 struct { 318 uint32 put; /* last 32-bit-word adress given to engine to exec. to */ 319 uint32 current; /* first free 32-bit-word adress in buffer */ 320 uint32 free; /* nr. of useable free 32-bit words remaining in buffer */ 321 uint32 max; /* command buffer's useable size in 32-bit words */ 322 } dma; 323 bool agp_mode; /* card is running in AGP mode */ 324 struct { 325 uint32 clones; /* clone 'number' (mask, slot) (one bit per clone) */ 326 uint32 reload; /* reload state and surfaces (one bit per clone) */ 327 uint32 newmode; /* re-allocate all buffers (one bit per clone) */ 328 //fixme: memory stuff needs to be expanded (shared texture allocation?) 329 uint32 mem_low; /* ptr to first free mem adress: cardmem local offset */ 330 uint32 mem_high; /* ptr to last free mem adress: cardmem local offset */ 331 bool mode_changing; /* a mode-change is in progress (set/clear by 2D drv) */ 332 } threeD; 333 } engine; 334 335 struct 336 { 337 /* specialised registers for card initialisation read from NV BIOS (pins) */ 338 339 /* general card information */ 340 uint32 card_type; /* see card_type enum above */ 341 uint32 card_arch; /* see card_arch enum above */ 342 bool laptop; /* mobile chipset or not ('internal' flatpanel!) */ 343 bool slaved_tmds1; /* external TMDS encoder active on CRTC1 */ 344 bool slaved_tmds2; /* external TMDS encoder active on CRTC2 */ 345 bool master_tmds1; /* on die TMDS encoder active on CRTC1 */ 346 bool master_tmds2; /* on die TMDS encoder active on CRTC2 */ 347 bool tmds1_active; /* found panel on CRTC1 that is active */ 348 bool tmds2_active; /* found panel on CRTC2 that is active */ 349 display_timing p1_timing; /* 'modeline' fetched for panel 1 */ 350 display_timing p2_timing; /* 'modeline' fetched for panel 2 */ 351 float panel1_aspect; /* panel's aspect ratio */ 352 float panel2_aspect; /* panel's aspect ratio */ 353 edid_specs con1_screen; /* EDID properties of the screen connected to connector 1 */ 354 edid_specs con2_screen; /* EDID properties of the screen connected to connector 2 */ 355 bool crtc2_prim; /* using CRTC2 as primary CRTC */ 356 bool i2c_bus0; /* we have a wired I2C bus 0 on board */ 357 bool i2c_bus1; /* we have a wired I2C bus 1 on board */ 358 bool i2c_bus2; /* we have a wired I2C bus 2 on board */ 359 struct 360 { 361 uint32 type; /* see tvchip_type enum above */ 362 uint8 version; /* chip silicon version */ 363 uint8 bus; /* I2C bus on which TVout chip resides */ 364 uint8 adress; /* I2C adress on which TVout chip resides */ 365 } tv_encoder; 366 uint8 monitors; /* output devices connection matrix */ 367 bool int_assigned; /* card has a useable INT assigned to it */ 368 status_t pins_status; /* B_OK if read correctly, B_ERROR if faked */ 369 370 /* PINS */ 371 float f_ref; /* PLL reference-oscillator frequency (Mhz) */ 372 bool ext_pll; /* the extended PLL contains more dividers */ 373 uint32 max_system_vco; /* graphics engine PLL VCO limits (Mhz) */ 374 uint32 min_system_vco; 375 uint32 max_pixel_vco; /* dac1 PLL VCO limits (Mhz) */ 376 uint32 min_pixel_vco; 377 uint32 max_video_vco; /* dac2 PLL VCO limits (Mhz) */ 378 uint32 min_video_vco; 379 uint32 std_engine_clock; /* graphics engine clock speed needed (Mhz) */ 380 uint32 std_memory_clock; /* card memory clock speed needed (Mhz) */ 381 uint32 max_dac1_clock; /* dac1 limits (Mhz) */ 382 uint32 max_dac1_clock_8; /* dac1 limits correlated to RAMspeed limits (Mhz) */ 383 uint32 max_dac1_clock_16; 384 uint32 max_dac1_clock_24; 385 uint32 max_dac1_clock_32; 386 uint32 max_dac1_clock_32dh; 387 uint32 max_dac2_clock; /* dac2 limits (Mhz) */ 388 uint32 max_dac2_clock_8; /* dac2, maven limits correlated to RAMspeed limits (Mhz) */ 389 uint32 max_dac2_clock_16; 390 uint32 max_dac2_clock_24; 391 uint32 max_dac2_clock_32; 392 uint32 max_dac2_clock_32dh; 393 bool secondary_head; /* presence of functions */ 394 bool tvout; 395 bool primary_dvi; 396 bool secondary_dvi; 397 uint32 memory_size; /* memory (in bytes) */ 398 } ps; 399 400 /* mirror of the ROM (copied in driver, because may not be mapped permanently) */ 401 uint8 rom_mirror[65536]; 402 403 /* some configuration settings from ~/config/settings/kernel/drivers/nv.settings if exists */ 404 nv_settings settings; 405 406 struct 407 { 408 overlay_buffer myBuffer[MAXBUFFERS];/* scaler input buffers */ 409 int_buf_info myBufInfo[MAXBUFFERS]; /* extra info on scaler input buffers */ 410 overlay_token myToken; /* scaler is free/in use */ 411 benaphore lock; /* for creating buffers and aquiring overlay unit routines */ 412 bool crtc; /* location of overlay unit */ 413 /* variables needed for virtualscreens (move_overlay()): */ 414 bool active; /* true is overlay currently in use */ 415 overlay_window ow; /* current position of overlay output window */ 416 overlay_buffer ob; /* current inputbuffer in use */ 417 overlay_view my_ov; /* current corrected view in inputbuffer */ 418 uint32 h_ifactor; /* current 'unclipped' horizontal inverse scaling factor */ 419 uint32 v_ifactor; /* current 'unclipped' vertical inverse scaling factor */ 420 } overlay; 421 422 } shared_info; 423 424 /* Read or write a value in PCI configuration space */ 425 typedef struct { 426 uint32 magic; /* magic number to make sure the caller groks us */ 427 uint32 offset; /* Offset to read/write */ 428 uint32 size; /* Number of bytes to transfer */ 429 uint32 value; /* The value read or written */ 430 } nv_get_set_pci; 431 432 /* Enable or Disable CRTC (1,2) interrupts */ 433 typedef struct { 434 uint32 magic; /* magic number to make sure the caller groks us */ 435 bool crtc; /* adressed CRTC */ 436 bool do_it; /* state to set */ 437 } nv_set_vblank_int; 438 439 /* Retrieve the area_id of the kernel/accelerant shared info */ 440 typedef struct { 441 uint32 magic; /* magic number to make sure the caller groks us */ 442 area_id shared_info_area; /* area_id containing the shared information */ 443 } nv_get_private_data; 444 445 /* Retrieve the device name. Usefull for when we have a file handle, but want 446 to know the device name (like when we are cloning the accelerant) */ 447 typedef struct { 448 uint32 magic; /* magic number to make sure the caller groks us */ 449 char *name; /* The name of the device, less the /dev root */ 450 } nv_device_name; 451 452 /* Retrieve an AGP device interface if there. Usefull to find the AGP speed scheme 453 used (pre 3.x or 3.x) */ 454 typedef struct { 455 uint32 magic; /* magic number to make sure the caller groks us */ 456 bool agp_bus;/* indicates if we have access to the AGP busmanager */ 457 uint8 index; /* device index in list of devices found */ 458 bool exist; /* we got AGP device info */ 459 agp_info agpi; /* AGP interface info of a device */ 460 } nv_nth_agp_info; 461 462 /* Execute an AGP command */ 463 typedef struct { 464 uint32 magic; /* magic number to make sure the caller groks us */ 465 bool agp_bus;/* indicates if we have access to the AGP busmanager */ 466 uint32 cmd; /* actual command to execute */ 467 } nv_cmd_agp; 468 469 /* Read or write a value in ISA I/O space */ 470 typedef struct { 471 uint32 magic; /* magic number to make sure the caller groks us */ 472 uint16 adress; /* Offset to read/write */ 473 uint8 size; /* Number of bytes to transfer */ 474 uint16 data; /* The value read or written */ 475 } nv_in_out_isa; 476 477 enum { 478 479 _WAIT_FOR_VBLANK = (1 << 0) 480 }; 481 482 #if defined(__cplusplus) 483 } 484 #endif 485 486 487 #endif 488