xref: /haiku/headers/private/graphics/nvidia/DriverInterface.h (revision 22440f4105cafc95cc1d49f9bc65bb395c527d86)
1 /*
2 	Copyright 1999, Be Incorporated.   All Rights Reserved.
3 	This file may be used under the terms of the Be Sample Code License.
4 
5 	Other authors:
6 	Mark Watson;
7 	Apsed;
8 	Rudolf Cornelissen 10/2002-10/2009.
9 */
10 
11 #ifndef DRIVERINTERFACE_H
12 #define DRIVERINTERFACE_H
13 
14 #include <Accelerant.h>
15 #include <video_overlay.h>
16 #include <Drivers.h>
17 #include <PCI.h>
18 #include <OS.h>
19 #include <edid.h>
20 #include <AGP.h>
21 
22 #define DRIVER_PREFIX "nvidia"
23 #define DEVICE_FORMAT "%04x_%04x_%02x%02x%02x"
24 
25 /*
26 	Internal driver state (also for sharing info between driver and accelerant)
27 */
28 #if defined(__cplusplus)
29 extern "C" {
30 #endif
31 
32 typedef struct {
33 	sem_id	sem;
34 	int32	ben;
35 } benaphore;
36 
37 #define INIT_BEN(x)		x.sem = create_sem(0, "NV "#x" benaphore");  x.ben = 0;
38 #define AQUIRE_BEN(x)	if((atomic_add(&(x.ben), 1)) >= 1) acquire_sem(x.sem);
39 #define RELEASE_BEN(x)	if((atomic_add(&(x.ben), -1)) > 1) release_sem(x.sem);
40 #define	DELETE_BEN(x)	delete_sem(x.sem);
41 
42 
43 #define NV_PRIVATE_DATA_MAGIC	0x0009 /* a private driver rev, of sorts */
44 
45 /* monitor setup */
46 #define CRTC1_TMDS	0x01
47 #define CRTC2_TMDS	0x10
48 #define CRTC1_VGA	0x02
49 #define CRTC2_VGA	0x20
50 
51 /* dualhead extensions to flags */
52 #define DUALHEAD_OFF (0<<6)
53 #define DUALHEAD_CLONE (1<<6)
54 #define DUALHEAD_ON (2<<6)
55 #define DUALHEAD_SWITCH (3<<6)
56 #define DUALHEAD_BITS (3<<6)
57 #define DUALHEAD_CAPABLE (1<<8)
58 #define TV_BITS (3<<9)
59 #define TV_MON (0<<9)
60 #define TV_PAL (1<<9)
61 #define TV_NTSC (2<<9)
62 #define TV_CAPABLE (1<<11)
63 #define TV_VIDEO (1<<12)
64 #define TV_PRIMARY (1<<13)
65 
66 #define SKD_MOVE_CURSOR    0x00000001
67 #define SKD_PROGRAM_CLUT   0x00000002
68 #define SKD_SET_START_ADDR 0x00000004
69 #define SKD_SET_CURSOR     0x00000008
70 #define SKD_HANDLER_INSTALLED 0x80000000
71 
72 enum {
73 	NV_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1,
74 	NV_GET_PCI,
75 	NV_SET_PCI,
76 	NV_DEVICE_NAME,
77 	NV_RUN_INTERRUPTS,
78 	NV_GET_NTH_AGP_INFO,
79 	NV_ENABLE_AGP,
80 	NV_ISA_OUT,
81 	NV_ISA_IN
82 };
83 
84 /* card_type in order of date of NV chip design */
85 enum {
86 	NV04 = 0,
87 	NV05,
88 	NV05M64,
89 	NV06,
90 	NV10,
91 	NV11,
92 	NV15,
93 	NV17,
94 	NV18,
95 	NV20,
96 	NV25,
97 	NV28,
98 	NV30,
99 	NV31,
100 	NV34,
101 	NV35,
102 	NV36,
103 	NV38,
104 	NV40,
105 	NV41,
106 	NV43,
107 	NV44,
108 	NV45,
109 	G70,
110 	G71,
111 	G72,
112 	G73
113 };
114 
115 /* card_arch in order of date of NV chip design */
116 enum {
117 	NV04A = 0,
118 	NV10A,
119 	NV20A,
120 	NV30A,
121 	NV40A
122 };
123 
124 /* card info - information gathered from PINS (and other sources) */
125 enum
126 {	// tv_encoder_type in order of capability (more or less)
127 	NONE = 0,
128 	CH7003,
129 	CH7004,
130 	CH7005,
131 	CH7006,
132 	CH7007,
133 	CH7008,
134 	SAA7102,
135 	SAA7103,
136 	SAA7104,
137 	SAA7105,
138 	BT868,
139 	BT869,
140 	CX25870,
141 	CX25871,
142 	NVIDIA
143 };
144 
145 /* handles to pre-defined engine commands */
146 #define NV_ROP5_SOLID					0x00000000 /* 2D */
147 #define NV_IMAGE_BLACK_RECTANGLE		0x00000001 /* 2D/3D */
148 #define NV_IMAGE_PATTERN				0x00000002 /* 2D */
149 #define NV_SCALED_IMAGE_FROM_MEMORY		0x00000003 /* 2D */
150 #define NV_TCL_PRIMITIVE_3D				0x00000004 /* 3D */ //2007
151 #define NV4_SURFACE						0x00000010 /* 2D */
152 #define NV10_CONTEXT_SURFACES_2D		0x00000010 /* 2D */
153 #define NV_IMAGE_BLIT					0x00000011 /* 2D */
154 #define NV12_IMAGE_BLIT					0x00000011 /* 2D */
155 /* fixme:
156  * never use NV3_GDI_RECTANGLE_TEXT for DMA acceleration:
157  * There's a hardware fault in the input->output colorspace conversion here.
158  * Besides, in NV40 and up this command nolonger exists. Both 'facts' are confirmed
159  * by testing.
160  */
161 //#define NV3_GDI_RECTANGLE_TEXT			0x00000012 /* 2D */
162 #define NV4_GDI_RECTANGLE_TEXT			0x00000012 /* 2D */
163 #define NV4_CONTEXT_SURFACES_ARGB_ZS	0x00000013 /* 3D */
164 #define NV10_CONTEXT_SURFACES_ARGB_ZS	0x00000013 /* 3D */
165 #define NV4_DX5_TEXTURE_TRIANGLE		0x00000014 /* 3D */
166 #define NV10_DX5_TEXTURE_TRIANGLE		0x00000014 /* 3D */
167 #define NV4_DX6_MULTI_TEXTURE_TRIANGLE	0x00000015 /* unused (yet?) */
168 #define NV10_DX6_MULTI_TEXTURE_TRIANGLE	0x00000015 /* unused (yet?) */
169 #define NV1_RENDER_SOLID_LIN			0x00000016 /* 2D: unused */
170 
171 /* max. number of overlay buffers */
172 #define MAXBUFFERS 3
173 
174 //-----------------------------------------------------------------------------------
175 /* safety byte-offset from end of cardRAM for preventing acceleration engine crashes
176  * caused by the existance of DMA engine command buffers in cardRAM and/or fifo
177  * channel engine command re-assigning on-the-fly */
178 
179 /* pre-NV40 notes:
180  * - we need at least 70kB distance from the end of RAM for fifo-reassigning 'bug'
181  *   (confirmed on a TNT1);
182  * - keep extra failsafe room to prevent malfunctioning apps from crashing engine. */
183 #define PRE_NV40_OFFSET		80 * 1024
184 
185 /* NV40 and higher notes:
186  * - we need at least 416kB distance from the DMA command buffer:
187  *   If you get too close to the DMA command buffer on NV40 and NV43 at least (both
188  *   confirmed), the source DMA instance will mess-up for at least engine command
189  *   NV_IMAGE_BLIT and NV12_IMAGE_BLIT;
190  * - we need at least ???kB distance from the end of RAM for fifo-reassigning 'bug'
191  *   (fixme: unknown yet because fifo assignment switching isn't used here atm);
192  * - keep extra failsafe room to prevent malfunctioning apps from crashing engine. */
193 #define NV40_PLUS_OFFSET	512 * 1024
194 
195 /* fifo re-assigning bug definition:
196  * if the fifo assignment is changed while at the same time card memory in the
197  * dangerous region is being accessed by some application, the engine will crash.
198  * This bug applies for both PIO and DMA mode acceleration! */
199 
200 /* source-DMA instance bug definition:
201  * if card memory in the dangerous region is being accessed by some application while
202  * a DMA command buffer exists in the same memory (though in a different place),
203  * the engine will crash. */
204 //-----------------------------------------------------------------------------------
205 
206 /* internal used info on overlay buffers */
207 typedef	struct {
208 	uint16 slopspace;
209 	uint32 size;
210 } int_buf_info;
211 
212 typedef struct { // apsed, see comments in nvidia.settings
213 	// for driver
214 	char   accelerant[B_FILE_NAME_LENGTH];
215 	char   primary[B_FILE_NAME_LENGTH];
216 	bool   dumprom;
217 	// for accelerant
218 	uint32 logmask;
219 	uint32 memory;
220 	uint32 tv_output;
221 	bool   usebios;
222 	bool   hardcursor;
223 	bool   switchhead;
224 	bool   force_pci;
225 	bool   unhide_fw;
226 	bool   pgm_panel;
227 	bool   dma_acc;
228 	bool   vga_on_tv;
229 	bool   force_sync;
230 	bool   force_ws;
231 	bool   block_acc;
232 	uint32 gpu_clk;
233 	uint32 ram_clk;
234 } nv_settings;
235 
236 /* monitor info gathered via EDID */
237 typedef struct {
238 	bool have_native_edid;	/* gathered 'native' EDID either via DDC or via GPU */
239 	bool digital;			/* screen connection type: analog (VGA) or digital (DVI) */
240 	display_timing timing;	/* 'native modeline' fetched for screen */
241 	float aspect;			/* screen's aspect ratio */
242 	bool have_full_edid;	/* EDID read succesfully via DDC  */
243 	edid1_info full_edid;	/* complete EDID info as fetched via DDC */
244 } edid_specs;
245 
246 /* shared info */
247 typedef struct {
248   /* a few ID things */
249 	uint16	vendor_id;	/* PCI vendor ID, from pci_info */
250 	uint16	device_id;	/* PCI device ID, from pci_info */
251 	uint8	revision;	/* PCI device revsion, from pci_info */
252 	uint8	bus;		/* PCI bus number, from pci_info */
253 	uint8	device;		/* PCI device number on bus, from pci_info */
254 	uint8	function;	/* PCI function number in device, from pci_info */
255 
256   /* used to return status for INIT_ACCELERANT and CLONE_ACCELERANT */
257 	bool	accelerant_in_use;
258 
259   /* bug workaround for 4.5.0 */
260 	uint32 use_clone_bugfix;	/*for 4.5.0, cloning of physical memory does not work*/
261 	uint32 * clone_bugfix_regs;
262 
263   /*memory mappings*/
264 	area_id	regs_area;	/* Kernel's area_id for the memory mapped registers.
265 							It will be cloned into the accelerant's	address
266 							space. */
267 
268 	area_id	fb_area;	/* Frame buffer's area_id.  The addresses are shared with all teams. */
269 	area_id	unaligned_dma_area;	/* Area assigned for DMA. It will be (partially) mapped to an
270 									aligned area using MTRR-WC. */
271 	area_id	dma_area;	/* Aligned area assigned for DMA. The addresses are shared with all teams. */
272 
273 	void	*framebuffer;		/* As viewed from virtual memory */
274 	void	*framebuffer_pci;	/* As viewed from the PCI bus (for DMA) */
275 	void	*dma_buffer;		/* As viewed from virtual memory */
276 	void	*dma_buffer_pci;	/* As viewed from the PCI bus (for DMA) */
277 
278   /*screenmode list*/
279 	area_id	mode_area;              /* Contains the list of display modes the driver supports */
280 	uint32	mode_count;             /* Number of display modes in the list */
281 
282   /*flags - used by driver*/
283 	uint32 flags;
284 
285   /*vblank semaphore*/
286 	sem_id	vblank;	                /* The vertical blank semaphore. Ownership will be
287 						transfered to the team opening the device first */
288   /*cursor information*/
289 	struct {
290 		uint16	hot_x;		/* Cursor hot spot. The top left corner of the cursor */
291 		uint16	hot_y;		/* is 0,0 */
292 		uint16	x;		/* The location of the cursor hot spot on the */
293 		uint16	y;		/* desktop */
294 		uint16	width;		/* Width and height of the cursor shape (always 16!) */
295 		uint16	height;
296 		bool	is_visible;	/* Is the cursor currently displayed? */
297 		bool	dh_right;	/* Is cursor on right side of stretched screen? */
298 	} cursor;
299 
300   /*colour lookup table*/
301 	uint8	color_data[3 * 256];	/* Colour lookup table - as used by DAC */
302 
303   /*more display mode stuff*/
304 	display_mode dm;		/* current display mode configuration: head1 */
305 	uint32 dpms_flags;		/* current DPMS mode */
306 	bool acc_mode;			/* signals (non)accelerated mode */
307 	bool interlaced_tv_mode;/* signals interlaced CRTC TV output mode */
308 	bool crtc_switch_mode;	/* signals dualhead switch mode if panels are used */
309 
310   /*frame buffer config - for BDirectScreen*/
311 	frame_buffer_config fbc;	/* bytes_per_row and start of frame buffer: head1 */
312 	accelerant_device_info adi;	/* as returned by hook GET_ACCELERANT_DEVICE_INFO */
313 
314   /*acceleration engine*/
315 	struct {
316 		uint32		count;		/* last dwgsync slot used */
317 		uint32		last_idle;	/* last dwgsync slot we *know* the engine was idle after */
318 		benaphore	lock;		/* for serializing access to the acc engine */
319 		struct {
320 			uint32	handle[0x08];	/* FIFO channel's cmd handle for the owning cmd */
321 			uint32	ch_ptr[0x20];	/* cmd handle's ptr to it's assigned FIFO ch (if any) */
322 		} fifo;
323 		struct {
324 			uint32 put;			/* last 32-bit-word adress given to engine to exec. to */
325 			uint32 current;		/* first free 32-bit-word adress in buffer */
326 			uint32 free;		/* nr. of useable free 32-bit words remaining in buffer */
327 			uint32 max;			/* command buffer's useable size in 32-bit words */
328 		} dma;
329 		bool agp_mode;			/* card is running in AGP mode */
330 		struct {
331 			uint32 clones;		/* clone 'number' (mask, slot) (one bit per clone) */
332 			uint32 reload;		/* reload state and surfaces (one bit per clone) */
333 			uint32 newmode;		/* re-allocate all buffers (one bit per clone) */
334 			//fixme: memory stuff needs to be expanded (shared texture allocation?)
335 			uint32 mem_low;		/* ptr to first free mem adress: cardmem local offset */
336 			uint32 mem_high;	/* ptr to last free mem adress: cardmem local offset */
337 			bool mode_changing;	/* a mode-change is in progress (set/clear by 2D drv) */
338 		} threeD;
339 	} engine;
340 
341 	struct
342 	{
343 		/* specialised registers for card initialisation read from NV BIOS (pins) */
344 
345 		/* general card information */
346 		uint32 card_type;           /* see card_type enum above */
347 		uint32 card_arch;           /* see card_arch enum above */
348 		bool laptop;	            /* mobile chipset or not ('internal' flatpanel!) */
349 		bool slaved_tmds1;			/* external TMDS encoder active on CRTC1 */
350 		bool slaved_tmds2;			/* external TMDS encoder active on CRTC2 */
351 		bool master_tmds1;			/* on die TMDS encoder active on CRTC1 */
352 		bool master_tmds2;			/* on die TMDS encoder active on CRTC2 */
353 		display_timing p1_timing;	/* 'modeline' fetched for panel at CRTC1 */
354 		display_timing p2_timing;	/* 'modeline' fetched for panel at CRTC2 */
355 		edid_specs con1_screen;		/* EDID properties of the screen connected to connector 1 */
356 		edid_specs con2_screen;		/* EDID properties of the screen connected to connector 2 */
357 		edid_specs crtc1_screen;	/* EDID properties of the screen connected to CRTC1 */
358 		edid_specs crtc2_screen;	/* EDID properties of the screen connected to CRTC2 */
359 		bool crtc2_prim;			/* using CRTC2 as primary CRTC */
360 		bool i2c_bus0;				/* we have a wired I2C bus 0 on board */
361 		bool i2c_bus1;				/* we have a wired I2C bus 1 on board */
362 		bool i2c_bus2;				/* we have a wired I2C bus 2 on board */
363 		struct
364 		{
365 			uint32 type;			/* see tvchip_type enum above */
366 			uint8 version;			/* chip silicon version */
367 			uint8 bus;				/* I2C bus on which TVout chip resides */
368 			uint8 adress;			/* I2C adress on which TVout chip resides */
369 		} tv_encoder;
370 		uint8 monitors;				/* output devices connection matrix */
371 		bool int_assigned;			/* card has a useable INT assigned to it */
372 		status_t pins_status;		/* B_OK if read correctly, B_ERROR if faked */
373 
374 		/* PINS */
375 		float f_ref;				/* PLL reference-oscillator frequency (Mhz) */
376 		bool ext_pll;				/* the extended PLL contains more dividers */
377 		uint32 max_system_vco;		/* graphics engine PLL VCO limits (Mhz) */
378 		uint32 min_system_vco;
379 		uint32 max_pixel_vco;		/* dac1 PLL VCO limits (Mhz) */
380 		uint32 min_pixel_vco;
381 		uint32 max_video_vco;		/* dac2 PLL VCO limits (Mhz) */
382 		uint32 min_video_vco;
383 		uint32 std_engine_clock;	/* graphics engine clock speed needed (Mhz) */
384 		uint32 std_memory_clock;	/* card memory clock speed needed (Mhz) */
385 		uint32 max_dac1_clock;		/* dac1 limits (Mhz) */
386 		uint32 max_dac1_clock_8;	/* dac1 limits correlated to RAMspeed limits (Mhz) */
387 		uint32 max_dac1_clock_16;
388 		uint32 max_dac1_clock_24;
389 		uint32 max_dac1_clock_32;
390 		uint32 max_dac1_clock_32dh;
391 		uint32 max_dac2_clock;		/* dac2 limits (Mhz) */
392 		uint32 max_dac2_clock_8;	/* dac2, maven limits correlated to RAMspeed limits (Mhz) */
393 		uint32 max_dac2_clock_16;
394 		uint32 max_dac2_clock_24;
395 		uint32 max_dac2_clock_32;
396 		uint32 max_dac2_clock_32dh;
397 		bool secondary_head;		/* presence of functions */
398 		bool tvout;
399 		bool primary_dvi;
400 		bool secondary_dvi;
401 		uint32 memory_size;			/* memory (in bytes) */
402 	} ps;
403 
404 	/* mirror of the ROM (copied in driver, because may not be mapped permanently) */
405 	uint8 rom_mirror[65536];
406 
407 	/* some configuration settings from ~/config/settings/kernel/drivers/nv.settings if exists */
408 	nv_settings settings;
409 
410 	struct
411 	{
412 		overlay_buffer myBuffer[MAXBUFFERS];/* scaler input buffers */
413 		int_buf_info myBufInfo[MAXBUFFERS];	/* extra info on scaler input buffers */
414 		overlay_token myToken;				/* scaler is free/in use */
415 		benaphore lock;						/* for creating buffers and aquiring overlay unit routines */
416 		bool crtc;							/* location of overlay unit */
417 		/* variables needed for virtualscreens (move_overlay()): */
418 		bool active;						/* true is overlay currently in use */
419 		overlay_window ow;					/* current position of overlay output window */
420 		overlay_buffer ob;					/* current inputbuffer in use */
421 		overlay_view my_ov;					/* current corrected view in inputbuffer */
422 		uint32 h_ifactor;					/* current 'unclipped' horizontal inverse scaling factor */
423 		uint32 v_ifactor;					/* current 'unclipped' vertical inverse scaling factor */
424 	} overlay;
425 
426 } shared_info;
427 
428 /* Read or write a value in PCI configuration space */
429 typedef struct {
430 	uint32	magic;		/* magic number to make sure the caller groks us */
431 	uint32	offset;		/* Offset to read/write */
432 	uint32	size;		/* Number of bytes to transfer */
433 	uint32	value;		/* The value read or written */
434 } nv_get_set_pci;
435 
436 /* Enable or Disable CRTC (1,2) interrupts */
437 typedef struct {
438 	uint32	magic;		/* magic number to make sure the caller groks us */
439 	bool	crtc;		/* adressed CRTC */
440 	bool	do_it;		/* state to set */
441 } nv_set_vblank_int;
442 
443 /* Retrieve the area_id of the kernel/accelerant shared info */
444 typedef struct {
445 	uint32	magic;		/* magic number to make sure the caller groks us */
446 	area_id	shared_info_area;	/* area_id containing the shared information */
447 } nv_get_private_data;
448 
449 /* Retrieve the device name.  Usefull for when we have a file handle, but want
450 to know the device name (like when we are cloning the accelerant) */
451 typedef struct {
452 	uint32	magic;		/* magic number to make sure the caller groks us */
453 	char	*name;		/* The name of the device, less the /dev root */
454 } nv_device_name;
455 
456 /* Retrieve an AGP device interface if there. Usefull to find the AGP speed scheme
457 used (pre 3.x or 3.x) */
458 typedef struct {
459 	uint32		magic;	/* magic number to make sure the caller groks us */
460 	bool		agp_bus;/* indicates if we have access to the AGP busmanager */
461 	uint8		index;	/* device index in list of devices found */
462 	bool		exist;	/* we got AGP device info */
463 	agp_info	agpi;	/* AGP interface info of a device */
464 } nv_nth_agp_info;
465 
466 /* Execute an AGP command */
467 typedef struct {
468 	uint32		magic;	/* magic number to make sure the caller groks us */
469 	bool		agp_bus;/* indicates if we have access to the AGP busmanager */
470 	uint32		cmd;	/* actual command to execute */
471 } nv_cmd_agp;
472 
473 /* Read or write a value in ISA I/O space */
474 typedef struct {
475 	uint32	magic;		/* magic number to make sure the caller groks us */
476 	uint16	adress;		/* Offset to read/write */
477 	uint8	size;		/* Number of bytes to transfer */
478 	uint16	data;		/* The value read or written */
479 } nv_in_out_isa;
480 
481 enum {
482 
483 	_WAIT_FOR_VBLANK = (1 << 0)
484 };
485 
486 #if defined(__cplusplus)
487 }
488 #endif
489 
490 
491 #endif
492