1 /* 2 Copyright 1999, Be Incorporated. All Rights Reserved. 3 This file may be used under the terms of the Be Sample Code License. 4 5 Other authors: 6 Mark Watson; 7 Apsed; 8 Rudolf Cornelissen 10/2002-9/2007. 9 */ 10 11 #ifndef DRIVERINTERFACE_H 12 #define DRIVERINTERFACE_H 13 14 #include <Accelerant.h> 15 #include "video_overlay.h" 16 #include <Drivers.h> 17 #include <PCI.h> 18 #include <OS.h> 19 #include "AGP.h" 20 21 #define DRIVER_PREFIX "nvidia" 22 #define DEVICE_FORMAT "%04x_%04x_%02x%02x%02x" 23 24 /* 25 Internal driver state (also for sharing info between driver and accelerant) 26 */ 27 #if defined(__cplusplus) 28 extern "C" { 29 #endif 30 31 typedef struct { 32 sem_id sem; 33 int32 ben; 34 } benaphore; 35 36 #define INIT_BEN(x) x.sem = create_sem(0, "NV "#x" benaphore"); x.ben = 0; 37 #define AQUIRE_BEN(x) if((atomic_add(&(x.ben), 1)) >= 1) acquire_sem(x.sem); 38 #define RELEASE_BEN(x) if((atomic_add(&(x.ben), -1)) > 1) release_sem(x.sem); 39 #define DELETE_BEN(x) delete_sem(x.sem); 40 41 42 #define NV_PRIVATE_DATA_MAGIC 0x0009 /* a private driver rev, of sorts */ 43 44 /* dualhead extensions to flags */ 45 #define DUALHEAD_OFF (0<<6) 46 #define DUALHEAD_CLONE (1<<6) 47 #define DUALHEAD_ON (2<<6) 48 #define DUALHEAD_SWITCH (3<<6) 49 #define DUALHEAD_BITS (3<<6) 50 #define DUALHEAD_CAPABLE (1<<8) 51 #define TV_BITS (3<<9) 52 #define TV_MON (0<<9 53 #define TV_PAL (1<<9) 54 #define TV_NTSC (2<<9) 55 #define TV_CAPABLE (1<<11) 56 #define TV_VIDEO (1<<12) 57 #define TV_PRIMARY (1<<13) 58 59 #define SKD_MOVE_CURSOR 0x00000001 60 #define SKD_PROGRAM_CLUT 0x00000002 61 #define SKD_SET_START_ADDR 0x00000004 62 #define SKD_SET_CURSOR 0x00000008 63 #define SKD_HANDLER_INSTALLED 0x80000000 64 65 enum { 66 NV_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1, 67 NV_GET_PCI, 68 NV_SET_PCI, 69 NV_DEVICE_NAME, 70 NV_RUN_INTERRUPTS, 71 NV_GET_NTH_AGP_INFO, 72 NV_ENABLE_AGP, 73 NV_ISA_OUT, 74 NV_ISA_IN 75 }; 76 77 /* card_type in order of date of NV chip design */ 78 enum { 79 NV04 = 0, 80 NV05, 81 NV05M64, 82 NV06, 83 NV10, 84 NV11, 85 NV11M, 86 NV15, 87 NV17, 88 NV17M, 89 NV18, 90 NV18M, 91 NV20, 92 NV25, 93 NV28, 94 NV30, 95 NV31, 96 NV34, 97 NV35, 98 NV36, 99 NV38, 100 NV40, 101 NV41, 102 NV43, 103 NV44, 104 NV45, 105 G70, 106 G71, 107 G72, 108 G73, 109 G80, 110 G84, 111 G86 112 }; 113 114 /* card_arch in order of date of NV chip design */ 115 enum { 116 NV04A = 0, 117 NV10A, 118 NV20A, 119 NV30A, 120 NV40A, 121 NV50A 122 }; 123 124 /* card info - information gathered from PINS (and other sources) */ 125 enum 126 { // tv_encoder_type in order of capability (more or less) 127 NONE = 0, 128 CH7003, 129 CH7004, 130 CH7005, 131 CH7006, 132 CH7007, 133 CH7008, 134 SAA7102, 135 SAA7103, 136 SAA7104, 137 SAA7105, 138 BT868, 139 BT869, 140 CX25870, 141 CX25871, 142 NVIDIA 143 }; 144 145 /* handles to pre-defined engine commands */ 146 #define NV_ROP5_SOLID 0x00000000 /* 2D */ 147 #define NV_IMAGE_BLACK_RECTANGLE 0x00000001 /* 2D/3D */ 148 #define NV_IMAGE_PATTERN 0x00000002 /* 2D */ 149 #define NV_SCALED_IMAGE_FROM_MEMORY 0x00000003 /* 2D */ 150 #define NV_TCL_PRIMITIVE_3D 0x00000004 /* 3D */ //2007 151 #define NV4_SURFACE 0x00000010 /* 2D */ 152 #define NV10_CONTEXT_SURFACES_2D 0x00000010 /* 2D */ 153 #define NV_IMAGE_BLIT 0x00000011 /* 2D */ 154 #define NV12_IMAGE_BLIT 0x00000011 /* 2D */ 155 /* fixme: 156 * never use NV3_GDI_RECTANGLE_TEXT for DMA acceleration: 157 * There's a hardware fault in the input->output colorspace conversion here. 158 * Besides, in NV40 and up this command nolonger exists. Both 'facts' are confirmed 159 * by testing. 160 */ 161 //#define NV3_GDI_RECTANGLE_TEXT 0x00000012 /* 2D */ 162 #define NV4_GDI_RECTANGLE_TEXT 0x00000012 /* 2D */ 163 #define NV4_CONTEXT_SURFACES_ARGB_ZS 0x00000013 /* 3D */ 164 #define NV10_CONTEXT_SURFACES_ARGB_ZS 0x00000013 /* 3D */ 165 #define NV4_DX5_TEXTURE_TRIANGLE 0x00000014 /* 3D */ 166 #define NV10_DX5_TEXTURE_TRIANGLE 0x00000014 /* 3D */ 167 #define NV4_DX6_MULTI_TEXTURE_TRIANGLE 0x00000015 /* unused (yet?) */ 168 #define NV10_DX6_MULTI_TEXTURE_TRIANGLE 0x00000015 /* unused (yet?) */ 169 #define NV1_RENDER_SOLID_LIN 0x00000016 /* 2D: unused */ 170 171 /* max. number of overlay buffers */ 172 #define MAXBUFFERS 3 173 174 //----------------------------------------------------------------------------------- 175 /* safety byte-offset from end of cardRAM for preventing acceleration engine crashes 176 * caused by the existance of DMA engine command buffers in cardRAM and/or fifo 177 * channel engine command re-assigning on-the-fly */ 178 179 /* pre-NV40 notes: 180 * - we need at least 70kB distance from the end of RAM for fifo-reassigning 'bug' 181 * (confirmed on a TNT1); 182 * - keep extra failsafe room to prevent malfunctioning apps from crashing engine. */ 183 #define PRE_NV40_OFFSET 80 * 1024 184 185 /* NV40 and higher notes: 186 * - we need at least 416kB distance from the DMA command buffer: 187 * If you get too close to the DMA command buffer on NV40 and NV43 at least (both 188 * confirmed), the source DMA instance will mess-up for at least engine command 189 * NV_IMAGE_BLIT and NV12_IMAGE_BLIT; 190 * - we need at least ???kB distance from the end of RAM for fifo-reassigning 'bug' 191 * (fixme: unknown yet because fifo assignment switching isn't used here atm); 192 * - keep extra failsafe room to prevent malfunctioning apps from crashing engine. */ 193 #define NV40_PLUS_OFFSET 512 * 1024 194 195 /* fifo re-assigning bug definition: 196 * if the fifo assignment is changed while at the same time card memory in the 197 * dangerous region is being accessed by some application, the engine will crash. 198 * This bug applies for both PIO and DMA mode acceleration! */ 199 200 /* source-DMA instance bug definition: 201 * if card memory in the dangerous region is being accessed by some application while 202 * a DMA command buffer exists in the same memory (though in a different place), 203 * the engine will crash. */ 204 //----------------------------------------------------------------------------------- 205 206 /* internal used info on overlay buffers */ 207 typedef struct { 208 uint16 slopspace; 209 uint32 size; 210 } int_buf_info; 211 212 typedef struct { // apsed, see comments in nv.settings 213 // for driver 214 char accelerant[B_FILE_NAME_LENGTH]; 215 char primary[B_FILE_NAME_LENGTH]; 216 bool dumprom; 217 // for accelerant 218 uint32 logmask; 219 uint32 memory; 220 uint32 tv_output; 221 bool usebios; 222 bool hardcursor; 223 bool switchhead; 224 bool force_pci; 225 bool unhide_fw; 226 bool pgm_panel; 227 bool dma_acc; 228 bool vga_on_tv; 229 bool force_sync; 230 bool force_ws; 231 uint32 gpu_clk; 232 uint32 ram_clk; 233 } nv_settings; 234 235 /* shared info */ 236 typedef struct { 237 /* a few ID things */ 238 uint16 vendor_id; /* PCI vendor ID, from pci_info */ 239 uint16 device_id; /* PCI device ID, from pci_info */ 240 uint8 revision; /* PCI device revsion, from pci_info */ 241 uint8 bus; /* PCI bus number, from pci_info */ 242 uint8 device; /* PCI device number on bus, from pci_info */ 243 uint8 function; /* PCI function number in device, from pci_info */ 244 245 /* used to return status for INIT_ACCELERANT and CLONE_ACCELERANT */ 246 bool accelerant_in_use; 247 248 /* bug workaround for 4.5.0 */ 249 uint32 use_clone_bugfix; /*for 4.5.0, cloning of physical memory does not work*/ 250 uint32 * clone_bugfix_regs; 251 252 /*memory mappings*/ 253 area_id regs_area; /* Kernel's area_id for the memory mapped registers. 254 It will be cloned into the accelerant's address 255 space. */ 256 257 area_id fb_area; /* Frame buffer's area_id. The addresses are shared with all teams. */ 258 area_id unaligned_dma_area; /* Area assigned for DMA. It will be (partially) mapped to an 259 aligned area using MTRR-WC. */ 260 area_id dma_area; /* Aligned area assigned for DMA. The addresses are shared with all teams. */ 261 262 void *framebuffer; /* As viewed from virtual memory */ 263 void *framebuffer_pci; /* As viewed from the PCI bus (for DMA) */ 264 void *dma_buffer; /* As viewed from virtual memory */ 265 void *dma_buffer_pci; /* As viewed from the PCI bus (for DMA) */ 266 267 /*screenmode list*/ 268 area_id mode_area; /* Contains the list of display modes the driver supports */ 269 uint32 mode_count; /* Number of display modes in the list */ 270 271 /*flags - used by driver*/ 272 uint32 flags; 273 274 /*vblank semaphore*/ 275 sem_id vblank; /* The vertical blank semaphore. Ownership will be 276 transfered to the team opening the device first */ 277 /*cursor information*/ 278 struct { 279 uint16 hot_x; /* Cursor hot spot. The top left corner of the cursor */ 280 uint16 hot_y; /* is 0,0 */ 281 uint16 x; /* The location of the cursor hot spot on the */ 282 uint16 y; /* desktop */ 283 uint16 width; /* Width and height of the cursor shape (always 16!) */ 284 uint16 height; 285 bool is_visible; /* Is the cursor currently displayed? */ 286 bool dh_right; /* Is cursor on right side of stretched screen? */ 287 } cursor; 288 289 /*colour lookup table*/ 290 uint8 color_data[3 * 256]; /* Colour lookup table - as used by DAC */ 291 292 /*more display mode stuff*/ 293 display_mode dm; /* current display mode configuration: head1 */ 294 uint32 dpms_flags; /* current DPMS mode */ 295 bool acc_mode; /* signals (non)accelerated mode */ 296 bool interlaced_tv_mode;/* signals interlaced CRTC TV output mode */ 297 bool crtc_switch_mode; /* signals dualhead switch mode if panels are used */ 298 299 /*frame buffer config - for BDirectScreen*/ 300 frame_buffer_config fbc; /* bytes_per_row and start of frame buffer: head1 */ 301 accelerant_device_info adi; /* as returned by hook GET_ACCELERANT_DEVICE_INFO */ 302 303 /*acceleration engine*/ 304 struct { 305 uint32 count; /* last dwgsync slot used */ 306 uint32 last_idle; /* last dwgsync slot we *know* the engine was idle after */ 307 benaphore lock; /* for serializing access to the acc engine */ 308 struct { 309 uint32 handle[0x08]; /* FIFO channel's cmd handle for the owning cmd */ 310 uint32 ch_ptr[0x20]; /* cmd handle's ptr to it's assigned FIFO ch (if any) */ 311 } fifo; 312 struct { 313 uint32 put; /* last 32-bit-word adress given to engine to exec. to */ 314 uint32 current; /* first free 32-bit-word adress in buffer */ 315 uint32 free; /* nr. of useable free 32-bit words remaining in buffer */ 316 uint32 max; /* command buffer's useable size in 32-bit words */ 317 } dma; 318 bool agp_mode; /* card is running in AGP mode */ 319 struct { 320 uint32 clones; /* clone 'number' (mask, slot) (one bit per clone) */ 321 uint32 reload; /* reload state and surfaces (one bit per clone) */ 322 uint32 newmode; /* re-allocate all buffers (one bit per clone) */ 323 //fixme: memory stuff needs to be expanded (shared texture allocation?) 324 uint32 mem_low; /* ptr to first free mem adress: cardmem local offset */ 325 uint32 mem_high; /* ptr to last free mem adress: cardmem local offset */ 326 bool mode_changing; /* a mode-change is in progress (set/clear by 2D drv) */ 327 } threeD; 328 } engine; 329 330 struct 331 { 332 /* specialised registers for card initialisation read from NV BIOS (pins) */ 333 334 /* general card information */ 335 uint32 card_type; /* see card_type enum above */ 336 uint32 card_arch; /* see card_arch enum above */ 337 bool laptop; /* mobile chipset or not ('internal' flatpanel!) */ 338 bool slaved_tmds1; /* external TMDS encoder active on CRTC1 */ 339 bool slaved_tmds2; /* external TMDS encoder active on CRTC2 */ 340 bool master_tmds1; /* on die TMDS encoder active on CRTC1 */ 341 bool master_tmds2; /* on die TMDS encoder active on CRTC2 */ 342 bool tmds1_active; /* found panel on CRTC1 that is active */ 343 bool tmds2_active; /* found panel on CRTC2 that is active */ 344 display_timing p1_timing; /* 'modeline' fetched for panel 1 */ 345 display_timing p2_timing; /* 'modeline' fetched for panel 2 */ 346 float panel1_aspect; /* panel's aspect ratio */ 347 float panel2_aspect; /* panel's aspect ratio */ 348 bool crtc2_prim; /* using CRTC2 as primary CRTC */ 349 bool i2c_bus0; /* we have a wired I2C bus 0 on board */ 350 bool i2c_bus1; /* we have a wired I2C bus 1 on board */ 351 bool i2c_bus2; /* we have a wired I2C bus 2 on board */ 352 bool i2c_bus3; /* we have a wired I2C bus 3 on board */ 353 struct 354 { 355 uint32 type; /* see tvchip_type enum above */ 356 uint8 version; /* chip silicon version */ 357 uint8 bus; /* I2C bus on which TVout chip resides */ 358 uint8 adress; /* I2C adress on which TVout chip resides */ 359 } tv_encoder; 360 uint8 monitors; /* output devices connection matrix */ 361 bool int_assigned; /* card has a useable INT assigned to it */ 362 status_t pins_status; /* B_OK if read correctly, B_ERROR if faked */ 363 364 /* PINS */ 365 float f_ref; /* PLL reference-oscillator frequency (Mhz) */ 366 bool ext_pll; /* the extended PLL contains more dividers */ 367 uint32 max_system_vco; /* graphics engine PLL VCO limits (Mhz) */ 368 uint32 min_system_vco; 369 uint32 max_pixel_vco; /* dac1 PLL VCO limits (Mhz) */ 370 uint32 min_pixel_vco; 371 uint32 max_video_vco; /* dac2 PLL VCO limits (Mhz) */ 372 uint32 min_video_vco; 373 uint32 std_engine_clock; /* graphics engine clock speed needed (Mhz) */ 374 uint32 std_memory_clock; /* card memory clock speed needed (Mhz) */ 375 uint32 max_dac1_clock; /* dac1 limits (Mhz) */ 376 uint32 max_dac1_clock_8; /* dac1 limits correlated to RAMspeed limits (Mhz) */ 377 uint32 max_dac1_clock_16; 378 uint32 max_dac1_clock_24; 379 uint32 max_dac1_clock_32; 380 uint32 max_dac1_clock_32dh; 381 uint32 max_dac2_clock; /* dac2 limits (Mhz) */ 382 uint32 max_dac2_clock_8; /* dac2, maven limits correlated to RAMspeed limits (Mhz) */ 383 uint32 max_dac2_clock_16; 384 uint32 max_dac2_clock_24; 385 uint32 max_dac2_clock_32; 386 uint32 max_dac2_clock_32dh; 387 bool secondary_head; /* presence of functions */ 388 bool tvout; 389 bool primary_dvi; 390 bool secondary_dvi; 391 uint32 memory_size; /* memory (in bytes) */ 392 } ps; 393 394 /* mirror of the ROM (copied in driver, because may not be mapped permanently) */ 395 uint8 rom_mirror[65536]; 396 397 /* some configuration settings from ~/config/settings/kernel/drivers/nv.settings if exists */ 398 nv_settings settings; 399 400 struct 401 { 402 overlay_buffer myBuffer[MAXBUFFERS];/* scaler input buffers */ 403 int_buf_info myBufInfo[MAXBUFFERS]; /* extra info on scaler input buffers */ 404 overlay_token myToken; /* scaler is free/in use */ 405 benaphore lock; /* for creating buffers and aquiring overlay unit routines */ 406 bool crtc; /* location of overlay unit */ 407 /* variables needed for virtualscreens (move_overlay()): */ 408 bool active; /* true is overlay currently in use */ 409 overlay_window ow; /* current position of overlay output window */ 410 overlay_buffer ob; /* current inputbuffer in use */ 411 overlay_view my_ov; /* current corrected view in inputbuffer */ 412 uint32 h_ifactor; /* current 'unclipped' horizontal inverse scaling factor */ 413 uint32 v_ifactor; /* current 'unclipped' vertical inverse scaling factor */ 414 } overlay; 415 416 } shared_info; 417 418 /* Read or write a value in PCI configuration space */ 419 typedef struct { 420 uint32 magic; /* magic number to make sure the caller groks us */ 421 uint32 offset; /* Offset to read/write */ 422 uint32 size; /* Number of bytes to transfer */ 423 uint32 value; /* The value read or written */ 424 } nv_get_set_pci; 425 426 /* Enable or Disable CRTC (1,2) interrupts */ 427 typedef struct { 428 uint32 magic; /* magic number to make sure the caller groks us */ 429 bool crtc; /* adressed CRTC */ 430 bool do_it; /* state to set */ 431 } nv_set_vblank_int; 432 433 /* Retrieve the area_id of the kernel/accelerant shared info */ 434 typedef struct { 435 uint32 magic; /* magic number to make sure the caller groks us */ 436 area_id shared_info_area; /* area_id containing the shared information */ 437 } nv_get_private_data; 438 439 /* Retrieve the device name. Usefull for when we have a file handle, but want 440 to know the device name (like when we are cloning the accelerant) */ 441 typedef struct { 442 uint32 magic; /* magic number to make sure the caller groks us */ 443 char *name; /* The name of the device, less the /dev root */ 444 } nv_device_name; 445 446 /* Retrieve an AGP device interface if there. Usefull to find the AGP speed scheme 447 used (pre 3.x or 3.x) */ 448 typedef struct { 449 uint32 magic; /* magic number to make sure the caller groks us */ 450 bool agp_bus;/* indicates if we have access to the AGP busmanager */ 451 uint8 index; /* device index in list of devices found */ 452 bool exist; /* we got AGP device info */ 453 agp_info agpi; /* AGP interface info of a device */ 454 } nv_nth_agp_info; 455 456 /* Execute an AGP command */ 457 typedef struct { 458 uint32 magic; /* magic number to make sure the caller groks us */ 459 bool agp_bus;/* indicates if we have access to the AGP busmanager */ 460 uint32 cmd; /* actual command to execute */ 461 } nv_cmd_agp; 462 463 /* Read or write a value in ISA I/O space */ 464 typedef struct { 465 uint32 magic; /* magic number to make sure the caller groks us */ 466 uint16 adress; /* Offset to read/write */ 467 uint8 size; /* Number of bytes to transfer */ 468 uint16 data; /* The value read or written */ 469 } nv_in_out_isa; 470 471 enum { 472 473 _WAIT_FOR_VBLANK = (1 << 0) 474 }; 475 476 #if defined(__cplusplus) 477 } 478 #endif 479 480 481 #endif 482