1 /* NM registers definitions and macros for access to */ 2 3 //old: 4 /* PCI_config_space */ 5 #define NMCFG_DEVID 0x00 6 #define NMCFG_DEVCTRL 0x04 7 #define NMCFG_CLASS 0x08 8 #define NMCFG_HEADER 0x0c 9 #define NMCFG_NMBASE2 0x10 10 #define NMCFG_NMBASE1 0x14 11 #define NMCFG_NMBASE3 0x18 // >= MYST 12 #define NMCFG_SUBSYSIDR 0x2c // >= MYST 13 #define NMCFG_ROMBASE 0x30 14 #define NMCFG_CAP_PTR 0x34 // >= MIL2 15 #define NMCFG_INTCTRL 0x3c 16 #define NMCFG_OPTION 0x40 17 #define NMCFG_NM_INDEX 0x44 18 #define NMCFG_NM_DATA 0x48 19 #define NMCFG_SUBSYSIDW 0x4c // >= MYST 20 #define NMCFG_OPTION2 0x50 // >= G100 21 #define NMCFG_OPTION3 0x54 // >= G400 22 #define NMCFG_OPTION4 0x58 // >= G450 23 #define NMCFG_PM_IDENT 0xdc // >= G100 24 #define NMCFG_PM_CSR 0xe0 // >= G100 25 #define NMCFG_AGP_IDENT 0xf0 // >= MIL2 26 #define NMCFG_AGP_STS 0xf4 // >= MIL2 27 #define NMCFG_AGP_CMD 0xf8 // >= MIL2 28 //end old. 29 30 /* neomagic ISA direct registers */ 31 /* VGA standard registers: */ 32 #define NMISA8_ATTRINDW 0x03c0 33 #define NMISA8_ATTRINDR 0x03c1 34 #define NMISA8_ATTRDATW 0x03c0 35 #define NMISA8_ATTRDATR 0x03c1 36 #define NMISA8_SEQIND 0x03c4 37 #define NMISA8_SEQDAT 0x03c5 38 #define NMISA16_SEQIND 0x03c4 39 #define NMISA8_CRTCIND 0x03d4 40 #define NMISA8_CRTCDAT 0x03d5 41 #define NMISA16_CRTCIND 0x03d4 42 #define NMISA8_GRPHIND 0x03ce 43 #define NMISA8_GRPHDAT 0x03cf 44 #define NMISA16_GRPHIND 0x03ce 45 46 /* neomagic PCI direct registers */ 47 #define NM2PCI8_SEQIND 0x03c4 48 #define NM2PCI8_SEQDAT 0x03c5 49 #define NM2PCI16_SEQIND 0x03c4 50 #define NM2PCI8_GRPHIND 0x03ce 51 #define NM2PCI8_GRPHDAT 0x03cf 52 #define NM2PCI16_GRPHIND 0x03ce 53 54 /* neomagic ISA GENERAL direct registers */ 55 /* VGA standard registers: */ 56 #define NMISA8_MISCW 0x03c2 57 #define NMISA8_MISCR 0x03cc 58 #define NMISA8_INSTAT1 0x03da 59 60 /* neomagic ISA (DAC) COLOR direct registers (VGA palette RAM) */ 61 /* VGA standard registers: */ 62 #define NMISA8_PALMASK 0x03c6 63 #define NMISA8_PALINDR 0x03c7 64 #define NMISA8_PALINDW 0x03c8 65 #define NMISA8_PALDATA 0x03c9 66 67 /* neomagic ISA CRTC indexed registers */ 68 /* VGA standard registers: */ 69 #define NMCRTCX_HTOTAL 0x00 70 #define NMCRTCX_HDISPE 0x01 71 #define NMCRTCX_HBLANKS 0x02 72 #define NMCRTCX_HBLANKE 0x03 73 #define NMCRTCX_HSYNCS 0x04 74 #define NMCRTCX_HSYNCE 0x05 75 #define NMCRTCX_VTOTAL 0x06 76 #define NMCRTCX_OVERFLOW 0x07 77 #define NMCRTCX_PRROWSCN 0x08 78 #define NMCRTCX_MAXSCLIN 0x09 79 #define NMCRTCX_VGACURCTRL 0x0a 80 #define NMCRTCX_FBSTADDH 0x0c 81 #define NMCRTCX_FBSTADDL 0x0d 82 #define NMCRTCX_VSYNCS 0x10 83 #define NMCRTCX_VSYNCE 0x11 84 #define NMCRTCX_VDISPE 0x12 85 #define NMCRTCX_PITCHL 0x13 86 #define NMCRTCX_VBLANKS 0x15 87 #define NMCRTCX_VBLANKE 0x16 88 #define NMCRTCX_MODECTL 0x17 89 #define NMCRTCX_LINECOMP 0x18 90 /* NeoMagic specific registers: */ 91 #define NMCRTCX_VEXT 0x70 /* >= NM2200 */ 92 93 /* neomagic ISA SEQUENCER indexed registers */ 94 /* VGA standard registers: */ 95 #define NMSEQX_RESET 0x00 96 #define NMSEQX_CLKMODE 0x01 97 #define NMSEQX_MEMMODE 0x04 98 /* NeoMagic BES registers: (> NM2070) (accessible via mapped I/O: >= NM2097) */ 99 #define NMSEQX_BESCTRL2 0x08 100 #define NMSEQX_0x09 0x09 //?? 101 #define NMSEQX_0x0a 0x0a //?? 102 #define NMSEQX_BUF2ORGL 0x0c 103 #define NMSEQX_BUF2ORGM 0x0d 104 #define NMSEQX_BUF2ORGH 0x0e 105 #define NMSEQX_VSCOORD1L 0x14 /* >= NM2200(?), so clipping done via buffer startadress instead */ 106 #define NMSEQX_VSCOORD2L 0x15 /* >= NM2200(?), so clipping done via buffer startadress instead */ 107 #define NMSEQX_VSCOORD21H 0x16 /* >= NM2200(?), so clipping done via buffer startadress instead */ 108 #define NMSEQX_HSCOORD1L 0x17 /* >= NM2200(?), so clipping done via buffer startadress instead */ 109 #define NMSEQX_HSCOORD2L 0x18 /* >= NM2200(?), so clipping done via buffer startadress instead */ 110 #define NMSEQX_HSCOORD21H 0x19 /* >= NM2200(?), so clipping done via buffer startadress instead */ 111 #define NMSEQX_BUF2PITCHL 0x1a 112 #define NMSEQX_BUF2PITCHH 0x1b 113 #define NMSEQX_0x1c 0x1c //?? 114 #define NMSEQX_0x1d 0x1d //?? 115 #define NMSEQX_0x1e 0x1e //?? 116 #define NMSEQX_0x1f 0x1f //?? 117 118 /* neomagic ISA ATTRIBUTE indexed registers */ 119 /* VGA standard registers: */ 120 #define NMATBX_MODECTL 0x10 121 #define NMATBX_OSCANCOLOR 0x11 122 #define NMATBX_COLPLANE_EN 0x12 123 #define NMATBX_HORPIXPAN 0x13 124 #define NMATBX_COLSEL 0x14 125 126 /* neomagic ISA GRAPHICS indexed registers */ 127 /* VGA standard registers: */ 128 #define NMGRPHX_ENSETRESET 0x01 129 #define NMGRPHX_DATAROTATE 0x03 130 #define NMGRPHX_READMAPSEL 0x04 131 #define NMGRPHX_MODE 0x05 132 #define NMGRPHX_MISC 0x06 133 #define NMGRPHX_BITMASK 0x08 134 /* NeoMagic specific registers: */ 135 #define NMGRPHX_GRPHXLOCK 0x09 136 #define NMGRPHX_GENLOCK 0x0a 137 #define NMGRPHX_FBSTADDE 0x0e 138 #define NMGRPHX_CRTC_PITCHE 0x0f 139 #define NMGRPHX_IFACECTRL 0x11 140 #define NMGRPHX_PANELCTRL1 0x20 141 #define NMGRPHX_PANELTYPE 0x21 142 #define NMGRPHX_PANELCTRL2 0x25 143 #define NMGRPHX_PANELVCENT1 0x28 144 #define NMGRPHX_PANELVCENT2 0x29 145 #define NMGRPHX_PANELVCENT3 0x2a 146 #define NMGRPHX_PANELCTRL3 0x30 /* > NM2070 */ 147 #define NMGRPHX_PANELVCENT4 0x32 /* > NM2070 */ 148 #define NMGRPHX_PANELHCENT1 0x33 /* > NM2070 */ 149 #define NMGRPHX_PANELHCENT2 0x34 /* > NM2070 */ 150 #define NMGRPHX_PANELHCENT3 0x35 /* > NM2070 */ 151 #define NMGRPHX_PANELHCENT4 0x36 /* >= NM2160 */ 152 #define NMGRPHX_PANELVCENT5 0x37 /* >= NM2200 */ 153 #define NMGRPHX_PANELHCENT5 0x38 /* >= NM2200 */ 154 #define NMGRPHX_CURCTRL 0x82 155 #define NMGRPHX_COLDEPTH 0x90 156 /* (NeoMagic pixelPLL set C registers) */ 157 #define NMGRPHX_PLLC_NL 0x9b 158 #define NMGRPHX_PLLC_NH 0x8f /* >= NM2200 */ 159 #define NMGRPHX_PLLC_M 0x9f 160 /* NeoMagic BES registers: (> NM2070) (accessible via mapped I/O: >= NM2097) */ 161 #define NMGRPHX_BESCTRL1 0xb0 162 #define NMGRPHX_HDCOORD21H 0xb1 163 #define NMGRPHX_HDCOORD1L 0xb2 164 #define NMGRPHX_HDCOORD2L 0xb3 165 #define NMGRPHX_VDCOORD21H 0xb4 166 #define NMGRPHX_VDCOORD1L 0xb5 167 #define NMGRPHX_VDCOORD2L 0xb6 168 #define NMGRPHX_BUF1ORGH 0xb7 169 #define NMGRPHX_BUF1ORGM 0xb8 170 #define NMGRPHX_BUF1ORGL 0xb9 171 #define NMGRPHX_BUF1PITCHH 0xba 172 #define NMGRPHX_BUF1PITCHL 0xbb 173 #define NMGRPHX_0xbc 0xbc //?? 174 #define NMGRPHX_0xbd 0xbd //?? 175 #define NMGRPHX_0xbe 0xbe //?? 176 #define NMGRPHX_0xbf 0xbf //?? 177 #define NMGRPHX_XSCALEH 0xc0 178 #define NMGRPHX_XSCALEL 0xc1 179 #define NMGRPHX_YSCALEH 0xc2 180 #define NMGRPHX_YSCALEL 0xc3 181 #define NMGRPHX_BRIGHTNESS 0xc4 182 #define NMGRPHX_COLKEY_R 0xc5 183 #define NMGRPHX_COLKEY_G 0xc6 184 #define NMGRPHX_COLKEY_B 0xc7 185 186 /* NeoMagic specific PCI cursor registers < NM2200 */ 187 #define NMCR1_CURCTRL 0x0100 188 #define NMCR1_CURX 0x0104 189 #define NMCR1_CURY 0x0108 190 #define NMCR1_CURBGCOLOR 0x010c 191 #define NMCR1_CURFGCOLOR 0x0110 192 #define NMCR1_CURADDRESS 0x0114 193 /* NeoMagic specific PCI cursor registers >= NM2200 */ 194 #define NMCR1_22CURCTRL 0x1000 195 #define NMCR1_22CURX 0x1004 196 #define NMCR1_22CURY 0x1008 197 #define NMCR1_22CURBGCOLOR 0x100c 198 #define NMCR1_22CURFGCOLOR 0x1010 199 #define NMCR1_22CURADDRESS 0x1014 200 201 //old: 202 /* NM ACCeleration registers */ 203 #define NMACC_DWGCTL 0x1C00 204 #define NMACC_MACCESS 0x1C04 205 #define NMACC_MCTLWTST 0x1C08 206 #define NMACC_ZORG 0x1C0C 207 #define NMACC_PLNWT 0x1C1C 208 #define NMACC_BCOL 0x1C20 209 #define NMACC_FCOL 0x1C24 210 #define NMACC_XYSTRT 0x1C40 211 #define NMACC_XYEND 0x1C44 212 #define NMACC_SGN 0x1C58 213 #define NMACC_LEN 0x1C5C 214 #define NMACC_AR0 0x1C60 215 #define NMACC_AR3 0x1C6C 216 #define NMACC_AR5 0x1C74 217 #define NMACC_CXBNDRY 0x1C80 218 #define NMACC_FXBNDRY 0x1C84 219 #define NMACC_YDSTLEN 0x1C88 220 #define NMACC_PITCH 0x1C8C 221 #define NMACC_YDST 0x1C90 222 #define NMACC_YDSTORG 0x1C94 223 #define NMACC_YTOP 0x1C98 224 #define NMACC_YBOT 0x1C9C 225 #define NMACC_CXLEFT 0x1CA0 226 #define NMACC_CXRIGHT 0x1CA4 227 #define NMACC_FXLEFT 0x1CA8 228 #define NMACC_FXRIGHT 0x1CAC 229 #define NMACC_STATUS 0x1E14 230 #define NMACC_ICLEAR 0x1E18 /* required for interrupt stuff */ 231 #define NMACC_IEN 0x1E1C /* required for interrupt stuff */ 232 #define NMACC_RST 0x1E40 233 #define NMACC_MEMRDBK 0x1E44 234 #define NMACC_OPMODE 0x1E54 235 #define NMACC_PRIMADDRESS 0x1E58 236 #define NMACC_PRIMEND 0x1E5C 237 #define NMACC_TEXORG 0x2C24 // >= G100 238 #define NMACC_DWGSYNC 0x2C4C // >= G200 239 #define NMACC_TEXORG1 0x2CA4 // >= G200 240 #define NMACC_TEXORG2 0x2CA8 // >= G200 241 #define NMACC_TEXORG3 0x2CAC // >= G200 242 #define NMACC_TEXORG4 0x2CB0 // >= G200 243 #define NMACC_SRCORG 0x2CB4 // >= G200 244 #define NMACC_DSTORG 0x2CB8 // >= G200 245 //end old. 246 247 /* Macros for convenient accesses to the NM chips */ 248 249 /* primary PCI register area */ 250 #define NM_REG8(r_) ((vuint8 *)regs)[(r_)] 251 #define NM_REG16(r_) ((vuint16 *)regs)[(r_) >> 1] 252 #define NM_REG32(r_) ((vuint32 *)regs)[(r_) >> 2] 253 /* secondary PCI register area */ 254 #define NM_2REG8(r_) ((vuint8 *)regs2)[(r_)] 255 #define NM_2REG16(r_) ((vuint16 *)regs2)[(r_) >> 1] 256 #define NM_2REG32(r_) ((vuint32 *)regs2)[(r_) >> 2] 257 258 /* read and write to PCI config space */ 259 #define CFGR(A) (nm_pci_access.offset=NMCFG_##A, ioctl(fd,NM_GET_PCI, &nm_pci_access,sizeof(nm_pci_access)), nm_pci_access.value) 260 #define CFGW(A,B) (nm_pci_access.offset=NMCFG_##A, nm_pci_access.value = B, ioctl(fd,NM_SET_PCI,&nm_pci_access,sizeof(nm_pci_access))) 261 262 //old: 263 /* read and write from the powergraphics registers */ 264 #define ACCR(A) (NM_REG32(NMACC_##A)) 265 #define ACCW(A,B) (NM_REG32(NMACC_##A)=B) 266 #define ACCGO(A,B) (NM_REG32(NMACC_##A + 0x0100)=B) 267 //end old. 268 269 /* read and write from first CRTC (mapped) */ 270 #define CR1R(A) (NM_REG32(NMCR1_##A)) 271 #define CR1W(A,B) (NM_REG32(NMCR1_##A) = (B)) 272 273 /* read and write from ISA I/O space */ 274 #define ISAWB(A,B)(nm_isa_access.adress=NMISA8_##A, nm_isa_access.data = (uint8)B, nm_isa_access.size = 1, ioctl(fd,NM_ISA_OUT, &nm_isa_access,sizeof(nm_isa_access))) 275 #define ISAWW(A,B)(nm_isa_access.adress=NMISA16_##A, nm_isa_access.data = B, nm_isa_access.size = 2, ioctl(fd,NM_ISA_OUT, &nm_isa_access,sizeof(nm_isa_access))) 276 #define ISARB(A) (nm_isa_access.adress=NMISA8_##A, ioctl(fd,NM_ISA_IN, &nm_isa_access,sizeof(nm_isa_access)), (uint8)nm_isa_access.data) 277 #define ISARW(A) (nm_isa_access.adress=NMISA16_##A, ioctl(fd,NM_ISA_IN, &nm_isa_access,sizeof(nm_isa_access)), nm_isa_access.data) 278 279 /* read and write from ISA CRTC indexed registers */ 280 #define ISACRTCW(A,B)(ISAWW(CRTCIND, ((NMCRTCX_##A) | ((B) << 8)))) 281 #define ISACRTCR(A) (ISAWB(CRTCIND, (NMCRTCX_##A)), ISARB(CRTCDAT)) 282 283 /* read and write from ISA GRAPHICS indexed registers */ 284 #define ISAGRPHW(A,B)(ISAWW(GRPHIND, ((NMGRPHX_##A) | ((B) << 8)))) 285 #define ISAGRPHR(A) (ISAWB(GRPHIND, (NMGRPHX_##A)), ISARB(GRPHDAT)) 286 287 /* read and write from PCI GRAPHICS indexed registers (>= NM2097) */ 288 #define PCIGRPHW(A,B)(NM_2REG16(NM2PCI16_GRPHIND) = ((NMGRPHX_##A) | ((B) << 8))) 289 #define PCIGRPHR(A) (NM_2REG8(NM2PCI8_GRPHIND) = (NMGRPHX_##A), NM_2REG8(NM2PCI8_GRPHDAT)) 290 291 /* read and write from ISA SEQUENCER indexed registers */ 292 #define ISASEQW(A,B)(ISAWW(SEQIND, ((NMSEQX_##A) | ((B) << 8)))) 293 #define ISASEQR(A) (ISAWB(SEQIND, (NMSEQX_##A)), ISARB(SEQDAT)) 294 295 /* read and write from PCI SEQUENCER indexed registers (>= NM2097) */ 296 #define PCISEQW(A,B)(NM_2REG16(NM2PCI16_SEQIND) = ((NMSEQX_##A) | ((B) << 8))) 297 #define PCISEQR(A) (NM_2REG8(NM2PCI8_SEQIND) = (NMSEQX_##A), NM_2REG8(NM2PCI8_SEQDAT)) 298 299 /* read and write from ISA ATTRIBUTE indexed registers */ 300 #define ISAATBW(A,B)((void)ISARB(INSTAT1), ISAWB(ATTRINDW, ((NMATBX_##A) | 0x20)), ISAWB(ATTRDATW, (B))) 301 #define ISAATBR(A) ((void)ISARB(INSTAT1), ISAWB(ATTRINDW, ((NMATBX_##A) | 0x20)), ISARB(ATTRDATR)) 302