1 /* NM registers definitions and macros for access to */ 2 3 //old: 4 /* PCI_config_space */ 5 #define NMCFG_DEVID 0x00 6 #define NMCFG_DEVCTRL 0x04 7 #define NMCFG_CLASS 0x08 8 #define NMCFG_HEADER 0x0c 9 #define NMCFG_NMBASE2 0x10 10 #define NMCFG_NMBASE1 0x14 11 #define NMCFG_NMBASE3 0x18 // >= MYST 12 #define NMCFG_SUBSYSIDR 0x2c // >= MYST 13 #define NMCFG_ROMBASE 0x30 14 #define NMCFG_CAP_PTR 0x34 // >= MIL2 15 #define NMCFG_INTCTRL 0x3c 16 #define NMCFG_OPTION 0x40 17 #define NMCFG_NM_INDEX 0x44 18 #define NMCFG_NM_DATA 0x48 19 #define NMCFG_SUBSYSIDW 0x4c // >= MYST 20 #define NMCFG_OPTION2 0x50 // >= G100 21 #define NMCFG_OPTION3 0x54 // >= G400 22 #define NMCFG_OPTION4 0x58 // >= G450 23 #define NMCFG_PM_IDENT 0xdc // >= G100 24 #define NMCFG_PM_CSR 0xe0 // >= G100 25 #define NMCFG_AGP_IDENT 0xf0 // >= MIL2 26 #define NMCFG_AGP_STS 0xf4 // >= MIL2 27 #define NMCFG_AGP_CMD 0xf8 // >= MIL2 28 //end old. 29 30 /* neomagic ISA direct registers */ 31 /* VGA standard registers: */ 32 #define NMISA8_ATTRINDW 0x03c0 33 #define NMISA8_ATTRINDR 0x03c1 34 #define NMISA8_ATTRDATW 0x03c0 35 #define NMISA8_ATTRDATR 0x03c1 36 #define NMISA8_SEQIND 0x03c4 37 #define NMISA8_SEQDAT 0x03c5 38 #define NMISA16_SEQIND 0x03c4 39 #define NMISA8_CRTCIND 0x03d4 40 #define NMISA8_CRTCDAT 0x03d5 41 #define NMISA16_CRTCIND 0x03d4 42 #define NMISA8_GRPHIND 0x03ce 43 #define NMISA8_GRPHDAT 0x03cf 44 #define NMISA16_GRPHIND 0x03ce 45 46 /* neomagic PCI direct registers */ 47 #define NM2PCI8_SEQIND 0x03c4 48 #define NM2PCI8_SEQDAT 0x03c5 49 #define NM2PCI16_SEQIND 0x03c4 50 #define NM2PCI8_GRPHIND 0x03ce 51 #define NM2PCI8_GRPHDAT 0x03cf 52 #define NM2PCI16_GRPHIND 0x03ce 53 54 /* neomagic ISA GENERAL direct registers */ 55 /* VGA standard registers: */ 56 #define NMISA8_MISCW 0x03c2 57 #define NMISA8_MISCR 0x03cc 58 #define NMISA8_INSTAT1 0x03da 59 60 /* neomagic ISA (DAC) COLOR direct registers (VGA palette RAM) */ 61 /* VGA standard registers: */ 62 #define NMISA8_PALMASK 0x03c6 63 #define NMISA8_PALINDR 0x03c7 64 #define NMISA8_PALINDW 0x03c8 65 #define NMISA8_PALDATA 0x03c9 66 67 /* neomagic ISA CRTC indexed registers */ 68 /* VGA standard registers: */ 69 #define NMCRTCX_HTOTAL 0x00 70 #define NMCRTCX_HDISPE 0x01 71 #define NMCRTCX_HBLANKS 0x02 72 #define NMCRTCX_HBLANKE 0x03 73 #define NMCRTCX_HSYNCS 0x04 74 #define NMCRTCX_HSYNCE 0x05 75 #define NMCRTCX_VTOTAL 0x06 76 #define NMCRTCX_OVERFLOW 0x07 77 #define NMCRTCX_PRROWSCN 0x08 78 #define NMCRTCX_MAXSCLIN 0x09 79 #define NMCRTCX_VGACURCTRL 0x0a 80 #define NMCRTCX_FBSTADDH 0x0c 81 #define NMCRTCX_FBSTADDL 0x0d 82 #define NMCRTCX_VSYNCS 0x10 83 #define NMCRTCX_VSYNCE 0x11 84 #define NMCRTCX_VDISPE 0x12 85 #define NMCRTCX_PITCHL 0x13 86 #define NMCRTCX_VBLANKS 0x15 87 #define NMCRTCX_VBLANKE 0x16 88 #define NMCRTCX_MODECTL 0x17 89 #define NMCRTCX_LINECOMP 0x18 90 /* NeoMagic specific registers: */ 91 #define NMCRTCX_VEXT 0x70 /* >= NM2200 */ 92 93 /* neomagic ISA SEQUENCER indexed registers */ 94 /* VGA standard registers: */ 95 #define NMSEQX_RESET 0x00 96 #define NMSEQX_CLKMODE 0x01 97 #define NMSEQX_MAPMASK 0x02 98 #define NMSEQX_MEMMODE 0x04 99 /* NeoMagic BES registers: (> NM2070) (accessible via mapped I/O: >= NM2097) */ 100 #define NMSEQX_BESCTRL2 0x08 101 #define NMSEQX_0x09 0x09 //?? 102 #define NMSEQX_0x0a 0x0a //?? 103 #define NMSEQX_BUF2ORGL 0x0c 104 #define NMSEQX_BUF2ORGM 0x0d 105 #define NMSEQX_BUF2ORGH 0x0e 106 #define NMSEQX_VSCOORD1L 0x14 /* >= NM2200(?), so clipping done via buffer startadress instead */ 107 #define NMSEQX_VSCOORD2L 0x15 /* >= NM2200(?), so clipping done via buffer startadress instead */ 108 #define NMSEQX_VSCOORD21H 0x16 /* >= NM2200(?), so clipping done via buffer startadress instead */ 109 #define NMSEQX_HSCOORD1L 0x17 /* >= NM2200(?), so clipping done via buffer startadress instead */ 110 #define NMSEQX_HSCOORD2L 0x18 /* >= NM2200(?), so clipping done via buffer startadress instead */ 111 #define NMSEQX_HSCOORD21H 0x19 /* >= NM2200(?), so clipping done via buffer startadress instead */ 112 #define NMSEQX_BUF2PITCHL 0x1a 113 #define NMSEQX_BUF2PITCHH 0x1b 114 #define NMSEQX_0x1c 0x1c //?? 115 #define NMSEQX_0x1d 0x1d //?? 116 #define NMSEQX_0x1e 0x1e //?? 117 #define NMSEQX_0x1f 0x1f //?? 118 119 /* neomagic ISA ATTRIBUTE indexed registers */ 120 /* VGA standard registers: */ 121 #define NMATBX_MODECTL 0x10 122 #define NMATBX_OSCANCOLOR 0x11 123 #define NMATBX_COLPLANE_EN 0x12 124 #define NMATBX_HORPIXPAN 0x13 125 #define NMATBX_COLSEL 0x14 126 #define NMATBX_0x16 0x16 127 128 /* neomagic ISA GRAPHICS indexed registers */ 129 /* VGA standard registers: */ 130 #define NMGRPHX_ENSETRESET 0x01 131 #define NMGRPHX_DATAROTATE 0x03 132 #define NMGRPHX_READMAPSEL 0x04 133 #define NMGRPHX_MODE 0x05 134 #define NMGRPHX_MISC 0x06 135 #define NMGRPHX_BITMASK 0x08 136 /* NeoMagic specific registers: */ 137 #define NMGRPHX_GRPHXLOCK 0x09 138 #define NMGRPHX_GENLOCK 0x0a 139 #define NMGRPHX_FBSTADDE 0x0e 140 #define NMGRPHX_CRTC_PITCHE 0x0f /* > NM2070 */ 141 #define NMGRPHX_IFACECTRL1 0x10 142 #define NMGRPHX_IFACECTRL2 0x11 143 #define NMGRPHX_0x15 0x15 144 #define NMGRPHX_PANELCTRL1 0x20 145 #define NMGRPHX_PANELTYPE 0x21 146 #define NMGRPHX_PANELCTRL2 0x25 147 #define NMGRPHX_PANELVCENT1 0x28 148 #define NMGRPHX_PANELVCENT2 0x29 149 #define NMGRPHX_PANELVCENT3 0x2a 150 #define NMGRPHX_PANELCTRL3 0x30 /* > NM2070 */ 151 #define NMGRPHX_PANELVCENT4 0x32 /* > NM2070 */ 152 #define NMGRPHX_PANELHCENT1 0x33 /* > NM2070 */ 153 #define NMGRPHX_PANELHCENT2 0x34 /* > NM2070 */ 154 #define NMGRPHX_PANELHCENT3 0x35 /* > NM2070 */ 155 #define NMGRPHX_PANELHCENT4 0x36 /* >= NM2160 */ 156 #define NMGRPHX_PANELVCENT5 0x37 /* >= NM2200 */ 157 #define NMGRPHX_PANELHCENT5 0x38 /* >= NM2200 */ 158 #define NMGRPHX_CURCTRL 0x82 159 #define NMGRPHX_COLDEPTH 0x90 160 /* mem or core PLL register??? */ 161 #define NMGRPHX_SPEED 0x93 162 /* (NeoMagic pixelPLL set C registers) */ 163 #define NMGRPHX_PLLC_NH 0x8f /* >= NM2200 */ 164 #define NMGRPHX_PLLC_NL 0x9b 165 #define NMGRPHX_PLLC_M 0x9f 166 /* NeoMagic BES registers: (> NM2070) (accessible via mapped I/O: >= NM2097) */ 167 #define NMGRPHX_BESCTRL1 0xb0 168 #define NMGRPHX_HDCOORD21H 0xb1 169 #define NMGRPHX_HDCOORD1L 0xb2 170 #define NMGRPHX_HDCOORD2L 0xb3 171 #define NMGRPHX_VDCOORD21H 0xb4 172 #define NMGRPHX_VDCOORD1L 0xb5 173 #define NMGRPHX_VDCOORD2L 0xb6 174 #define NMGRPHX_BUF1ORGH 0xb7 175 #define NMGRPHX_BUF1ORGM 0xb8 176 #define NMGRPHX_BUF1ORGL 0xb9 177 #define NMGRPHX_BUF1PITCHH 0xba 178 #define NMGRPHX_BUF1PITCHL 0xbb 179 #define NMGRPHX_0xbc 0xbc //?? 180 #define NMGRPHX_0xbd 0xbd //?? 181 #define NMGRPHX_0xbe 0xbe //?? 182 #define NMGRPHX_0xbf 0xbf //?? 183 #define NMGRPHX_XSCALEH 0xc0 184 #define NMGRPHX_XSCALEL 0xc1 185 #define NMGRPHX_YSCALEH 0xc2 186 #define NMGRPHX_YSCALEL 0xc3 187 #define NMGRPHX_BRIGHTNESS 0xc4 188 #define NMGRPHX_COLKEY_R 0xc5 189 #define NMGRPHX_COLKEY_G 0xc6 190 #define NMGRPHX_COLKEY_B 0xc7 191 192 /* NeoMagic specific PCI cursor registers < NM2200 */ 193 #define NMCR1_CURCTRL 0x0100 194 #define NMCR1_CURX 0x0104 195 #define NMCR1_CURY 0x0108 196 #define NMCR1_CURBGCOLOR 0x010c 197 #define NMCR1_CURFGCOLOR 0x0110 198 #define NMCR1_CURADDRESS 0x0114 199 /* NeoMagic specific PCI cursor registers >= NM2200 */ 200 #define NMCR1_22CURCTRL 0x1000 201 #define NMCR1_22CURX 0x1004 202 #define NMCR1_22CURY 0x1008 203 #define NMCR1_22CURBGCOLOR 0x100c 204 #define NMCR1_22CURFGCOLOR 0x1010 205 #define NMCR1_22CURADDRESS 0x1014 206 207 /* NeoMagic PCI acceleration registers */ 208 #define NMACC_STATUS 0x0000 209 #define NMACC_CONTROL 0x0004 210 #define NMACC_FGCOLOR 0x000c 211 #define NMACC_CLIPLT 0x0018 212 #define NMACC_CLIPRB 0x001c 213 #define NMACC_SRCSTARTOFF 0x0024 214 #define NMACC_DSTSTARTOFF 0x002c 215 #define NMACC_XYEXT 0x0030 216 217 218 /* Macros for convenient accesses to the NM chips */ 219 220 /* primary PCI register area */ 221 #define NM_REG8(r_) ((vuint8 *)regs)[(r_)] 222 #define NM_REG16(r_) ((vuint16 *)regs)[(r_) >> 1] 223 #define NM_REG32(r_) ((vuint32 *)regs)[(r_) >> 2] 224 /* secondary PCI register area */ 225 #define NM_2REG8(r_) ((vuint8 *)regs2)[(r_)] 226 #define NM_2REG16(r_) ((vuint16 *)regs2)[(r_) >> 1] 227 #define NM_2REG32(r_) ((vuint32 *)regs2)[(r_) >> 2] 228 229 /* read and write to PCI config space */ 230 #define CFGR(A) (nm_pci_access.offset=NMCFG_##A, ioctl(fd,NM_GET_PCI, &nm_pci_access,sizeof(nm_pci_access)), nm_pci_access.value) 231 #define CFGW(A,B) (nm_pci_access.offset=NMCFG_##A, nm_pci_access.value = B, ioctl(fd,NM_SET_PCI,&nm_pci_access,sizeof(nm_pci_access))) 232 233 /* read and write from acceleration engine */ 234 #define ACCR(A) (NM_REG32(NMACC_##A)) 235 #define ACCW(A,B) (NM_REG32(NMACC_##A) = (B)) 236 237 /* read and write from first CRTC (mapped) */ 238 #define CR1R(A) (NM_REG32(NMCR1_##A)) 239 #define CR1W(A,B) (NM_REG32(NMCR1_##A) = (B)) 240 241 /* read and write from ISA I/O space */ 242 #define ISAWB(A,B)(nm_isa_access.adress=NMISA8_##A, nm_isa_access.data = (uint8)B, nm_isa_access.size = 1, ioctl(fd,NM_ISA_OUT, &nm_isa_access,sizeof(nm_isa_access))) 243 #define ISAWW(A,B)(nm_isa_access.adress=NMISA16_##A, nm_isa_access.data = B, nm_isa_access.size = 2, ioctl(fd,NM_ISA_OUT, &nm_isa_access,sizeof(nm_isa_access))) 244 #define ISARB(A) (nm_isa_access.adress=NMISA8_##A, ioctl(fd,NM_ISA_IN, &nm_isa_access,sizeof(nm_isa_access)), (uint8)nm_isa_access.data) 245 #define ISARW(A) (nm_isa_access.adress=NMISA16_##A, ioctl(fd,NM_ISA_IN, &nm_isa_access,sizeof(nm_isa_access)), nm_isa_access.data) 246 247 /* read and write from ISA CRTC indexed registers */ 248 #define ISACRTCW(A,B)(ISAWW(CRTCIND, ((NMCRTCX_##A) | ((B) << 8)))) 249 #define ISACRTCR(A) (ISAWB(CRTCIND, (NMCRTCX_##A)), ISARB(CRTCDAT)) 250 251 /* read and write from ISA GRAPHICS indexed registers */ 252 #define ISAGRPHW(A,B)(ISAWW(GRPHIND, ((NMGRPHX_##A) | ((B) << 8)))) 253 #define ISAGRPHR(A) (ISAWB(GRPHIND, (NMGRPHX_##A)), ISARB(GRPHDAT)) 254 255 /* read and write from PCI GRAPHICS indexed registers (>= NM2097) */ 256 #define PCIGRPHW(A,B)(NM_2REG16(NM2PCI16_GRPHIND) = ((NMGRPHX_##A) | ((B) << 8))) 257 #define PCIGRPHR(A) (NM_2REG8(NM2PCI8_GRPHIND) = (NMGRPHX_##A), NM_2REG8(NM2PCI8_GRPHDAT)) 258 259 /* read and write from ISA SEQUENCER indexed registers */ 260 #define ISASEQW(A,B)(ISAWW(SEQIND, ((NMSEQX_##A) | ((B) << 8)))) 261 #define ISASEQR(A) (ISAWB(SEQIND, (NMSEQX_##A)), ISARB(SEQDAT)) 262 263 /* read and write from PCI SEQUENCER indexed registers (>= NM2097) */ 264 #define PCISEQW(A,B)(NM_2REG16(NM2PCI16_SEQIND) = ((NMSEQX_##A) | ((B) << 8))) 265 #define PCISEQR(A) (NM_2REG8(NM2PCI8_SEQIND) = (NMSEQX_##A), NM_2REG8(NM2PCI8_SEQDAT)) 266 267 /* read and write from ISA ATTRIBUTE indexed registers */ 268 #define ISAATBW(A,B)((void)ISARB(INSTAT1), ISAWB(ATTRINDW, ((NMATBX_##A) | 0x20)), ISAWB(ATTRDATW, (B))) 269 #define ISAATBR(A) ((void)ISARB(INSTAT1), ISAWB(ATTRINDW, ((NMATBX_##A) | 0x20)), ISARB(ATTRDATR)) 270