1 /* NM registers definitions and macros for access to */ 2 3 //old: 4 /* PCI_config_space */ 5 #define NMCFG_DEVID 0x00 6 #define NMCFG_DEVCTRL 0x04 7 #define NMCFG_CLASS 0x08 8 #define NMCFG_HEADER 0x0c 9 #define NMCFG_NMBASE2 0x10 10 #define NMCFG_NMBASE1 0x14 11 #define NMCFG_NMBASE3 0x18 // >= MYST 12 #define NMCFG_SUBSYSIDR 0x2c // >= MYST 13 #define NMCFG_ROMBASE 0x30 14 #define NMCFG_CAP_PTR 0x34 // >= MIL2 15 #define NMCFG_INTCTRL 0x3c 16 #define NMCFG_OPTION 0x40 17 #define NMCFG_NM_INDEX 0x44 18 #define NMCFG_NM_DATA 0x48 19 #define NMCFG_SUBSYSIDW 0x4c // >= MYST 20 #define NMCFG_OPTION2 0x50 // >= G100 21 #define NMCFG_OPTION3 0x54 // >= G400 22 #define NMCFG_OPTION4 0x58 // >= G450 23 #define NMCFG_PM_IDENT 0xdc // >= G100 24 #define NMCFG_PM_CSR 0xe0 // >= G100 25 #define NMCFG_AGP_IDENT 0xf0 // >= MIL2 26 #define NMCFG_AGP_STS 0xf4 // >= MIL2 27 #define NMCFG_AGP_CMD 0xf8 // >= MIL2 28 //end old. 29 30 /* neomagic ISA direct registers */ 31 /* VGA standard registers: */ 32 #define NMISA8_ATTRINDW 0x03c0 33 #define NMISA8_ATTRINDR 0x03c1 34 #define NMISA8_ATTRDATW 0x03c0 35 #define NMISA8_ATTRDATR 0x03c1 36 #define NMISA8_SEQIND 0x03c4 37 #define NMISA8_SEQDAT 0x03c5 38 #define NMISA16_SEQIND 0x03c4 39 #define NMISA8_CRTCIND 0x03d4 40 #define NMISA8_CRTCDAT 0x03d5 41 #define NMISA16_CRTCIND 0x03d4 42 #define NMISA8_GRPHIND 0x03ce 43 #define NMISA8_GRPHDAT 0x03cf 44 #define NMISA16_GRPHIND 0x03ce 45 46 /* neomagic PCI direct registers */ 47 #define NM2PCI8_SEQIND 0x03c4 48 #define NM2PCI8_SEQDAT 0x03c5 49 #define NM2PCI16_SEQIND 0x03c4 50 #define NM2PCI8_GRPHIND 0x03ce 51 #define NM2PCI8_GRPHDAT 0x03cf 52 #define NM2PCI16_GRPHIND 0x03ce 53 54 /* neomagic ISA GENERAL direct registers */ 55 /* VGA standard registers: */ 56 #define NMISA8_MISCW 0x03c2 57 #define NMISA8_MISCR 0x03cc 58 #define NMISA8_INSTAT1 0x03da 59 60 /* neomagic ISA (DAC) COLOR direct registers (VGA palette RAM) */ 61 /* VGA standard registers: */ 62 #define NMISA8_PALMASK 0x03c6 63 #define NMISA8_PALINDR 0x03c7 64 #define NMISA8_PALINDW 0x03c8 65 #define NMISA8_PALDATA 0x03c9 66 67 /* neomagic ISA CRTC indexed registers */ 68 /* VGA standard registers: */ 69 #define NMCRTCX_HTOTAL 0x00 70 #define NMCRTCX_HDISPE 0x01 71 #define NMCRTCX_HBLANKS 0x02 72 #define NMCRTCX_HBLANKE 0x03 73 #define NMCRTCX_HSYNCS 0x04 74 #define NMCRTCX_HSYNCE 0x05 75 #define NMCRTCX_VTOTAL 0x06 76 #define NMCRTCX_OVERFLOW 0x07 77 #define NMCRTCX_PRROWSCN 0x08 78 #define NMCRTCX_MAXSCLIN 0x09 79 #define NMCRTCX_VGACURCTRL 0x0a 80 #define NMCRTCX_FBSTADDH 0x0c 81 #define NMCRTCX_FBSTADDL 0x0d 82 #define NMCRTCX_VSYNCS 0x10 83 #define NMCRTCX_VSYNCE 0x11 84 #define NMCRTCX_VDISPE 0x12 85 #define NMCRTCX_PITCHL 0x13 86 #define NMCRTCX_VBLANKS 0x15 87 #define NMCRTCX_VBLANKE 0x16 88 #define NMCRTCX_MODECTL 0x17 89 #define NMCRTCX_LINECOMP 0x18 90 /* NeoMagic specific registers: */ 91 #define NMCRTCX_PANEL_0x40 0x40 92 #define NMCRTCX_PANEL_0x41 0x41 93 #define NMCRTCX_PANEL_0x42 0x42 94 #define NMCRTCX_PANEL_0x43 0x43 95 #define NMCRTCX_PANEL_0x44 0x44 96 #define NMCRTCX_PANEL_0x45 0x45 97 #define NMCRTCX_PANEL_0x46 0x46 98 #define NMCRTCX_PANEL_0x47 0x47 99 #define NMCRTCX_PANEL_0x48 0x48 100 #define NMCRTCX_PANEL_0x49 0x49 101 #define NMCRTCX_PANEL_0x4a 0x4a 102 #define NMCRTCX_PANEL_0x4b 0x4b 103 #define NMCRTCX_PANEL_0x4c 0x4c 104 #define NMCRTCX_PANEL_0x4d 0x4d 105 #define NMCRTCX_PANEL_0x4e 0x4e 106 #define NMCRTCX_PANEL_0x4f 0x4f 107 #define NMCRTCX_PANEL_0x50 0x50 /* >= NM2090 */ 108 #define NMCRTCX_PANEL_0x51 0x51 /* >= NM2090 */ 109 #define NMCRTCX_PANEL_0x52 0x52 /* >= NM2090 */ 110 #define NMCRTCX_PANEL_0x53 0x53 /* >= NM2090 */ 111 #define NMCRTCX_PANEL_0x54 0x54 /* >= NM2090 */ 112 #define NMCRTCX_PANEL_0x55 0x55 /* >= NM2090 */ 113 #define NMCRTCX_PANEL_0x56 0x56 /* >= NM2090 */ 114 #define NMCRTCX_PANEL_0x57 0x57 /* >= NM2090 */ 115 #define NMCRTCX_PANEL_0x58 0x58 /* >= NM2090 */ 116 #define NMCRTCX_PANEL_0x59 0x59 /* >= NM2090 */ 117 #define NMCRTCX_PANEL_0x60 0x60 /* >= NM2097(?) */ 118 #define NMCRTCX_PANEL_0x61 0x61 /* >= NM2097(?) */ 119 #define NMCRTCX_PANEL_0x62 0x62 /* >= NM2097(?) */ 120 #define NMCRTCX_PANEL_0x63 0x63 /* >= NM2097(?) */ 121 #define NMCRTCX_PANEL_0x64 0x64 /* >= NM2097(?) */ 122 #define NMCRTCX_VEXT 0x70 /* >= NM2200 */ 123 124 /* neomagic ISA SEQUENCER indexed registers */ 125 /* VGA standard registers: */ 126 #define NMSEQX_RESET 0x00 127 #define NMSEQX_CLKMODE 0x01 128 #define NMSEQX_MAPMASK 0x02 129 #define NMSEQX_MEMMODE 0x04 130 /* NeoMagic BES registers: (> NM2070) (accessible via mapped I/O: >= NM2097) */ 131 #define NMSEQX_BESCTRL2 0x08 132 #define NMSEQX_0x09 0x09 //?? 133 #define NMSEQX_ZVCAP_DSCAL 0x0a 134 #define NMSEQX_BUF2ORGL 0x0c 135 #define NMSEQX_BUF2ORGM 0x0d 136 #define NMSEQX_BUF2ORGH 0x0e 137 #define NMSEQX_VD2COORD1L 0x14 /* >= NM2200(?) */ 138 #define NMSEQX_VD2COORD2L 0x15 /* >= NM2200(?) */ 139 #define NMSEQX_VD2COORD21H 0x16 /* >= NM2200(?) */ 140 #define NMSEQX_HD2COORD1L 0x17 /* >= NM2200(?) */ 141 #define NMSEQX_HD2COORD2L 0x18 /* >= NM2200(?) */ 142 #define NMSEQX_HD2COORD21H 0x19 /* >= NM2200(?) */ 143 #define NMSEQX_BUF2PITCHL 0x1a 144 #define NMSEQX_BUF2PITCHH 0x1b 145 #define NMSEQX_0x1c 0x1c //?? 146 #define NMSEQX_0x1d 0x1d //?? 147 #define NMSEQX_0x1e 0x1e //?? 148 #define NMSEQX_0x1f 0x1f //?? 149 150 /* neomagic ISA ATTRIBUTE indexed registers */ 151 /* VGA standard registers: */ 152 #define NMATBX_MODECTL 0x10 153 #define NMATBX_OSCANCOLOR 0x11 154 #define NMATBX_COLPLANE_EN 0x12 155 #define NMATBX_HORPIXPAN 0x13 156 #define NMATBX_COLSEL 0x14 157 #define NMATBX_0x16 0x16 158 159 /* neomagic ISA GRAPHICS indexed registers */ 160 /* VGA standard registers: */ 161 #define NMGRPHX_ENSETRESET 0x01 162 #define NMGRPHX_DATAROTATE 0x03 163 #define NMGRPHX_READMAPSEL 0x04 164 #define NMGRPHX_MODE 0x05 165 #define NMGRPHX_MISC 0x06 166 #define NMGRPHX_BITMASK 0x08 167 /* NeoMagic specific registers: */ 168 #define NMGRPHX_GRPHXLOCK 0x09 169 #define NMGRPHX_GENLOCK 0x0a 170 #define NMGRPHX_FBSTADDE 0x0e 171 #define NMGRPHX_CRTC_PITCHE 0x0f /* > NM2070 */ 172 #define NMGRPHX_IFACECTRL1 0x10 173 #define NMGRPHX_IFACECTRL2 0x11 174 #define NMGRPHX_0x15 0x15 175 #define NMGRPHX_ACT_CLK_SAV 0x19 /* >= NM2200? auto-pwr-save.. (b2-0) */ 176 #define NMGRPHX_PANELCTRL1 0x20 177 #define NMGRPHX_PANELTYPE 0x21 178 #define NMGRPHX_PANELCTRL2 0x25 179 #define NMGRPHX_PANELVCENT1 0x28 180 #define NMGRPHX_PANELVCENT2 0x29 181 #define NMGRPHX_PANELVCENT3 0x2a 182 #define NMGRPHX_PANELCTRL3 0x30 /* > NM2070 */ 183 #define NMGRPHX_PANELVCENT4 0x32 /* > NM2070 */ 184 #define NMGRPHX_PANELHCENT1 0x33 /* > NM2070 */ 185 #define NMGRPHX_PANELHCENT2 0x34 /* > NM2070 */ 186 #define NMGRPHX_PANELHCENT3 0x35 /* > NM2070 */ 187 #define NMGRPHX_PANELHCENT4 0x36 /* >= NM2160 */ 188 #define NMGRPHX_PANELVCENT5 0x37 /* >= NM2200 */ 189 #define NMGRPHX_PANELHCENT5 0x38 /* >= NM2200 */ 190 #define NMGRPHX_CURCTRL 0x82 191 #define NMGRPHX_COLDEPTH 0x90 192 /* mem or core PLL register??? */ 193 #define NMGRPHX_SPEED 0x93 194 /* (NeoMagic pixelPLL set C registers) */ 195 #define NMGRPHX_PLLC_NH 0x8f /* >= NM2200 */ 196 #define NMGRPHX_PLLC_NL 0x9b 197 #define NMGRPHX_PLLC_M 0x9f 198 /* NeoMagic BES registers: (> NM2070) (accessible via mapped I/O: >= NM2097) */ 199 #define NMGRPHX_BESCTRL1 0xb0 200 #define NMGRPHX_HD1COORD21H 0xb1 201 #define NMGRPHX_HD1COORD1L 0xb2 202 #define NMGRPHX_HD1COORD2L 0xb3 203 #define NMGRPHX_VD1COORD21H 0xb4 204 #define NMGRPHX_VD1COORD1L 0xb5 205 #define NMGRPHX_VD1COORD2L 0xb6 206 #define NMGRPHX_BUF1ORGH 0xb7 207 #define NMGRPHX_BUF1ORGM 0xb8 208 #define NMGRPHX_BUF1ORGL 0xb9 209 #define NMGRPHX_BUF1PITCHH 0xba 210 #define NMGRPHX_BUF1PITCHL 0xbb 211 #define NMGRPHX_0xbc 0xbc //?? 212 #define NMGRPHX_0xbd 0xbd //?? 213 #define NMGRPHX_0xbe 0xbe //?? 214 #define NMGRPHX_0xbf 0xbf //?? 215 #define NMGRPHX_XSCALEH 0xc0 216 #define NMGRPHX_XSCALEL 0xc1 217 #define NMGRPHX_YSCALEH 0xc2 218 #define NMGRPHX_YSCALEL 0xc3 219 #define NMGRPHX_BRIGHTNESS 0xc4 220 #define NMGRPHX_COLKEY_R 0xc5 221 #define NMGRPHX_COLKEY_G 0xc6 222 #define NMGRPHX_COLKEY_B 0xc7 223 224 /* NeoMagic specific PCI cursor registers < NM2200 */ 225 #define NMCR1_CURCTRL 0x0100 226 #define NMCR1_CURX 0x0104 227 #define NMCR1_CURY 0x0108 228 #define NMCR1_CURBGCOLOR 0x010c 229 #define NMCR1_CURFGCOLOR 0x0110 230 #define NMCR1_CURADDRESS 0x0114 231 /* NeoMagic specific PCI cursor registers >= NM2200 */ 232 #define NMCR1_22CURCTRL 0x1000 233 #define NMCR1_22CURX 0x1004 234 #define NMCR1_22CURY 0x1008 235 #define NMCR1_22CURBGCOLOR 0x100c 236 #define NMCR1_22CURFGCOLOR 0x1010 237 #define NMCR1_22CURADDRESS 0x1014 238 239 /* NeoMagic PCI acceleration registers */ 240 /* all cards, but some registers only on 2090 and later; and some on 2200 and later */ 241 #define NMACC_STATUS 0x0000 242 #define NMACC_CONTROL 0x0004 243 #define NMACC_FGCOLOR 0x000c 244 #define NMACC_2200_SRC_PITCH 0x0014 245 #define NMACC_2090_CLIPLT 0x0018 246 #define NMACC_2090_CLIPRB 0x001c 247 #define NMACC_SRCSTARTOFF 0x0024 248 #define NMACC_2090_DSTSTARTOFF 0x002c 249 #define NMACC_2090_XYEXT 0x0030 250 /* NM2070 only */ 251 #define NMACC_2070_PLANEMASK 0x0014 252 #define NMACC_2070_XYEXT 0x0018 253 #define NMACC_2070_SRCPITCH 0x001c 254 #define NMACC_2070_SRCBITOFF 0x0020 255 #define NMACC_2070_DSTPITCH 0x0028 256 #define NMACC_2070_DSTBITOFF 0x002c 257 #define NMACC_2070_DSTSTARTOFF 0x0030 258 259 260 /* Macros for convenient accesses to the NM chips */ 261 262 /* primary PCI register area */ 263 #define NM_REG8(r_) ((vuint8 *)regs)[(r_)] 264 #define NM_REG16(r_) ((vuint16 *)regs)[(r_) >> 1] 265 #define NM_REG32(r_) ((vuint32 *)regs)[(r_) >> 2] 266 /* secondary PCI register area */ 267 #define NM_2REG8(r_) ((vuint8 *)regs2)[(r_)] 268 #define NM_2REG16(r_) ((vuint16 *)regs2)[(r_) >> 1] 269 #define NM_2REG32(r_) ((vuint32 *)regs2)[(r_) >> 2] 270 271 /* read and write to PCI config space */ 272 #define CFGR(A) (nm_pci_access.offset=NMCFG_##A, ioctl(fd,NM_GET_PCI, &nm_pci_access,sizeof(nm_pci_access)), nm_pci_access.value) 273 #define CFGW(A,B) (nm_pci_access.offset=NMCFG_##A, nm_pci_access.value = B, ioctl(fd,NM_SET_PCI,&nm_pci_access,sizeof(nm_pci_access))) 274 275 /* read and write from acceleration engine */ 276 #define ACCR(A) (NM_REG32(NMACC_##A)) 277 #define ACCW(A,B) (NM_REG32(NMACC_##A) = (B)) 278 279 /* read and write from first CRTC (mapped) */ 280 #define CR1R(A) (NM_REG32(NMCR1_##A)) 281 #define CR1W(A,B) (NM_REG32(NMCR1_##A) = (B)) 282 283 /* read and write from ISA I/O space */ 284 #define ISAWB(A,B)(nm_isa_access.adress=NMISA8_##A, nm_isa_access.data = (uint8)B, nm_isa_access.size = 1, ioctl(fd,NM_ISA_OUT, &nm_isa_access,sizeof(nm_isa_access))) 285 #define ISAWW(A,B)(nm_isa_access.adress=NMISA16_##A, nm_isa_access.data = B, nm_isa_access.size = 2, ioctl(fd,NM_ISA_OUT, &nm_isa_access,sizeof(nm_isa_access))) 286 #define ISARB(A) (nm_isa_access.adress=NMISA8_##A, ioctl(fd,NM_ISA_IN, &nm_isa_access,sizeof(nm_isa_access)), (uint8)nm_isa_access.data) 287 #define ISARW(A) (nm_isa_access.adress=NMISA16_##A, ioctl(fd,NM_ISA_IN, &nm_isa_access,sizeof(nm_isa_access)), nm_isa_access.data) 288 289 /* read and write from ISA CRTC indexed registers */ 290 #define ISACRTCW(A,B)(ISAWW(CRTCIND, ((NMCRTCX_##A) | ((B) << 8)))) 291 #define ISACRTCR(A) (ISAWB(CRTCIND, (NMCRTCX_##A)), ISARB(CRTCDAT)) 292 293 /* read and write from ISA GRAPHICS indexed registers */ 294 #define ISAGRPHW(A,B)(ISAWW(GRPHIND, ((NMGRPHX_##A) | ((B) << 8)))) 295 #define ISAGRPHR(A) (ISAWB(GRPHIND, (NMGRPHX_##A)), ISARB(GRPHDAT)) 296 297 /* read and write from PCI GRAPHICS indexed registers (>= NM2097) */ 298 #define PCIGRPHW(A,B)(NM_2REG16(NM2PCI16_GRPHIND) = ((NMGRPHX_##A) | ((B) << 8))) 299 #define PCIGRPHR(A) (NM_2REG8(NM2PCI8_GRPHIND) = (NMGRPHX_##A), NM_2REG8(NM2PCI8_GRPHDAT)) 300 301 /* read and write from ISA SEQUENCER indexed registers */ 302 #define ISASEQW(A,B)(ISAWW(SEQIND, ((NMSEQX_##A) | ((B) << 8)))) 303 #define ISASEQR(A) (ISAWB(SEQIND, (NMSEQX_##A)), ISARB(SEQDAT)) 304 305 /* read and write from PCI SEQUENCER indexed registers (>= NM2097) */ 306 #define PCISEQW(A,B)(NM_2REG16(NM2PCI16_SEQIND) = ((NMSEQX_##A) | ((B) << 8))) 307 #define PCISEQR(A) (NM_2REG8(NM2PCI8_SEQIND) = (NMSEQX_##A), NM_2REG8(NM2PCI8_SEQDAT)) 308 309 /* read and write from ISA ATTRIBUTE indexed registers */ 310 #define ISAATBW(A,B)((void)ISARB(INSTAT1), ISAWB(ATTRINDW, ((NMATBX_##A) | 0x20)), ISAWB(ATTRDATW, (B))) 311 #define ISAATBR(A) ((void)ISARB(INSTAT1), ISAWB(ATTRINDW, ((NMATBX_##A) | 0x20)), ISARB(ATTRDATR)) 312