1 /* NM registers definitions and macros for access to */ 2 3 /* PCI_config_space */ 4 #define NMCFG_DEVID 0x00 5 #define NMCFG_DEVCTRL 0x04 6 #define NMCFG_CLASS 0x08 7 #define NMCFG_HEADER 0x0c 8 #define NMCFG_NMBASE2 0x10 9 #define NMCFG_NMBASE1 0x14 10 #define NMCFG_NMBASE3 0x18 // >= MYST 11 #define NMCFG_SUBSYSIDR 0x2c // >= MYST 12 #define NMCFG_ROMBASE 0x30 13 #define NMCFG_CAP_PTR 0x34 // >= MIL2 14 #define NMCFG_INTCTRL 0x3c 15 #define NMCFG_OPTION 0x40 16 #define NMCFG_NM_INDEX 0x44 17 #define NMCFG_NM_DATA 0x48 18 #define NMCFG_SUBSYSIDW 0x4c // >= MYST 19 #define NMCFG_OPTION2 0x50 // >= G100 20 #define NMCFG_OPTION3 0x54 // >= G400 21 #define NMCFG_OPTION4 0x58 // >= G450 22 #define NMCFG_PM_IDENT 0xdc // >= G100 23 #define NMCFG_PM_CSR 0xe0 // >= G100 24 #define NMCFG_AGP_IDENT 0xf0 // >= MIL2 25 #define NMCFG_AGP_STS 0xf4 // >= MIL2 26 #define NMCFG_AGP_CMD 0xf8 // >= MIL2 27 28 //new: 29 /* neomagic ISA direct registers */ 30 /* VGA standard registers: */ 31 #define NMISA8_ATTRINDW 0x03c0 32 #define NMISA8_ATTRINDR 0x03c1 33 #define NMISA8_ATTRDATW 0x03c0 34 #define NMISA8_ATTRDATR 0x03c1 35 #define NMISA8_SEQIND 0x03c4 36 #define NMISA8_SEQDAT 0x03c5 37 #define NMISA16_SEQIND 0x03c4 38 #define NMISA8_CRTCIND 0x03d4 39 #define NMISA8_CRTCDAT 0x03d5 40 #define NMISA16_CRTCIND 0x03d4 41 #define NMISA8_GRPHIND 0x03ce 42 #define NMISA8_GRPHDAT 0x03cf 43 #define NMISA16_GRPHIND 0x03ce 44 45 /* neomagic ISA GENERAL direct registers */ 46 /* VGA standard registers: */ 47 #define NMISA8_MISCW 0x03c2 48 #define NMISA8_MISCR 0x03cc 49 #define NMISA8_INSTAT1 0x03da 50 51 /* neomagic ISA (DAC) COLOR direct registers (VGA palette RAM) */ 52 /* VGA standard registers: */ 53 #define NMISA8_PALMASK 0x03c6 54 #define NMISA8_PALINDR 0x03c7 55 #define NMISA8_PALINDW 0x03c8 56 #define NMISA8_PALDATA 0x03c9 57 58 /* neomagic ISA CRTC indexed registers */ 59 /* VGA standard registers: */ 60 #define NMCRTCX_HTOTAL 0x00 61 #define NMCRTCX_HDISPE 0x01 62 #define NMCRTCX_HBLANKS 0x02 63 #define NMCRTCX_HBLANKE 0x03 64 #define NMCRTCX_HSYNCS 0x04 65 #define NMCRTCX_HSYNCE 0x05 66 #define NMCRTCX_VTOTAL 0x06 67 #define NMCRTCX_OVERFLOW 0x07 68 #define NMCRTCX_PRROWSCN 0x08 69 #define NMCRTCX_MAXSCLIN 0x09 70 #define NMCRTCX_VGACURCTRL 0x0a 71 #define NMCRTCX_FBSTADDH 0x0c 72 #define NMCRTCX_FBSTADDL 0x0d 73 #define NMCRTCX_VSYNCS 0x10 74 #define NMCRTCX_VSYNCE 0x11 75 #define NMCRTCX_VDISPE 0x12 76 #define NMCRTCX_PITCHL 0x13 77 #define NMCRTCX_VBLANKS 0x15 78 #define NMCRTCX_VBLANKE 0x16 79 #define NMCRTCX_MODECTL 0x17 80 #define NMCRTCX_LINECOMP 0x18 81 /* NeoMagic specific registers: */ 82 #define NMCRTCX_VEXT 0x70 /* >= NM2200 */ 83 84 /* neomagic ISA SEQUENCER indexed registers */ 85 /* VGA standard registers: */ 86 #define NMSEQX_RESET 0x00 87 #define NMSEQX_CLKMODE 0x01 88 #define NMSEQX_MEMMODE 0x04 89 90 /* neomagic ISA ATTRIBUTE indexed registers */ 91 /* VGA standard registers: */ 92 #define NMATBX_MODECTL 0x10 93 #define NMATBX_OSCANCOLOR 0x11 94 #define NMATBX_COLPLANE_EN 0x12 95 #define NMATBX_HORPIXPAN 0x13 96 #define NMATBX_COLSEL 0x14 97 98 /* neomagic ISA GRAPHICS indexed registers */ 99 /* VGA standard registers: */ 100 #define NMGRPHX_ENSETRESET 0x01 101 #define NMGRPHX_DATAROTATE 0x03 102 #define NMGRPHX_READMAPSEL 0x04 103 #define NMGRPHX_MODE 0x05 104 #define NMGRPHX_MISC 0x06 105 #define NMGRPHX_BITMASK 0x08 106 /* NeoMagic specific registers: */ 107 #define NMGRPHX_GRPHXLOCK 0x09 108 #define NMGRPHX_GENLOCK 0x0a 109 #define NMGRPHX_FBSTADDE 0x0e 110 #define NMGRPHX_CRTC_PITCHE 0x0f 111 #define NMGRPHX_IFACECTRL 0x11 112 #define NMGRPHX_PANELCTRL1 0x20 113 #define NMGRPHX_PANELTYPE 0x21 114 #define NMGRPHX_PANELCTRL2 0x25 115 #define NMGRPHX_PANELVCENT1 0x28 116 #define NMGRPHX_PANELVCENT2 0x29 117 #define NMGRPHX_PANELVCENT3 0x2a 118 #define NMGRPHX_PANELCTRL3 0x30 /* > NM2070 */ 119 #define NMGRPHX_PANELVCENT4 0x32 /* > NM2070 */ 120 #define NMGRPHX_PANELHCENT1 0x33 /* > NM2070 */ 121 #define NMGRPHX_PANELHCENT2 0x34 /* > NM2070 */ 122 #define NMGRPHX_PANELHCENT3 0x35 /* > NM2070 */ 123 #define NMGRPHX_PANELHCENT4 0x36 /* >= NM2160 */ 124 #define NMGRPHX_PANELVCENT5 0x37 /* >= NM2200 */ 125 #define NMGRPHX_PANELHCENT5 0x38 /* >= NM2200 */ 126 #define NMGRPHX_CURCTRL 0x82 127 #define NMGRPHX_COLDEPTH 0x90 128 /* (NeoMagic pixelPLL set C registers) */ 129 #define NMGRPHX_PLLC_NL 0x9b 130 #define NMGRPHX_PLLC_NH 0x8f /* >= NM2200 */ 131 #define NMGRPHX_PLLC_M 0x9f 132 133 /* NeoMagic specific PCI cursor registers < NM2200 */ 134 #define NMCR1_CURCTRL 0x0100 135 #define NMCR1_CURX 0x0104 136 #define NMCR1_CURY 0x0108 137 #define NMCR1_CURBGCOLOR 0x010c 138 #define NMCR1_CURFGCOLOR 0x0110 139 #define NMCR1_CURADDRESS 0x0114 140 /* NeoMagic specific PCI cursor registers >= NM2200 */ 141 #define NMCR1_22CURCTRL 0x1000 142 #define NMCR1_22CURX 0x1004 143 #define NMCR1_22CURY 0x1008 144 #define NMCR1_22CURBGCOLOR 0x100c 145 #define NMCR1_22CURFGCOLOR 0x1010 146 #define NMCR1_22CURADDRESS 0x1014 147 //end new. 148 149 /* NM ACCeleration registers */ 150 #define NMACC_DWGCTL 0x1C00 151 #define NMACC_MACCESS 0x1C04 152 #define NMACC_MCTLWTST 0x1C08 153 #define NMACC_ZORG 0x1C0C 154 #define NMACC_PLNWT 0x1C1C 155 #define NMACC_BCOL 0x1C20 156 #define NMACC_FCOL 0x1C24 157 #define NMACC_XYSTRT 0x1C40 158 #define NMACC_XYEND 0x1C44 159 #define NMACC_SGN 0x1C58 160 #define NMACC_LEN 0x1C5C 161 #define NMACC_AR0 0x1C60 162 #define NMACC_AR3 0x1C6C 163 #define NMACC_AR5 0x1C74 164 #define NMACC_CXBNDRY 0x1C80 165 #define NMACC_FXBNDRY 0x1C84 166 #define NMACC_YDSTLEN 0x1C88 167 #define NMACC_PITCH 0x1C8C 168 #define NMACC_YDST 0x1C90 169 #define NMACC_YDSTORG 0x1C94 170 #define NMACC_YTOP 0x1C98 171 #define NMACC_YBOT 0x1C9C 172 #define NMACC_CXLEFT 0x1CA0 173 #define NMACC_CXRIGHT 0x1CA4 174 #define NMACC_FXLEFT 0x1CA8 175 #define NMACC_FXRIGHT 0x1CAC 176 #define NMACC_STATUS 0x1E14 177 #define NMACC_ICLEAR 0x1E18 /* required for interrupt stuff */ 178 #define NMACC_IEN 0x1E1C /* required for interrupt stuff */ 179 #define NMACC_RST 0x1E40 180 #define NMACC_MEMRDBK 0x1E44 181 #define NMACC_OPMODE 0x1E54 182 #define NMACC_PRIMADDRESS 0x1E58 183 #define NMACC_PRIMEND 0x1E5C 184 #define NMACC_TEXORG 0x2C24 // >= G100 185 #define NMACC_DWGSYNC 0x2C4C // >= G200 186 #define NMACC_TEXORG1 0x2CA4 // >= G200 187 #define NMACC_TEXORG2 0x2CA8 // >= G200 188 #define NMACC_TEXORG3 0x2CAC // >= G200 189 #define NMACC_TEXORG4 0x2CB0 // >= G200 190 #define NMACC_SRCORG 0x2CB4 // >= G200 191 #define NMACC_DSTORG 0x2CB8 // >= G200 192 193 /*NM BES (Back End Scaler) registers (>= G200) */ 194 #define NMBES_A1ORG 0x3D00 195 #define NMBES_A2ORG 0x3D04 196 #define NMBES_B1ORG 0x3D08 197 #define NMBES_B2ORG 0x3D0C 198 #define NMBES_A1CORG 0x3D10 199 #define NMBES_A2CORG 0x3D14 200 #define NMBES_B1CORG 0x3D18 201 #define NMBES_B2CORG 0x3D1C 202 #define NMBES_CTL 0x3D20 203 #define NMBES_PITCH 0x3D24 204 #define NMBES_HCOORD 0x3D28 205 #define NMBES_VCOORD 0x3D2C 206 #define NMBES_HISCAL 0x3D30 207 #define NMBES_VISCAL 0x3D34 208 #define NMBES_HSRCST 0x3D38 209 #define NMBES_HSRCEND 0x3D3C 210 #define NMBES_LUMACTL 0x3D40 211 #define NMBES_V1WGHT 0x3D48 212 #define NMBES_V2WGHT 0x3D4C 213 #define NMBES_HSRCLST 0x3D50 214 #define NMBES_V1SRCLST 0x3D54 215 #define NMBES_V2SRCLST 0x3D58 216 #define NMBES_A1C3ORG 0x3D60 217 #define NMBES_A2C3ORG 0x3D64 218 #define NMBES_B1C3ORG 0x3D68 219 #define NMBES_B2C3ORG 0x3D6C 220 #define NMBES_GLOBCTL 0x3DC0 221 #define NMBES_STATUS 0x3DC4 222 223 /* Macros for convenient accesses to the NM chips */ 224 225 #define NM_REG8(r_) ((vuint8 *)regs)[(r_)] 226 #define NM_REG32(r_) ((vuint32 *)regs)[(r_) >> 2] 227 228 /* read and write to PCI config space */ 229 #define CFGR(A) (mn_pci_access.offset=NMCFG_##A, ioctl(fd,MN_GET_PCI, &mn_pci_access,sizeof(mn_pci_access)), mn_pci_access.value) 230 #define CFGW(A,B) (mn_pci_access.offset=NMCFG_##A, mn_pci_access.value = B, ioctl(fd,MN_SET_PCI,&mn_pci_access,sizeof(mn_pci_access))) 231 232 /* read and write from the powergraphics registers */ 233 #define ACCR(A) (NM_REG32(NMACC_##A)) 234 #define ACCW(A,B) (NM_REG32(NMACC_##A)=B) 235 #define ACCGO(A,B) (NM_REG32(NMACC_##A + 0x0100)=B) 236 237 /* read and write from the backend scaler registers */ 238 #define BESR(A) (NM_REG32(NMBES_##A)) 239 #define BESW(A,B) (NM_REG32(NMBES_##A)=B) 240 241 //new: 242 /* read and write from first CRTC (mapped) */ 243 #define CR1R(A) (NM_REG32(NMCR1_##A)) 244 #define CR1W(A,B) (NM_REG32(NMCR1_##A) = (B)) 245 246 /* read and write from ISA I/O space */ 247 #define ISAWB(A,B)(mn_isa_access.adress=NMISA8_##A, mn_isa_access.data = (uint8)B, mn_isa_access.size = 1, ioctl(fd,MN_ISA_OUT, &mn_isa_access,sizeof(mn_isa_access))) 248 #define ISAWW(A,B)(mn_isa_access.adress=NMISA16_##A, mn_isa_access.data = B, mn_isa_access.size = 2, ioctl(fd,MN_ISA_OUT, &mn_isa_access,sizeof(mn_isa_access))) 249 #define ISARB(A) (mn_isa_access.adress=NMISA8_##A, ioctl(fd,MN_ISA_IN, &mn_isa_access,sizeof(mn_isa_access)), (uint8)mn_isa_access.data) 250 #define ISARW(A) (mn_isa_access.adress=NMISA16_##A, ioctl(fd,MN_ISA_IN, &mn_isa_access,sizeof(mn_isa_access)), mn_isa_access.data) 251 252 /* read and write from ISA CRTC indexed registers */ 253 #define ISACRTCW(A,B)(ISAWW(CRTCIND, ((NMCRTCX_##A) | ((B) << 8)))) 254 #define ISACRTCR(A) (ISAWB(CRTCIND, (NMCRTCX_##A)), ISARB(CRTCDAT)) 255 256 /* read and write from ISA GRAPHICS indexed registers */ 257 #define ISAGRPHW(A,B)(ISAWW(GRPHIND, ((NMGRPHX_##A) | ((B) << 8)))) 258 #define ISAGRPHR(A) (ISAWB(GRPHIND, (NMGRPHX_##A)), ISARB(GRPHDAT)) 259 260 /* read and write from ISA SEQUENCER indexed registers */ 261 #define ISASEQW(A,B)(ISAWW(SEQIND, ((NMSEQX_##A) | ((B) << 8)))) 262 #define ISASEQR(A) (ISAWB(SEQIND, (NMSEQX_##A)), ISARB(SEQDAT)) 263 264 /* read and write from ISA ATTRIBUTE indexed registers */ 265 /* define DUMMY to prevent compiler warnings */ 266 #define static uint8 DUMMY; 267 #define ISAATBW(A,B)(DUMMY = ISARB(INSTAT1), ISAWB(ATTRINDW, ((NMATBX_##A) | 0x20)), ISAWB(ATTRDATW, (B))) 268 #define ISAATBR(A) (DUMMY = ISARB(INSTAT1), ISAWB(ATTRINDW, ((NMATBX_##A) | 0x20)), ISARB(ATTRDATR)) 269