10252982aSshatty /* NM registers definitions and macros for access to */ 20252982aSshatty 30252982aSshatty /* PCI_config_space */ 40252982aSshatty #define NMCFG_DEVID 0x00 50252982aSshatty #define NMCFG_DEVCTRL 0x04 60252982aSshatty #define NMCFG_CLASS 0x08 70252982aSshatty #define NMCFG_HEADER 0x0c 8*d7c38808SRudolf Cornelissen #define NMCFG_BASE1FB 0x10 9*d7c38808SRudolf Cornelissen #define NMCFG_BASE2REG1 0x14 10*d7c38808SRudolf Cornelissen #define NMCFG_BASE3REG2 0x18 11*d7c38808SRudolf Cornelissen #define NMCFG_BASE4 0x1c //unknown if used 12*d7c38808SRudolf Cornelissen #define NMCFG_BASE5 0x20 //unknown if used 13*d7c38808SRudolf Cornelissen #define NMCFG_BASE6 0x24 //unknown if used 14*d7c38808SRudolf Cornelissen #define NMCFG_BASE7 0x28 //unknown if used 15*d7c38808SRudolf Cornelissen #define NMCFG_SUBSYSID1 0x2c 160252982aSshatty #define NMCFG_ROMBASE 0x30 17*d7c38808SRudolf Cornelissen #define NMCFG_CAPPTR 0x34 18*d7c38808SRudolf Cornelissen #define NMCFG_CFG_1 0x38 //unknown if used 19*d7c38808SRudolf Cornelissen #define NMCFG_INTERRUPT 0x3c 20*d7c38808SRudolf Cornelissen #define NMCFG_CFG_3 0x40 //unknown if used 21*d7c38808SRudolf Cornelissen #define NMCFG_CFG_4 0x44 //unknown if used 22*d7c38808SRudolf Cornelissen #define NMCFG_CFG_5 0x48 //unknown if used 23*d7c38808SRudolf Cornelissen #define NMCFG_CFG_6 0x4c //unknown if used 24*d7c38808SRudolf Cornelissen #define NMCFG_CFG_7 0x50 //unknown if used 25*d7c38808SRudolf Cornelissen #define NMCFG_CFG_8 0x54 //unknown if used 26*d7c38808SRudolf Cornelissen #define NMCFG_CFG_9 0x58 //unknown if used 27*d7c38808SRudolf Cornelissen #define NMCFG_CFG_10 0x5c //unknown if used 28*d7c38808SRudolf Cornelissen #define NMCFG_CFG_11 0x60 //unknown if used 29*d7c38808SRudolf Cornelissen #define NMCFG_CFG_12 0x64 //unknown if used 30*d7c38808SRudolf Cornelissen #define NMCFG_CFG_13 0x68 //unknown if used 31*d7c38808SRudolf Cornelissen #define NMCFG_CFG_14 0x6c //unknown if used 32*d7c38808SRudolf Cornelissen #define NMCFG_CFG_15 0x70 //unknown if used 33*d7c38808SRudolf Cornelissen #define NMCFG_CFG_16 0x74 //unknown if used 34*d7c38808SRudolf Cornelissen #define NMCFG_CFG_17 0x78 //unknown if used 35*d7c38808SRudolf Cornelissen #define NMCFG_CFG_18 0x7c //unknown if used 36*d7c38808SRudolf Cornelissen #define NMCFG_CFG_19 0x80 //unknown if used 37*d7c38808SRudolf Cornelissen #define NMCFG_CFG_20 0x84 //unknown if used 38*d7c38808SRudolf Cornelissen #define NMCFG_CFG_21 0x88 //unknown if used 39*d7c38808SRudolf Cornelissen #define NMCFG_CFG_22 0x8c //unknown if used 40*d7c38808SRudolf Cornelissen #define NMCFG_CFG_23 0x90 //unknown if used 41*d7c38808SRudolf Cornelissen #define NMCFG_CFG_24 0x94 //unknown if used 42*d7c38808SRudolf Cornelissen #define NMCFG_CFG_25 0x98 //unknown if used 43*d7c38808SRudolf Cornelissen #define NMCFG_CFG_26 0x9c //unknown if used 44*d7c38808SRudolf Cornelissen #define NMCFG_CFG_27 0xa0 //unknown if used 45*d7c38808SRudolf Cornelissen #define NMCFG_CFG_28 0xa4 //unknown if used 46*d7c38808SRudolf Cornelissen #define NMCFG_CFG_29 0xa8 //unknown if used 47*d7c38808SRudolf Cornelissen #define NMCFG_CFG_30 0xac //unknown if used 48*d7c38808SRudolf Cornelissen #define NMCFG_CFG_31 0xb0 //unknown if used 49*d7c38808SRudolf Cornelissen #define NMCFG_CFG_32 0xb4 //unknown if used 50*d7c38808SRudolf Cornelissen #define NMCFG_CFG_33 0xb8 //unknown if used 51*d7c38808SRudolf Cornelissen #define NMCFG_CFG_34 0xbc //unknown if used 52*d7c38808SRudolf Cornelissen #define NMCFG_CFG_35 0xc0 //unknown if used 53*d7c38808SRudolf Cornelissen #define NMCFG_CFG_36 0xc4 //unknown if used 54*d7c38808SRudolf Cornelissen #define NMCFG_CFG_37 0xc8 //unknown if used 55*d7c38808SRudolf Cornelissen #define NMCFG_CFG_38 0xcc //unknown if used 56*d7c38808SRudolf Cornelissen #define NMCFG_CFG_39 0xd0 //unknown if used 57*d7c38808SRudolf Cornelissen #define NMCFG_CFG_40 0xd4 //unknown if used 58*d7c38808SRudolf Cornelissen #define NMCFG_CFG_41 0xd8 //unknown if used 59*d7c38808SRudolf Cornelissen #define NMCFG_CFG_42 0xdc //unknown if used 60*d7c38808SRudolf Cornelissen #define NMCFG_CFG_43 0xe0 //unknown if used 61*d7c38808SRudolf Cornelissen #define NMCFG_CFG_44 0xe4 //unknown if used 62*d7c38808SRudolf Cornelissen #define NMCFG_CFG_45 0xe8 //unknown if used 63*d7c38808SRudolf Cornelissen #define NMCFG_CFG_46 0xec //unknown if used 64*d7c38808SRudolf Cornelissen #define NMCFG_CFG_47 0xf0 //unknown if used 65*d7c38808SRudolf Cornelissen #define NMCFG_CFG_48 0xf4 //unknown if used 66*d7c38808SRudolf Cornelissen #define NMCFG_CFG_49 0xf8 //unknown if used 67*d7c38808SRudolf Cornelissen #define NMCFG_CFG_50 0xfc //unknown if used 680252982aSshatty 690252982aSshatty /* neomagic ISA direct registers */ 700252982aSshatty /* VGA standard registers: */ 710252982aSshatty #define NMISA8_ATTRINDW 0x03c0 720252982aSshatty #define NMISA8_ATTRINDR 0x03c1 730252982aSshatty #define NMISA8_ATTRDATW 0x03c0 740252982aSshatty #define NMISA8_ATTRDATR 0x03c1 750252982aSshatty #define NMISA8_SEQIND 0x03c4 760252982aSshatty #define NMISA8_SEQDAT 0x03c5 770252982aSshatty #define NMISA16_SEQIND 0x03c4 780252982aSshatty #define NMISA8_CRTCIND 0x03d4 790252982aSshatty #define NMISA8_CRTCDAT 0x03d5 800252982aSshatty #define NMISA16_CRTCIND 0x03d4 810252982aSshatty #define NMISA8_GRPHIND 0x03ce 820252982aSshatty #define NMISA8_GRPHDAT 0x03cf 830252982aSshatty #define NMISA16_GRPHIND 0x03ce 840252982aSshatty 85ee2288b7Sshatty /* neomagic PCI direct registers */ 86ee2288b7Sshatty #define NM2PCI8_SEQIND 0x03c4 87ee2288b7Sshatty #define NM2PCI8_SEQDAT 0x03c5 88ee2288b7Sshatty #define NM2PCI16_SEQIND 0x03c4 89ee2288b7Sshatty #define NM2PCI8_GRPHIND 0x03ce 90ee2288b7Sshatty #define NM2PCI8_GRPHDAT 0x03cf 91ee2288b7Sshatty #define NM2PCI16_GRPHIND 0x03ce 92ee2288b7Sshatty 930252982aSshatty /* neomagic ISA GENERAL direct registers */ 940252982aSshatty /* VGA standard registers: */ 950252982aSshatty #define NMISA8_MISCW 0x03c2 960252982aSshatty #define NMISA8_MISCR 0x03cc 970252982aSshatty #define NMISA8_INSTAT1 0x03da 980252982aSshatty 990252982aSshatty /* neomagic ISA (DAC) COLOR direct registers (VGA palette RAM) */ 1000252982aSshatty /* VGA standard registers: */ 1010252982aSshatty #define NMISA8_PALMASK 0x03c6 1020252982aSshatty #define NMISA8_PALINDR 0x03c7 1030252982aSshatty #define NMISA8_PALINDW 0x03c8 1040252982aSshatty #define NMISA8_PALDATA 0x03c9 1050252982aSshatty 1060252982aSshatty /* neomagic ISA CRTC indexed registers */ 1070252982aSshatty /* VGA standard registers: */ 1080252982aSshatty #define NMCRTCX_HTOTAL 0x00 1090252982aSshatty #define NMCRTCX_HDISPE 0x01 1100252982aSshatty #define NMCRTCX_HBLANKS 0x02 1110252982aSshatty #define NMCRTCX_HBLANKE 0x03 1120252982aSshatty #define NMCRTCX_HSYNCS 0x04 1130252982aSshatty #define NMCRTCX_HSYNCE 0x05 1140252982aSshatty #define NMCRTCX_VTOTAL 0x06 1150252982aSshatty #define NMCRTCX_OVERFLOW 0x07 1160252982aSshatty #define NMCRTCX_PRROWSCN 0x08 1170252982aSshatty #define NMCRTCX_MAXSCLIN 0x09 1180252982aSshatty #define NMCRTCX_VGACURCTRL 0x0a 1190252982aSshatty #define NMCRTCX_FBSTADDH 0x0c 1200252982aSshatty #define NMCRTCX_FBSTADDL 0x0d 1210252982aSshatty #define NMCRTCX_VSYNCS 0x10 1220252982aSshatty #define NMCRTCX_VSYNCE 0x11 1230252982aSshatty #define NMCRTCX_VDISPE 0x12 1240252982aSshatty #define NMCRTCX_PITCHL 0x13 1250252982aSshatty #define NMCRTCX_VBLANKS 0x15 1260252982aSshatty #define NMCRTCX_VBLANKE 0x16 1270252982aSshatty #define NMCRTCX_MODECTL 0x17 1280252982aSshatty #define NMCRTCX_LINECOMP 0x18 1290252982aSshatty /* NeoMagic specific registers: */ 1306274eb68SRudolf Cornelissen #define NMCRTCX_PANEL_0x40 0x40 1316274eb68SRudolf Cornelissen #define NMCRTCX_PANEL_0x41 0x41 1326274eb68SRudolf Cornelissen #define NMCRTCX_PANEL_0x42 0x42 1336274eb68SRudolf Cornelissen #define NMCRTCX_PANEL_0x43 0x43 1346274eb68SRudolf Cornelissen #define NMCRTCX_PANEL_0x44 0x44 1356274eb68SRudolf Cornelissen #define NMCRTCX_PANEL_0x45 0x45 1366274eb68SRudolf Cornelissen #define NMCRTCX_PANEL_0x46 0x46 1376274eb68SRudolf Cornelissen #define NMCRTCX_PANEL_0x47 0x47 1386274eb68SRudolf Cornelissen #define NMCRTCX_PANEL_0x48 0x48 1396274eb68SRudolf Cornelissen #define NMCRTCX_PANEL_0x49 0x49 1406274eb68SRudolf Cornelissen #define NMCRTCX_PANEL_0x4a 0x4a 1416274eb68SRudolf Cornelissen #define NMCRTCX_PANEL_0x4b 0x4b 1426274eb68SRudolf Cornelissen #define NMCRTCX_PANEL_0x4c 0x4c 1436274eb68SRudolf Cornelissen #define NMCRTCX_PANEL_0x4d 0x4d 1446274eb68SRudolf Cornelissen #define NMCRTCX_PANEL_0x4e 0x4e 1456274eb68SRudolf Cornelissen #define NMCRTCX_PANEL_0x4f 0x4f 1466274eb68SRudolf Cornelissen #define NMCRTCX_PANEL_0x50 0x50 /* >= NM2090 */ 1476274eb68SRudolf Cornelissen #define NMCRTCX_PANEL_0x51 0x51 /* >= NM2090 */ 1486274eb68SRudolf Cornelissen #define NMCRTCX_PANEL_0x52 0x52 /* >= NM2090 */ 1496274eb68SRudolf Cornelissen #define NMCRTCX_PANEL_0x53 0x53 /* >= NM2090 */ 1506274eb68SRudolf Cornelissen #define NMCRTCX_PANEL_0x54 0x54 /* >= NM2090 */ 1516274eb68SRudolf Cornelissen #define NMCRTCX_PANEL_0x55 0x55 /* >= NM2090 */ 1526274eb68SRudolf Cornelissen #define NMCRTCX_PANEL_0x56 0x56 /* >= NM2090 */ 1536274eb68SRudolf Cornelissen #define NMCRTCX_PANEL_0x57 0x57 /* >= NM2090 */ 1546274eb68SRudolf Cornelissen #define NMCRTCX_PANEL_0x58 0x58 /* >= NM2090 */ 1556274eb68SRudolf Cornelissen #define NMCRTCX_PANEL_0x59 0x59 /* >= NM2090 */ 1566274eb68SRudolf Cornelissen #define NMCRTCX_PANEL_0x60 0x60 /* >= NM2097(?) */ 1576274eb68SRudolf Cornelissen #define NMCRTCX_PANEL_0x61 0x61 /* >= NM2097(?) */ 1586274eb68SRudolf Cornelissen #define NMCRTCX_PANEL_0x62 0x62 /* >= NM2097(?) */ 1596274eb68SRudolf Cornelissen #define NMCRTCX_PANEL_0x63 0x63 /* >= NM2097(?) */ 1606274eb68SRudolf Cornelissen #define NMCRTCX_PANEL_0x64 0x64 /* >= NM2097(?) */ 1610252982aSshatty #define NMCRTCX_VEXT 0x70 /* >= NM2200 */ 1620252982aSshatty 1630252982aSshatty /* neomagic ISA SEQUENCER indexed registers */ 1640252982aSshatty /* VGA standard registers: */ 1650252982aSshatty #define NMSEQX_RESET 0x00 1660252982aSshatty #define NMSEQX_CLKMODE 0x01 16777354258SRudolf Cornelissen #define NMSEQX_MAPMASK 0x02 1680252982aSshatty #define NMSEQX_MEMMODE 0x04 169ee2288b7Sshatty /* NeoMagic BES registers: (> NM2070) (accessible via mapped I/O: >= NM2097) */ 170ee2288b7Sshatty #define NMSEQX_BESCTRL2 0x08 171ee2288b7Sshatty #define NMSEQX_0x09 0x09 //?? 172630b1126SRudolf Cornelissen #define NMSEQX_ZVCAP_DSCAL 0x0a 173ee2288b7Sshatty #define NMSEQX_BUF2ORGL 0x0c 174ee2288b7Sshatty #define NMSEQX_BUF2ORGM 0x0d 175ee2288b7Sshatty #define NMSEQX_BUF2ORGH 0x0e 176630b1126SRudolf Cornelissen #define NMSEQX_VD2COORD1L 0x14 /* >= NM2200(?) */ 177630b1126SRudolf Cornelissen #define NMSEQX_VD2COORD2L 0x15 /* >= NM2200(?) */ 178630b1126SRudolf Cornelissen #define NMSEQX_VD2COORD21H 0x16 /* >= NM2200(?) */ 179630b1126SRudolf Cornelissen #define NMSEQX_HD2COORD1L 0x17 /* >= NM2200(?) */ 180630b1126SRudolf Cornelissen #define NMSEQX_HD2COORD2L 0x18 /* >= NM2200(?) */ 181630b1126SRudolf Cornelissen #define NMSEQX_HD2COORD21H 0x19 /* >= NM2200(?) */ 182ee2288b7Sshatty #define NMSEQX_BUF2PITCHL 0x1a 183ee2288b7Sshatty #define NMSEQX_BUF2PITCHH 0x1b 184ee2288b7Sshatty #define NMSEQX_0x1c 0x1c //?? 185ee2288b7Sshatty #define NMSEQX_0x1d 0x1d //?? 186ee2288b7Sshatty #define NMSEQX_0x1e 0x1e //?? 187ee2288b7Sshatty #define NMSEQX_0x1f 0x1f //?? 1880252982aSshatty 1890252982aSshatty /* neomagic ISA ATTRIBUTE indexed registers */ 1900252982aSshatty /* VGA standard registers: */ 1910252982aSshatty #define NMATBX_MODECTL 0x10 1920252982aSshatty #define NMATBX_OSCANCOLOR 0x11 1930252982aSshatty #define NMATBX_COLPLANE_EN 0x12 1940252982aSshatty #define NMATBX_HORPIXPAN 0x13 1950252982aSshatty #define NMATBX_COLSEL 0x14 19677354258SRudolf Cornelissen #define NMATBX_0x16 0x16 1970252982aSshatty 1980252982aSshatty /* neomagic ISA GRAPHICS indexed registers */ 1990252982aSshatty /* VGA standard registers: */ 2000252982aSshatty #define NMGRPHX_ENSETRESET 0x01 2010252982aSshatty #define NMGRPHX_DATAROTATE 0x03 2020252982aSshatty #define NMGRPHX_READMAPSEL 0x04 2030252982aSshatty #define NMGRPHX_MODE 0x05 2040252982aSshatty #define NMGRPHX_MISC 0x06 2050252982aSshatty #define NMGRPHX_BITMASK 0x08 2060252982aSshatty /* NeoMagic specific registers: */ 2070252982aSshatty #define NMGRPHX_GRPHXLOCK 0x09 2080252982aSshatty #define NMGRPHX_GENLOCK 0x0a 2090252982aSshatty #define NMGRPHX_FBSTADDE 0x0e 21077354258SRudolf Cornelissen #define NMGRPHX_CRTC_PITCHE 0x0f /* > NM2070 */ 21177354258SRudolf Cornelissen #define NMGRPHX_IFACECTRL1 0x10 21277354258SRudolf Cornelissen #define NMGRPHX_IFACECTRL2 0x11 21377354258SRudolf Cornelissen #define NMGRPHX_0x15 0x15 2142e60e96eSRudolf Cornelissen #define NMGRPHX_ACT_CLK_SAV 0x19 /* >= NM2200? auto-pwr-save.. (b2-0) */ 2150252982aSshatty #define NMGRPHX_PANELCTRL1 0x20 2160252982aSshatty #define NMGRPHX_PANELTYPE 0x21 2170252982aSshatty #define NMGRPHX_PANELCTRL2 0x25 2180252982aSshatty #define NMGRPHX_PANELVCENT1 0x28 2190252982aSshatty #define NMGRPHX_PANELVCENT2 0x29 2200252982aSshatty #define NMGRPHX_PANELVCENT3 0x2a 2210252982aSshatty #define NMGRPHX_PANELCTRL3 0x30 /* > NM2070 */ 2220252982aSshatty #define NMGRPHX_PANELVCENT4 0x32 /* > NM2070 */ 2230252982aSshatty #define NMGRPHX_PANELHCENT1 0x33 /* > NM2070 */ 2240252982aSshatty #define NMGRPHX_PANELHCENT2 0x34 /* > NM2070 */ 2250252982aSshatty #define NMGRPHX_PANELHCENT3 0x35 /* > NM2070 */ 2260252982aSshatty #define NMGRPHX_PANELHCENT4 0x36 /* >= NM2160 */ 2270252982aSshatty #define NMGRPHX_PANELVCENT5 0x37 /* >= NM2200 */ 2280252982aSshatty #define NMGRPHX_PANELHCENT5 0x38 /* >= NM2200 */ 2290252982aSshatty #define NMGRPHX_CURCTRL 0x82 2300252982aSshatty #define NMGRPHX_COLDEPTH 0x90 231b6e8c7e8SRudolf Cornelissen /* mem or core PLL register??? */ 232b6e8c7e8SRudolf Cornelissen #define NMGRPHX_SPEED 0x93 2330252982aSshatty /* (NeoMagic pixelPLL set C registers) */ 2340252982aSshatty #define NMGRPHX_PLLC_NH 0x8f /* >= NM2200 */ 235b6e8c7e8SRudolf Cornelissen #define NMGRPHX_PLLC_NL 0x9b 2360252982aSshatty #define NMGRPHX_PLLC_M 0x9f 237ee2288b7Sshatty /* NeoMagic BES registers: (> NM2070) (accessible via mapped I/O: >= NM2097) */ 238ee2288b7Sshatty #define NMGRPHX_BESCTRL1 0xb0 239630b1126SRudolf Cornelissen #define NMGRPHX_HD1COORD21H 0xb1 240630b1126SRudolf Cornelissen #define NMGRPHX_HD1COORD1L 0xb2 241630b1126SRudolf Cornelissen #define NMGRPHX_HD1COORD2L 0xb3 242630b1126SRudolf Cornelissen #define NMGRPHX_VD1COORD21H 0xb4 243630b1126SRudolf Cornelissen #define NMGRPHX_VD1COORD1L 0xb5 244630b1126SRudolf Cornelissen #define NMGRPHX_VD1COORD2L 0xb6 245ee2288b7Sshatty #define NMGRPHX_BUF1ORGH 0xb7 246ee2288b7Sshatty #define NMGRPHX_BUF1ORGM 0xb8 247ee2288b7Sshatty #define NMGRPHX_BUF1ORGL 0xb9 248ee2288b7Sshatty #define NMGRPHX_BUF1PITCHH 0xba 249ee2288b7Sshatty #define NMGRPHX_BUF1PITCHL 0xbb 250ee2288b7Sshatty #define NMGRPHX_0xbc 0xbc //?? 251ee2288b7Sshatty #define NMGRPHX_0xbd 0xbd //?? 252ee2288b7Sshatty #define NMGRPHX_0xbe 0xbe //?? 253ee2288b7Sshatty #define NMGRPHX_0xbf 0xbf //?? 254ee2288b7Sshatty #define NMGRPHX_XSCALEH 0xc0 255ee2288b7Sshatty #define NMGRPHX_XSCALEL 0xc1 256ee2288b7Sshatty #define NMGRPHX_YSCALEH 0xc2 257ee2288b7Sshatty #define NMGRPHX_YSCALEL 0xc3 258ee2288b7Sshatty #define NMGRPHX_BRIGHTNESS 0xc4 259ee2288b7Sshatty #define NMGRPHX_COLKEY_R 0xc5 260ee2288b7Sshatty #define NMGRPHX_COLKEY_G 0xc6 261ee2288b7Sshatty #define NMGRPHX_COLKEY_B 0xc7 2620252982aSshatty 2630252982aSshatty /* NeoMagic specific PCI cursor registers < NM2200 */ 2640252982aSshatty #define NMCR1_CURCTRL 0x0100 2650252982aSshatty #define NMCR1_CURX 0x0104 2660252982aSshatty #define NMCR1_CURY 0x0108 2670252982aSshatty #define NMCR1_CURBGCOLOR 0x010c 2680252982aSshatty #define NMCR1_CURFGCOLOR 0x0110 2690252982aSshatty #define NMCR1_CURADDRESS 0x0114 2700252982aSshatty /* NeoMagic specific PCI cursor registers >= NM2200 */ 2710252982aSshatty #define NMCR1_22CURCTRL 0x1000 2720252982aSshatty #define NMCR1_22CURX 0x1004 2730252982aSshatty #define NMCR1_22CURY 0x1008 2740252982aSshatty #define NMCR1_22CURBGCOLOR 0x100c 2750252982aSshatty #define NMCR1_22CURFGCOLOR 0x1010 2760252982aSshatty #define NMCR1_22CURADDRESS 0x1014 2770252982aSshatty 2783f618e4cSRudolf Cornelissen /* NeoMagic PCI acceleration registers */ 279af6e28e5SRudolf Cornelissen /* all cards, but some registers only on 2090 and later; and some on 2200 and later */ 2803f618e4cSRudolf Cornelissen #define NMACC_STATUS 0x0000 28188aa1acdSRudolf Cornelissen #define NMACC_CONTROL 0x0004 282b350e3f1SRudolf Cornelissen #define NMACC_FGCOLOR 0x000c 283630b1126SRudolf Cornelissen #define NMACC_2200_SRC_PITCH 0x0014 284d401e5beSRudolf Cornelissen #define NMACC_2090_CLIPLT 0x0018 285d401e5beSRudolf Cornelissen #define NMACC_2090_CLIPRB 0x001c 2863f618e4cSRudolf Cornelissen #define NMACC_SRCSTARTOFF 0x0024 287d401e5beSRudolf Cornelissen #define NMACC_2090_DSTSTARTOFF 0x002c 288d401e5beSRudolf Cornelissen #define NMACC_2090_XYEXT 0x0030 289d401e5beSRudolf Cornelissen /* NM2070 only */ 290d401e5beSRudolf Cornelissen #define NMACC_2070_PLANEMASK 0x0014 291d401e5beSRudolf Cornelissen #define NMACC_2070_XYEXT 0x0018 292d401e5beSRudolf Cornelissen #define NMACC_2070_SRCPITCH 0x001c 293d401e5beSRudolf Cornelissen #define NMACC_2070_SRCBITOFF 0x0020 294d401e5beSRudolf Cornelissen #define NMACC_2070_DSTPITCH 0x0028 295d401e5beSRudolf Cornelissen #define NMACC_2070_DSTBITOFF 0x002c 296d401e5beSRudolf Cornelissen #define NMACC_2070_DSTSTARTOFF 0x0030 2973f618e4cSRudolf Cornelissen 2980252982aSshatty 2990252982aSshatty /* Macros for convenient accesses to the NM chips */ 3000252982aSshatty 301ee2288b7Sshatty /* primary PCI register area */ 3020252982aSshatty #define NM_REG8(r_) ((vuint8 *)regs)[(r_)] 303ee2288b7Sshatty #define NM_REG16(r_) ((vuint16 *)regs)[(r_) >> 1] 3040252982aSshatty #define NM_REG32(r_) ((vuint32 *)regs)[(r_) >> 2] 305ee2288b7Sshatty /* secondary PCI register area */ 306ee2288b7Sshatty #define NM_2REG8(r_) ((vuint8 *)regs2)[(r_)] 307ee2288b7Sshatty #define NM_2REG16(r_) ((vuint16 *)regs2)[(r_) >> 1] 308ee2288b7Sshatty #define NM_2REG32(r_) ((vuint32 *)regs2)[(r_) >> 2] 3090252982aSshatty 3100252982aSshatty /* read and write to PCI config space */ 311a5130410SRudolf Cornelissen #define CFGR(A) (nm_pci_access.offset=NMCFG_##A, ioctl(fd,NM_GET_PCI, &nm_pci_access,sizeof(nm_pci_access)), nm_pci_access.value) 312a5130410SRudolf Cornelissen #define CFGW(A,B) (nm_pci_access.offset=NMCFG_##A, nm_pci_access.value = B, ioctl(fd,NM_SET_PCI,&nm_pci_access,sizeof(nm_pci_access))) 3130252982aSshatty 3143f618e4cSRudolf Cornelissen /* read and write from acceleration engine */ 3150252982aSshatty #define ACCR(A) (NM_REG32(NMACC_##A)) 3163f618e4cSRudolf Cornelissen #define ACCW(A,B) (NM_REG32(NMACC_##A) = (B)) 3170252982aSshatty 3180252982aSshatty /* read and write from first CRTC (mapped) */ 3190252982aSshatty #define CR1R(A) (NM_REG32(NMCR1_##A)) 3200252982aSshatty #define CR1W(A,B) (NM_REG32(NMCR1_##A) = (B)) 3210252982aSshatty 3220252982aSshatty /* read and write from ISA I/O space */ 323a5130410SRudolf Cornelissen #define ISAWB(A,B)(nm_isa_access.adress=NMISA8_##A, nm_isa_access.data = (uint8)B, nm_isa_access.size = 1, ioctl(fd,NM_ISA_OUT, &nm_isa_access,sizeof(nm_isa_access))) 324a5130410SRudolf Cornelissen #define ISAWW(A,B)(nm_isa_access.adress=NMISA16_##A, nm_isa_access.data = B, nm_isa_access.size = 2, ioctl(fd,NM_ISA_OUT, &nm_isa_access,sizeof(nm_isa_access))) 325a5130410SRudolf Cornelissen #define ISARB(A) (nm_isa_access.adress=NMISA8_##A, ioctl(fd,NM_ISA_IN, &nm_isa_access,sizeof(nm_isa_access)), (uint8)nm_isa_access.data) 326a5130410SRudolf Cornelissen #define ISARW(A) (nm_isa_access.adress=NMISA16_##A, ioctl(fd,NM_ISA_IN, &nm_isa_access,sizeof(nm_isa_access)), nm_isa_access.data) 3270252982aSshatty 3280252982aSshatty /* read and write from ISA CRTC indexed registers */ 3290252982aSshatty #define ISACRTCW(A,B)(ISAWW(CRTCIND, ((NMCRTCX_##A) | ((B) << 8)))) 3300252982aSshatty #define ISACRTCR(A) (ISAWB(CRTCIND, (NMCRTCX_##A)), ISARB(CRTCDAT)) 3310252982aSshatty 3320252982aSshatty /* read and write from ISA GRAPHICS indexed registers */ 3330252982aSshatty #define ISAGRPHW(A,B)(ISAWW(GRPHIND, ((NMGRPHX_##A) | ((B) << 8)))) 3340252982aSshatty #define ISAGRPHR(A) (ISAWB(GRPHIND, (NMGRPHX_##A)), ISARB(GRPHDAT)) 3350252982aSshatty 336ee2288b7Sshatty /* read and write from PCI GRAPHICS indexed registers (>= NM2097) */ 337ee2288b7Sshatty #define PCIGRPHW(A,B)(NM_2REG16(NM2PCI16_GRPHIND) = ((NMGRPHX_##A) | ((B) << 8))) 338ee2288b7Sshatty #define PCIGRPHR(A) (NM_2REG8(NM2PCI8_GRPHIND) = (NMGRPHX_##A), NM_2REG8(NM2PCI8_GRPHDAT)) 339ee2288b7Sshatty 3400252982aSshatty /* read and write from ISA SEQUENCER indexed registers */ 3410252982aSshatty #define ISASEQW(A,B)(ISAWW(SEQIND, ((NMSEQX_##A) | ((B) << 8)))) 3420252982aSshatty #define ISASEQR(A) (ISAWB(SEQIND, (NMSEQX_##A)), ISARB(SEQDAT)) 3430252982aSshatty 344ee2288b7Sshatty /* read and write from PCI SEQUENCER indexed registers (>= NM2097) */ 345ee2288b7Sshatty #define PCISEQW(A,B)(NM_2REG16(NM2PCI16_SEQIND) = ((NMSEQX_##A) | ((B) << 8))) 346ee2288b7Sshatty #define PCISEQR(A) (NM_2REG8(NM2PCI8_SEQIND) = (NMSEQX_##A), NM_2REG8(NM2PCI8_SEQDAT)) 347ee2288b7Sshatty 3480252982aSshatty /* read and write from ISA ATTRIBUTE indexed registers */ 3497d2bb07eSshatty #define ISAATBW(A,B)((void)ISARB(INSTAT1), ISAWB(ATTRINDW, ((NMATBX_##A) | 0x20)), ISAWB(ATTRDATW, (B))) 3507d2bb07eSshatty #define ISAATBR(A) ((void)ISARB(INSTAT1), ISAWB(ATTRINDW, ((NMATBX_##A) | 0x20)), ISARB(ATTRDATR)) 351