1 /* 2 Copyright 1999, Be Incorporated. All Rights Reserved. 3 This file may be used under the terms of the Be Sample Code License. 4 5 Other authors: 6 Mark Watson; 7 Apsed; 8 Rudolf Cornelissen 10/2002-1/2006. 9 */ 10 11 #ifndef DRIVERINTERFACE_H 12 #define DRIVERINTERFACE_H 13 14 #include <Accelerant.h> 15 #include "video_overlay.h" 16 #include <Drivers.h> 17 #include <PCI.h> 18 #include <OS.h> 19 20 #define DRIVER_PREFIX "mga" // apsed 21 #define DEVICE_FORMAT "%04X_%04X_%02X%02X%02X" // apsed 22 23 /* 24 Internal driver state (also for sharing info between driver and accelerant) 25 */ 26 #if defined(__cplusplus) 27 extern "C" { 28 #endif 29 30 typedef struct { 31 sem_id sem; 32 int32 ben; 33 } benaphore; 34 35 #define INIT_BEN(x) x.sem = create_sem(0, "G400 "#x" benaphore"); x.ben = 0; 36 #define AQUIRE_BEN(x) if((atomic_add(&(x.ben), 1)) >= 1) acquire_sem(x.sem); 37 #define RELEASE_BEN(x) if((atomic_add(&(x.ben), -1)) > 1) release_sem(x.sem); 38 #define DELETE_BEN(x) delete_sem(x.sem); 39 40 41 #define GX00_PRIVATE_DATA_MAGIC 0x0009 /* a private driver rev, of sorts */ 42 43 /*dualhead extensions to flags*/ 44 #define DUALHEAD_OFF (0<<6) 45 #define DUALHEAD_CLONE (1<<6) 46 #define DUALHEAD_ON (2<<6) 47 #define DUALHEAD_SWITCH (3<<6) 48 #define DUALHEAD_BITS (3<<6) 49 #define DUALHEAD_CAPABLE (1<<8) 50 #define TV_BITS (3<<9) 51 #define TV_MON (0<<9 52 #define TV_PAL (1<<9) 53 #define TV_NTSC (2<<9) 54 #define TV_CAPABLE (1<<11) 55 #define TV_VIDEO (1<<12) 56 #define TV_PRIMARY (1<<13) 57 58 #define SKD_MOVE_CURSOR 0x00000001 59 #define SKD_PROGRAM_CLUT 0x00000002 60 #define SKD_SET_START_ADDR 0x00000004 61 #define SKD_SET_CURSOR 0x00000008 62 #define SKD_HANDLER_INSTALLED 0x80000000 63 64 enum { 65 GX00_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1, 66 GX00_GET_PCI, 67 GX00_SET_PCI, 68 GX00_DEVICE_NAME, 69 GX00_RUN_INTERRUPTS 70 }; 71 72 /* max. number of overlay buffers */ 73 #define MAXBUFFERS 3 74 /* max. pixelclock speed the BES supports */ 75 #define BESMAXSPEED 135000 76 77 /* internal used info on overlay buffers */ 78 typedef struct 79 { 80 uint16 slopspace; 81 uint32 size; 82 } int_buf_info; 83 84 typedef struct settings { // apsed, see comments in mga.settings 85 // for driver 86 char accelerant[B_FILE_NAME_LENGTH]; 87 char primary[B_FILE_NAME_LENGTH]; 88 bool dumprom; 89 // for accelerant 90 uint32 logmask; 91 uint32 memory; 92 bool usebios; 93 bool hardcursor; 94 bool greensync; 95 } settings; 96 97 /*shared info*/ 98 typedef struct { 99 /*a few ID things*/ 100 uint16 vendor_id; /* PCI vendor ID, from pci_info */ 101 uint16 device_id; /* PCI device ID, from pci_info */ 102 uint8 revision; /* PCI device revsion, from pci_info */ 103 uint8 bus; /* PCI bus number, from pci_info */ 104 uint8 device; /* PCI device number on bus, from pci_info */ 105 uint8 function; /* PCI function number in device, from pci_info */ 106 107 /* bug workaround for 4.5.0 */ 108 uint32 use_clone_bugfix; /*for 4.5.0, cloning of physical memory does not work*/ 109 uint32 * clone_bugfix_regs; 110 111 /*memory mappings*/ 112 area_id regs_area; /* Kernel's area_id for the memory mapped registers. 113 It will be cloned into the accelerant's address 114 space. */ 115 116 area_id fb_area; /* Frame buffer's area_id. The addresses are shared with all teams. */ 117 area_id pseudo_dma_area; /* Pseudo dma area_id. Shared by all teams. */ 118 area_id dma_buffer_area; /* Area assigned for dma*/ 119 120 void *framebuffer; /* As viewed from virtual memory */ 121 void *framebuffer_pci; /* As viewed from the PCI bus (for DMA) */ 122 123 void *pseudo_dma; /* As viewed from virtual memory */ 124 125 void *dma_buffer; /* buffer for dma*/ 126 void *dma_buffer_pci; /* buffer for dma - from PCI bus*/ 127 128 /*screenmode list*/ 129 area_id mode_area; /* Contains the list of display modes the driver supports */ 130 uint32 mode_count; /* Number of display modes in the list */ 131 132 /*flags - used by driver*/ 133 uint32 flags; 134 135 /*vblank semaphore*/ 136 sem_id vblank; /* The vertical blank semaphore. Ownership will be 137 transfered to the team opening the device first */ 138 /*cursor information*/ 139 struct { 140 uint16 hot_x; /* Cursor hot spot. The top left corner of the cursor */ 141 uint16 hot_y; /* is 0,0 */ 142 uint16 x; /* The location of the cursor hot spot on the */ 143 uint16 y; /* desktop */ 144 uint16 width; /* Width and height of the cursor shape (always 16!) */ 145 uint16 height; 146 bool is_visible; /* Is the cursor currently displayed? */ 147 } cursor; 148 149 /*colour lookup table*/ 150 uint8 color_data[3 * 256]; /* Colour lookup table - as used by DAC */ 151 152 /*more display mode stuff*/ 153 display_mode dm; /* current display mode configuration: head1 */ 154 display_mode dm2; /* current display mode configuration: head2 */ 155 uint32 dpms_flags; /* current DPMS mode */ 156 bool switched_crtcs; /* dualhead stretch and switch mode info */ 157 bool acc_mode; /* signals (non)accelerated mode */ 158 bool interlaced_tv_mode;/* signals interlaced CRTC TV output mode */ 159 160 /*frame buffer config - for BDirectScreen*/ 161 frame_buffer_config fbc; /* bytes_per_row and start of frame buffer: head1 */ 162 frame_buffer_config fbc2; /* bytes_per_row and start of frame buffer: head2 */ 163 accelerant_device_info adi; /* as returned by hook GET_ACCELERANT_DEVICE_INFO */ 164 165 /*acceleration engine*/ 166 struct { 167 uint32 count; /* last dwgsync slot used */ 168 uint32 last_idle; /* last dwgsync slot we *know* the engine was idle after */ 169 benaphore lock; /* for serializing access to the acceleration engine */ 170 uint32 src_dst; /* G100 pre SRCORG/DSTORG registers */ 171 uint8 y_lin; /* MIL1/2 adress linearisation does not always work */ 172 uint8 depth; 173 } engine; 174 175 /* card info - information gathered from PINS (and other sources) */ 176 enum 177 { // card_type in order of date of MGA chip design 178 MIL1 = 0, 179 MYST, 180 MIL2, 181 G100, 182 G200, 183 G400, 184 G400MAX, 185 G450, 186 G550 187 }; 188 struct 189 { 190 /* specialised registers for card initialisation read from MGA BIOS (pins) */ 191 192 /* general card information */ 193 uint32 card_type; /* see card_type enum above */ 194 bool int_assigned; /* card has a useable INT assigned to it */ 195 status_t pins_status; /* B_OK if read correctly, B_ERROR if faked */ 196 bool sdram; /* TRUE if SDRAM card: needed info for 2D acceleration */ 197 198 /* PINS */ 199 float f_ref; /* PLL reference-oscillator frequency (Mhz) */ 200 uint32 max_system_vco; /* graphics engine PLL VCO limits (Mhz) */ 201 uint32 min_system_vco; 202 uint32 max_pixel_vco; /* dac1 PLL VCO limits (Mhz) */ 203 uint32 min_pixel_vco; 204 uint32 max_video_vco; /* dac2, maven PLL VCO limits (Mhz) */ 205 uint32 min_video_vco; 206 uint32 std_engine_clock; /* graphics engine clock speed needed (Mhz) */ 207 uint32 std_engine_clock_dh; 208 uint32 max_dac1_clock; /* dac1 limits (Mhz) */ 209 uint32 max_dac1_clock_8; /* dac1 limits correlated to RAMspeed limits (Mhz) */ 210 uint32 max_dac1_clock_16; 211 uint32 max_dac1_clock_24; 212 uint32 max_dac1_clock_32; 213 uint32 max_dac1_clock_32dh; 214 uint32 max_dac2_clock; /* dac2 limits (Mhz) */ 215 uint32 max_dac2_clock_8; /* dac2, maven limits correlated to RAMspeed limits (Mhz) */ 216 uint32 max_dac2_clock_16; 217 uint32 max_dac2_clock_24; 218 uint32 max_dac2_clock_32; 219 uint32 max_dac2_clock_32dh; 220 bool secondary_head; /* presence of functions */ 221 bool secondary_tvout; 222 bool primary_dvi; 223 bool secondary_dvi; 224 uint32 memory_size; /* memory (Mb) */ 225 uint32 mctlwtst_reg; /* memory control waitstate register */ 226 uint32 memrdbk_reg; /* memory readback register */ 227 uint32 option_reg; /* option register */ 228 uint32 option2_reg; /* option2 register */ 229 uint32 option3_reg; /* option3 register */ 230 uint32 option4_reg; /* option4 register */ 231 uint8 v3_option2_reg; /* pins v3 option2 register, not used for G100 */ 232 uint8 v3_clk_div; /* pins v3 memory and system clock division factors */ 233 uint8 v3_mem_type; /* pins v3 memory type info */ 234 uint16 v5_mem_type; /* pins v5 memory type info */ 235 } ps; 236 237 /* mirror of the ROM (copied in driver, because may not be mapped permanently - only over fb) */ 238 uint8 rom_mirror[32768]; 239 240 /* CRTC delay -> used in timing for MAVEN, depending on which CRTC is driving it */ 241 uint8 crtc_delay; 242 243 /* MAVEN sync polarity offset from 'reset' situation: MAVEN sync polarity setup 244 * works in a serial fashion without readback or handy reset options! */ 245 uint8 maven_syncpol_offset; 246 247 /* On G450/G550 we need this info for secondary head DPMS functionality */ 248 bool crossed_conns; 249 250 /* apsed: some configuration settings from ~/config/settings/kernel/drivers/mga.settings if exists */ 251 settings settings; 252 253 struct 254 { 255 overlay_buffer myBuffer[MAXBUFFERS];/* scaler input buffers */ 256 int_buf_info myBufInfo[MAXBUFFERS]; /* extra info on scaler input buffers */ 257 overlay_token myToken; /* scaler is free/in use */ 258 benaphore lock; /* for creating buffers and aquiring overlay unit routines */ 259 /* variables needed for virtualscreens (move_overlay()): */ 260 bool active; /* true is overlay currently in use */ 261 overlay_window ow; /* current position of overlay output window */ 262 overlay_buffer ob; /* current inputbuffer in use */ 263 overlay_view my_ov; /* current corrected view in inputbuffer */ 264 uint32 h_ifactor; /* current 'unclipped' horizontal inverse scaling factor */ 265 uint32 v_ifactor; /* current 'unclipped' vertical inverse scaling factor */ 266 } overlay; 267 268 } shared_info; 269 270 /* Read or write a value in PCI configuration space */ 271 typedef struct { 272 uint32 magic; /* magic number to make sure the caller groks us */ 273 uint32 offset; /* Offset to read/write */ 274 uint32 size; /* Number of bytes to transfer */ 275 uint32 value; /* The value read or written */ 276 } gx00_get_set_pci; 277 278 /* Set some boolean condition (like enabling or disabling interrupts) */ 279 typedef struct { 280 uint32 magic; /* magic number to make sure the caller groks us */ 281 bool do_it; /* state to set */ 282 } gx00_set_bool_state; 283 284 /* Retrieve the area_id of the kernel/accelerant shared info */ 285 typedef struct { 286 uint32 magic; /* magic number to make sure the caller groks us */ 287 area_id shared_info_area; /* area_id containing the shared information */ 288 } gx00_get_private_data; 289 290 /* Retrieve the device name. Usefull for when we have a file handle, but want 291 to know the device name (like when we are cloning the accelerant) */ 292 typedef struct { 293 uint32 magic; /* magic number to make sure the caller groks us */ 294 char *name; /* The name of the device, less the /dev root */ 295 } gx00_device_name; 296 297 enum { 298 GX00_WAIT_FOR_VBLANK = (1 << 0) 299 }; 300 301 #if defined(__cplusplus) 302 } 303 #endif 304 305 306 #endif 307