1 /* 2 Copyright 1999, Be Incorporated. All Rights Reserved. 3 This file may be used under the terms of the Be Sample Code License. 4 5 Other authors: 6 Mark Watson; 7 Apsed; 8 Rudolf Cornelissen 10/2002-11/2005. 9 */ 10 11 #ifndef DRIVERINTERFACE_H 12 #define DRIVERINTERFACE_H 13 14 #include <Accelerant.h> 15 #include "video_overlay.h" 16 #include <Drivers.h> 17 #include <PCI.h> 18 #include <OS.h> 19 20 #define DRIVER_PREFIX "mga" // apsed 21 22 /* 23 Internal driver state (also for sharing info between driver and accelerant) 24 */ 25 #if defined(__cplusplus) 26 extern "C" { 27 #endif 28 29 typedef struct { 30 sem_id sem; 31 int32 ben; 32 } benaphore; 33 34 #define INIT_BEN(x) x.sem = create_sem(0, "G400 "#x" benaphore"); x.ben = 0; 35 #define AQUIRE_BEN(x) if((atomic_add(&(x.ben), 1)) >= 1) acquire_sem(x.sem); 36 #define RELEASE_BEN(x) if((atomic_add(&(x.ben), -1)) > 1) release_sem(x.sem); 37 #define DELETE_BEN(x) delete_sem(x.sem); 38 39 40 #define GX00_PRIVATE_DATA_MAGIC 0x0009 /* a private driver rev, of sorts */ 41 42 /*dualhead extensions to flags*/ 43 #define DUALHEAD_OFF (0<<6) 44 #define DUALHEAD_CLONE (1<<6) 45 #define DUALHEAD_ON (2<<6) 46 #define DUALHEAD_SWITCH (3<<6) 47 #define DUALHEAD_BITS (3<<6) 48 #define DUALHEAD_CAPABLE (1<<8) 49 #define TV_BITS (3<<9) 50 #define TV_MON (0<<9 51 #define TV_PAL (1<<9) 52 #define TV_NTSC (2<<9) 53 #define TV_CAPABLE (1<<11) 54 #define TV_VIDEO (1<<12) 55 #define TV_PRIMARY (1<<13) 56 57 #define SKD_MOVE_CURSOR 0x00000001 58 #define SKD_PROGRAM_CLUT 0x00000002 59 #define SKD_SET_START_ADDR 0x00000004 60 #define SKD_SET_CURSOR 0x00000008 61 #define SKD_HANDLER_INSTALLED 0x80000000 62 63 enum { 64 GX00_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1, 65 GX00_GET_PCI, 66 GX00_SET_PCI, 67 GX00_DEVICE_NAME, 68 GX00_RUN_INTERRUPTS 69 }; 70 71 /* max. number of overlay buffers */ 72 #define MAXBUFFERS 3 73 /* max. pixelclock speed the BES supports */ 74 #define BESMAXSPEED 135000 75 76 /* internal used info on overlay buffers */ 77 typedef struct 78 { 79 uint16 slopspace; 80 uint32 size; 81 } int_buf_info; 82 83 typedef struct settings { // apsed, see comments in mga.settings 84 // for driver 85 char accelerant[B_FILE_NAME_LENGTH]; 86 bool dumprom; 87 // for accelerant 88 uint32 logmask; 89 uint32 memory; 90 bool usebios; 91 bool hardcursor; 92 bool greensync; 93 } settings; 94 95 /*shared info*/ 96 typedef struct { 97 /*a few ID things*/ 98 uint16 vendor_id; /* PCI vendor ID, from pci_info */ 99 uint16 device_id; /* PCI device ID, from pci_info */ 100 uint8 revision; /* PCI device revsion, from pci_info */ 101 102 /* bug workaround for 4.5.0 */ 103 uint32 use_clone_bugfix; /*for 4.5.0, cloning of physical memory does not work*/ 104 uint32 * clone_bugfix_regs; 105 106 /*memory mappings*/ 107 area_id regs_area; /* Kernel's area_id for the memory mapped registers. 108 It will be cloned into the accelerant's address 109 space. */ 110 111 area_id fb_area; /* Frame buffer's area_id. The addresses are shared with all teams. */ 112 area_id pseudo_dma_area; /* Pseudo dma area_id. Shared by all teams. */ 113 area_id dma_buffer_area; /* Area assigned for dma*/ 114 115 void *framebuffer; /* As viewed from virtual memory */ 116 void *framebuffer_pci; /* As viewed from the PCI bus (for DMA) */ 117 118 void *pseudo_dma; /* As viewed from virtual memory */ 119 120 void *dma_buffer; /* buffer for dma*/ 121 void *dma_buffer_pci; /* buffer for dma - from PCI bus*/ 122 123 /*screenmode list*/ 124 area_id mode_area; /* Contains the list of display modes the driver supports */ 125 uint32 mode_count; /* Number of display modes in the list */ 126 127 /*flags - used by driver*/ 128 uint32 flags; 129 130 /*vblank semaphore*/ 131 sem_id vblank; /* The vertical blank semaphore. Ownership will be 132 transfered to the team opening the device first */ 133 /*cursor information*/ 134 struct { 135 uint16 hot_x; /* Cursor hot spot. The top left corner of the cursor */ 136 uint16 hot_y; /* is 0,0 */ 137 uint16 x; /* The location of the cursor hot spot on the */ 138 uint16 y; /* desktop */ 139 uint16 width; /* Width and height of the cursor shape (always 16!) */ 140 uint16 height; 141 bool is_visible; /* Is the cursor currently displayed? */ 142 } cursor; 143 144 /*colour lookup table*/ 145 uint8 color_data[3 * 256]; /* Colour lookup table - as used by DAC */ 146 147 /*more display mode stuff*/ 148 display_mode dm; /* current display mode configuration: head1 */ 149 display_mode dm2; /* current display mode configuration: head2 */ 150 bool switched_crtcs; /* dualhead stretch and switch mode info */ 151 bool acc_mode; /* signals (non)accelerated mode */ 152 bool interlaced_tv_mode;/* signals interlaced CRTC TV output mode */ 153 154 /*frame buffer config - for BDirectScreen*/ 155 frame_buffer_config fbc; /* bytes_per_row and start of frame buffer: head1 */ 156 frame_buffer_config fbc2; /* bytes_per_row and start of frame buffer: head2 */ 157 158 /*acceleration engine*/ 159 struct { 160 uint32 count; /* last dwgsync slot used */ 161 uint32 last_idle; /* last dwgsync slot we *know* the engine was idle after */ 162 benaphore lock; /* for serializing access to the acceleration engine */ 163 uint32 src_dst; /* G100 pre SRCORG/DSTORG registers */ 164 uint8 y_lin; /* MIL1/2 adress linearisation does not always work */ 165 uint8 depth; 166 } engine; 167 168 /* card info - information gathered from PINS (and other sources) */ 169 enum 170 { // card_type in order of date of MGA chip design 171 MIL1 = 0, 172 MYST, 173 MIL2, 174 G100, 175 G200, 176 G400, 177 G400MAX, 178 G450, 179 G550 180 }; 181 struct 182 { 183 /* specialised registers for card initialisation read from MGA BIOS (pins) */ 184 185 /* general card information */ 186 uint32 card_type; /* see card_type enum above */ 187 bool int_assigned; /* card has a useable INT assigned to it */ 188 status_t pins_status; /* B_OK if read correctly, B_ERROR if faked */ 189 bool sdram; /* TRUE if SDRAM card: needed info for 2D acceleration */ 190 191 /* PINS */ 192 float f_ref; /* PLL reference-oscillator frequency (Mhz) */ 193 uint32 max_system_vco; /* graphics engine PLL VCO limits (Mhz) */ 194 uint32 min_system_vco; 195 uint32 max_pixel_vco; /* dac1 PLL VCO limits (Mhz) */ 196 uint32 min_pixel_vco; 197 uint32 max_video_vco; /* dac2, maven PLL VCO limits (Mhz) */ 198 uint32 min_video_vco; 199 uint32 std_engine_clock; /* graphics engine clock speed needed (Mhz) */ 200 uint32 std_engine_clock_dh; 201 uint32 max_dac1_clock; /* dac1 limits (Mhz) */ 202 uint32 max_dac1_clock_8; /* dac1 limits correlated to RAMspeed limits (Mhz) */ 203 uint32 max_dac1_clock_16; 204 uint32 max_dac1_clock_24; 205 uint32 max_dac1_clock_32; 206 uint32 max_dac1_clock_32dh; 207 uint32 max_dac2_clock; /* dac2 limits (Mhz) */ 208 uint32 max_dac2_clock_8; /* dac2, maven limits correlated to RAMspeed limits (Mhz) */ 209 uint32 max_dac2_clock_16; 210 uint32 max_dac2_clock_24; 211 uint32 max_dac2_clock_32; 212 uint32 max_dac2_clock_32dh; 213 bool secondary_head; /* presence of functions */ 214 bool secondary_tvout; 215 bool primary_dvi; 216 bool secondary_dvi; 217 uint32 memory_size; /* memory (Mb) */ 218 uint32 mctlwtst_reg; /* memory control waitstate register */ 219 uint32 memrdbk_reg; /* memory readback register */ 220 uint32 option_reg; /* option register */ 221 uint32 option2_reg; /* option2 register */ 222 uint32 option3_reg; /* option3 register */ 223 uint32 option4_reg; /* option4 register */ 224 uint8 v3_option2_reg; /* pins v3 option2 register, not used for G100 */ 225 uint8 v3_clk_div; /* pins v3 memory and system clock division factors */ 226 uint8 v3_mem_type; /* pins v3 memory type info */ 227 uint16 v5_mem_type; /* pins v5 memory type info */ 228 } ps; 229 230 /* mirror of the ROM (copied in driver, because may not be mapped permanently - only over fb) */ 231 uint8 rom_mirror[32768]; 232 233 /* CRTC delay -> used in timing for MAVEN, depending on which CRTC is driving it */ 234 uint8 crtc_delay; 235 236 /* MAVEN sync polarity offset from 'reset' situation: MAVEN sync polarity setup 237 * works in a serial fashion without readback or handy reset options! */ 238 uint8 maven_syncpol_offset; 239 240 /* On G450/G550 we need this info for secondary head DPMS functionality */ 241 bool crossed_conns; 242 243 /* apsed: some configuration settings from ~/config/settings/kernel/drivers/mga.settings if exists */ 244 settings settings; 245 246 struct 247 { 248 overlay_buffer myBuffer[MAXBUFFERS];/* scaler input buffers */ 249 int_buf_info myBufInfo[MAXBUFFERS]; /* extra info on scaler input buffers */ 250 overlay_token myToken; /* scaler is free/in use */ 251 benaphore lock; /* for creating buffers and aquiring overlay unit routines */ 252 /* variables needed for virtualscreens (move_overlay()): */ 253 bool active; /* true is overlay currently in use */ 254 overlay_window ow; /* current position of overlay output window */ 255 overlay_buffer ob; /* current inputbuffer in use */ 256 overlay_view my_ov; /* current corrected view in inputbuffer */ 257 uint32 h_ifactor; /* current 'unclipped' horizontal inverse scaling factor */ 258 uint32 v_ifactor; /* current 'unclipped' vertical inverse scaling factor */ 259 } overlay; 260 261 } shared_info; 262 263 /* Read or write a value in PCI configuration space */ 264 typedef struct { 265 uint32 magic; /* magic number to make sure the caller groks us */ 266 uint32 offset; /* Offset to read/write */ 267 uint32 size; /* Number of bytes to transfer */ 268 uint32 value; /* The value read or written */ 269 } gx00_get_set_pci; 270 271 /* Set some boolean condition (like enabling or disabling interrupts) */ 272 typedef struct { 273 uint32 magic; /* magic number to make sure the caller groks us */ 274 bool do_it; /* state to set */ 275 } gx00_set_bool_state; 276 277 /* Retrieve the area_id of the kernel/accelerant shared info */ 278 typedef struct { 279 uint32 magic; /* magic number to make sure the caller groks us */ 280 area_id shared_info_area; /* area_id containing the shared information */ 281 } gx00_get_private_data; 282 283 /* Retrieve the device name. Usefull for when we have a file handle, but want 284 to know the device name (like when we are cloning the accelerant) */ 285 typedef struct { 286 uint32 magic; /* magic number to make sure the caller groks us */ 287 char *name; /* The name of the device, less the /dev root */ 288 } gx00_device_name; 289 290 enum { 291 GX00_WAIT_FOR_VBLANK = (1 << 0) 292 }; 293 294 #if defined(__cplusplus) 295 } 296 #endif 297 298 299 #endif 300