1 /* 2 Copyright 1999, Be Incorporated. All Rights Reserved. 3 This file may be used under the terms of the Be Sample Code License. 4 5 Other authors: 6 Mark Watson; 7 Apsed; 8 Rudolf Cornelissen 10/2002. 9 */ 10 11 #ifndef DRIVERINTERFACE_H 12 #define DRIVERINTERFACE_H 13 14 #include <Accelerant.h> 15 #include "video_overlay.h" 16 #include <Drivers.h> 17 #include <PCI.h> 18 #include <OS.h> 19 20 #define DRIVER_PREFIX "mga" // apsed 21 22 /* 23 Internal driver state (also for sharing info between driver and accelerant) 24 */ 25 #if defined(__cplusplus) 26 extern "C" { 27 #endif 28 29 typedef struct { 30 sem_id sem; 31 int32 ben; 32 } benaphore; 33 34 #define INIT_BEN(x) x.sem = create_sem(0, "G400 "#x" benaphore"); x.ben = 0; 35 #define AQUIRE_BEN(x) if((atomic_add(&(x.ben), 1)) >= 1) acquire_sem(x.sem); 36 #define RELEASE_BEN(x) if((atomic_add(&(x.ben), -1)) > 1) release_sem(x.sem); 37 #define DELETE_BEN(x) delete_sem(x.sem); 38 39 40 #define GX00_PRIVATE_DATA_MAGIC 0x0009 /* a private driver rev, of sorts */ 41 42 /*dualhead extensions to flags*/ 43 #define DUALHEAD_OFF (0<<6) 44 #define DUALHEAD_CLONE (1<<6) 45 #define DUALHEAD_ON (2<<6) 46 #define DUALHEAD_SWITCH (3<<6) 47 #define DUALHEAD_BITS (3<<6) 48 #define DUALHEAD_CAPABLE (1<<8) 49 #define TV_BITS (3<<9) 50 #define TV_MON (0<<9 51 #define TV_PAL (1<<9) 52 #define TV_NTSC (2<<9) 53 #define TV_CAPABLE (1<<11) 54 55 #define SKD_MOVE_CURSOR 0x00000001 56 #define SKD_PROGRAM_CLUT 0x00000002 57 #define SKD_SET_START_ADDR 0x00000004 58 #define SKD_SET_CURSOR 0x00000008 59 #define SKD_HANDLER_INSTALLED 0x80000000 60 61 enum { 62 GX00_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1, 63 GX00_GET_PCI, 64 GX00_SET_PCI, 65 GX00_DEVICE_NAME, 66 GX00_RUN_INTERRUPTS 67 }; 68 69 /* max. number of overlay buffers */ 70 #define MAXBUFFERS 3 71 /* max. pixelclock speed the BES supports */ 72 #define BESMAXSPEED 135000 73 74 /* internal used info on overlay buffers */ 75 typedef struct 76 { 77 uint16 slopspace; 78 uint32 size; 79 } int_buf_info; 80 81 typedef struct settings { // apsed, see comments in mga.settings 82 // for driver 83 char accelerant[B_FILE_NAME_LENGTH]; 84 bool dumprom; 85 // for accelerant 86 uint32 logmask; 87 uint32 memory; 88 bool usebios; 89 bool hardcursor; 90 } settings; 91 92 /*shared info*/ 93 typedef struct { 94 /*a few ID things*/ 95 uint16 vendor_id; /* PCI vendor ID, from pci_info */ 96 uint16 device_id; /* PCI device ID, from pci_info */ 97 uint8 revision; /* PCI device revsion, from pci_info */ 98 99 /* bug workaround for 4.5.0 */ 100 uint32 use_clone_bugfix; /*for 4.5.0, cloning of physical memory does not work*/ 101 uint32 * clone_bugfix_regs; 102 103 /*memory mappings*/ 104 area_id regs_area; /* Kernel's area_id for the memory mapped registers. 105 It will be cloned into the accelerant's address 106 space. */ 107 108 area_id fb_area; /* Frame buffer's area_id. The addresses are shared with all teams. */ 109 area_id pseudo_dma_area; /* Pseudo dma area_id. Shared by all teams. */ 110 area_id dma_buffer_area; /* Area assigned for dma*/ 111 112 void *framebuffer; /* As viewed from virtual memory */ 113 void *framebuffer_pci; /* As viewed from the PCI bus (for DMA) */ 114 115 void *pseudo_dma; /* As viewed from virtual memory */ 116 117 void *dma_buffer; /* buffer for dma*/ 118 void *dma_buffer_pci; /* buffer for dma - from PCI bus*/ 119 120 /*screenmode list*/ 121 area_id mode_area; /* Contains the list of display modes the driver supports */ 122 uint32 mode_count; /* Number of display modes in the list */ 123 124 /*flags - used by driver*/ 125 uint32 flags; 126 127 /*vblank semaphore*/ 128 sem_id vblank; /* The vertical blank semaphore. Ownership will be 129 transfered to the team opening the device first */ 130 /*cursor information*/ 131 struct { 132 uint16 hot_x; /* Cursor hot spot. The top left corner of the cursor */ 133 uint16 hot_y; /* is 0,0 */ 134 uint16 x; /* The location of the cursor hot spot on the */ 135 uint16 y; /* desktop */ 136 uint16 width; /* Width and height of the cursor shape (always 16!) */ 137 uint16 height; 138 bool is_visible; /* Is the cursor currently displayed? */ 139 }cursor; 140 141 /*colour lookup table*/ 142 uint8 color_data[3 * 256]; /* Colour lookup table - as used by DAC */ 143 144 /*more display mode stuff*/ 145 display_mode dm; /* current display mode configuration */ 146 147 /*frame buffer config - for BDirectScreen*/ 148 frame_buffer_config fbc; /* bytes_per_row and start of frame buffer */ 149 150 /*acceleration engine*/ 151 struct { 152 uint32 count; /* last dwgsync slot used */ 153 uint32 last_idle; /* last dwgsync slot we *know* the engine was idle after */ 154 benaphore lock; /* for serializing access to the acceleration engine */ 155 } engine; 156 157 /* card info - information gathered from PINS (and other sources) */ 158 enum 159 { // card_type in order of date of MGA chip design 160 MILL=0, 161 MYST, 162 MIL2, 163 G100, 164 G200, 165 G400, 166 G400MAX, 167 G450, 168 G550 169 }; 170 struct 171 { 172 /*specialised registers for initialisation*/ 173 //will be deleted, will be replaced by new Pins implementation: 174 //these are nolonger used by G100. 175 uint32 mem_ctl; 176 uint32 mem_type; 177 uint8 membuf; /*memory buffer type*/ 178 uint32 mem_rd; 179 uint32 mem_rfhcnt; 180 181 /*temporary extra info for G450*/ 182 //will be deleted, will be replaced by new Pins implementation: 183 uint32 option; 184 uint32 option2; 185 uint32 option4; 186 uint32 maccess; 187 188 /* general card information */ 189 uint32 card_type; /* see card_type enum above */ 190 status_t pins_status; /* B_OK if read correctly, B_ERROR if faked */ 191 bool sdram; /* TRUE if SDRAM card: needed info for 2D acceleration */ 192 193 /* newly implemented PINS: will replace most of the above.. */ 194 float f_ref; /* PLL reference-oscillator frequency (Mhz) */ 195 uint32 max_system_vco; /* graphics engine PLL VCO limits (Mhz) */ 196 uint32 min_system_vco; 197 uint32 max_pixel_vco; /* dac1 PLL VCO limits (Mhz) */ 198 uint32 min_pixel_vco; 199 uint32 max_video_vco; /* dac2, maven PLL VCO limits (Mhz) */ 200 uint32 min_video_vco; 201 uint32 std_engine_clock; /* graphics engine clock speed needed (Mhz) */ 202 uint32 std_engine_clock_dh; 203 uint32 max_dac1_clock; /* dac1 limits (Mhz) */ 204 uint32 max_dac1_clock_8; /* dac1 limits correlated to RAMspeed limits (Mhz) */ 205 uint32 max_dac1_clock_16; 206 uint32 max_dac1_clock_24; 207 uint32 max_dac1_clock_32; 208 uint32 max_dac1_clock_32dh; 209 uint32 max_dac2_clock; /* dac2 limits (Mhz) */ 210 uint32 max_dac2_clock_8; /* dac2, maven limits correlated to RAMspeed limits (Mhz) */ 211 uint32 max_dac2_clock_16; 212 uint32 max_dac2_clock_24; 213 uint32 max_dac2_clock_32; 214 uint32 max_dac2_clock_32dh; 215 bool secondary_head; /* presence of functions */ 216 bool secondary_tvout; 217 bool primary_dvi; 218 bool secondary_dvi; 219 uint32 memory_size; /* memory (Mb) */ 220 uint32 mctlwtst_reg; /* memory control waitstate register */ 221 uint32 option_reg; /* option register */ 222 uint8 v3_clk_div; /* pins v3 memory and system clock division factors */ 223 uint8 v3_mem_type; /* pins v3 memory type info */ 224 } ps; 225 226 /*mirror of the ROM (copied in driver, because may not be mapped permanently - only over fb)*/ 227 uint8 rom_mirror[32768]; 228 229 /*CRTC delay -> used in timing for MAVEN, depending on which CRTC is driving it*/ 230 uint8 crtc_delay; 231 232 /* apsed: some configuration settings from ~/config/settings/kernel/drivers/mga.settings if exists */ 233 settings settings; 234 235 struct 236 { 237 overlay_buffer myBuffer[MAXBUFFERS];/* scaler input buffers */ 238 int_buf_info myBufInfo[MAXBUFFERS]; /* extra info on scaler input buffers */ 239 overlay_token myToken; /* scaler is free/in use */ 240 benaphore lock; /* for creating buffers and aquiring overlay unit routines */ 241 } overlay; 242 243 } shared_info; 244 245 /* Read or write a value in PCI configuration space */ 246 typedef struct { 247 uint32 magic; /* magic number to make sure the caller groks us */ 248 uint32 offset; /* Offset to read/write */ 249 uint32 size; /* Number of bytes to transfer */ 250 uint32 value; /* The value read or written */ 251 } gx00_get_set_pci; 252 253 /* Set some boolean condition (like enabling or disabling interrupts) */ 254 typedef struct { 255 uint32 magic; /* magic number to make sure the caller groks us */ 256 bool do_it; /* state to set */ 257 } gx00_set_bool_state; 258 259 /* Retrieve the area_id of the kernel/accelerant shared info */ 260 typedef struct { 261 uint32 magic; /* magic number to make sure the caller groks us */ 262 area_id shared_info_area; /* area_id containing the shared information */ 263 } gx00_get_private_data; 264 265 /* Retrieve the device name. Usefull for when we have a file handle, but want 266 to know the device name (like when we are cloning the accelerant) */ 267 typedef struct { 268 uint32 magic; /* magic number to make sure the caller groks us */ 269 char *name; /* The name of the device, less the /dev root */ 270 } gx00_device_name; 271 272 enum { 273 GX00_WAIT_FOR_VBLANK = (1 << 0) 274 }; 275 276 #if defined(__cplusplus) 277 } 278 #endif 279 280 281 #endif 282