1 /* 2 Copyright 1999, Be Incorporated. All Rights Reserved. 3 This file may be used under the terms of the Be Sample Code License. 4 5 Other authors: 6 Mark Watson; 7 Apsed; 8 Rudolf Cornelissen 10/2002-12/2003. 9 */ 10 11 #ifndef DRIVERINTERFACE_H 12 #define DRIVERINTERFACE_H 13 14 #include <Accelerant.h> 15 #include "video_overlay.h" 16 #include <Drivers.h> 17 #include <PCI.h> 18 #include <OS.h> 19 20 #define DRIVER_PREFIX "mga" // apsed 21 22 /* 23 Internal driver state (also for sharing info between driver and accelerant) 24 */ 25 #if defined(__cplusplus) 26 extern "C" { 27 #endif 28 29 typedef struct { 30 sem_id sem; 31 int32 ben; 32 } benaphore; 33 34 #define INIT_BEN(x) x.sem = create_sem(0, "G400 "#x" benaphore"); x.ben = 0; 35 #define AQUIRE_BEN(x) if((atomic_add(&(x.ben), 1)) >= 1) acquire_sem(x.sem); 36 #define RELEASE_BEN(x) if((atomic_add(&(x.ben), -1)) > 1) release_sem(x.sem); 37 #define DELETE_BEN(x) delete_sem(x.sem); 38 39 40 #define GX00_PRIVATE_DATA_MAGIC 0x0009 /* a private driver rev, of sorts */ 41 42 /*dualhead extensions to flags*/ 43 #define DUALHEAD_OFF (0<<6) 44 #define DUALHEAD_CLONE (1<<6) 45 #define DUALHEAD_ON (2<<6) 46 #define DUALHEAD_SWITCH (3<<6) 47 #define DUALHEAD_BITS (3<<6) 48 #define DUALHEAD_CAPABLE (1<<8) 49 #define TV_BITS (3<<9) 50 #define TV_MON (0<<9 51 #define TV_PAL (1<<9) 52 #define TV_NTSC (2<<9) 53 #define TV_CAPABLE (1<<11) 54 #define TV_VIDEO (1<<12) 55 56 #define SKD_MOVE_CURSOR 0x00000001 57 #define SKD_PROGRAM_CLUT 0x00000002 58 #define SKD_SET_START_ADDR 0x00000004 59 #define SKD_SET_CURSOR 0x00000008 60 #define SKD_HANDLER_INSTALLED 0x80000000 61 62 enum { 63 GX00_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1, 64 GX00_GET_PCI, 65 GX00_SET_PCI, 66 GX00_DEVICE_NAME, 67 GX00_RUN_INTERRUPTS 68 }; 69 70 /* max. number of overlay buffers */ 71 #define MAXBUFFERS 3 72 /* max. pixelclock speed the BES supports */ 73 #define BESMAXSPEED 135000 74 75 /* internal used info on overlay buffers */ 76 typedef struct 77 { 78 uint16 slopspace; 79 uint32 size; 80 } int_buf_info; 81 82 typedef struct settings { // apsed, see comments in mga.settings 83 // for driver 84 char accelerant[B_FILE_NAME_LENGTH]; 85 bool dumprom; 86 // for accelerant 87 uint32 logmask; 88 uint32 memory; 89 bool usebios; 90 bool hardcursor; 91 bool greensync; 92 } settings; 93 94 /*shared info*/ 95 typedef struct { 96 /*a few ID things*/ 97 uint16 vendor_id; /* PCI vendor ID, from pci_info */ 98 uint16 device_id; /* PCI device ID, from pci_info */ 99 uint8 revision; /* PCI device revsion, from pci_info */ 100 101 /* bug workaround for 4.5.0 */ 102 uint32 use_clone_bugfix; /*for 4.5.0, cloning of physical memory does not work*/ 103 uint32 * clone_bugfix_regs; 104 105 /*memory mappings*/ 106 area_id regs_area; /* Kernel's area_id for the memory mapped registers. 107 It will be cloned into the accelerant's address 108 space. */ 109 110 area_id fb_area; /* Frame buffer's area_id. The addresses are shared with all teams. */ 111 area_id pseudo_dma_area; /* Pseudo dma area_id. Shared by all teams. */ 112 area_id dma_buffer_area; /* Area assigned for dma*/ 113 114 void *framebuffer; /* As viewed from virtual memory */ 115 void *framebuffer_pci; /* As viewed from the PCI bus (for DMA) */ 116 117 void *pseudo_dma; /* As viewed from virtual memory */ 118 119 void *dma_buffer; /* buffer for dma*/ 120 void *dma_buffer_pci; /* buffer for dma - from PCI bus*/ 121 122 /*screenmode list*/ 123 area_id mode_area; /* Contains the list of display modes the driver supports */ 124 uint32 mode_count; /* Number of display modes in the list */ 125 126 /*flags - used by driver*/ 127 uint32 flags; 128 129 /*vblank semaphore*/ 130 sem_id vblank; /* The vertical blank semaphore. Ownership will be 131 transfered to the team opening the device first */ 132 /*cursor information*/ 133 struct { 134 uint16 hot_x; /* Cursor hot spot. The top left corner of the cursor */ 135 uint16 hot_y; /* is 0,0 */ 136 uint16 x; /* The location of the cursor hot spot on the */ 137 uint16 y; /* desktop */ 138 uint16 width; /* Width and height of the cursor shape (always 16!) */ 139 uint16 height; 140 bool is_visible; /* Is the cursor currently displayed? */ 141 } cursor; 142 143 /*colour lookup table*/ 144 uint8 color_data[3 * 256]; /* Colour lookup table - as used by DAC */ 145 146 /*more display mode stuff*/ 147 display_mode dm; /* current display mode configuration: head1 */ 148 display_mode dm2; /* current display mode configuration: head2 */ 149 bool switched_crtcs; /* dualhead stretch and switch mode info */ 150 bool acc_mode; /* signals (non)accelerated mode */ 151 bool interlaced_tv_mode;/* signals interlaced CRTC TV output mode */ 152 153 /*frame buffer config - for BDirectScreen*/ 154 frame_buffer_config fbc; /* bytes_per_row and start of frame buffer: head1 */ 155 frame_buffer_config fbc2; /* bytes_per_row and start of frame buffer: head2 */ 156 157 /*acceleration engine*/ 158 struct { 159 uint32 count; /* last dwgsync slot used */ 160 uint32 last_idle; /* last dwgsync slot we *know* the engine was idle after */ 161 benaphore lock; /* for serializing access to the acceleration engine */ 162 uint32 src_dst; /* G100 pre SRCORG/DSTORG registers */ 163 uint8 y_lin; /* MIL1/2 adress linearisation does not always work */ 164 uint8 depth; 165 } engine; 166 167 /* card info - information gathered from PINS (and other sources) */ 168 enum 169 { // card_type in order of date of MGA chip design 170 MIL1 = 0, 171 MYST, 172 MIL2, 173 G100, 174 G200, 175 G400, 176 G400MAX, 177 G450, 178 G550 179 }; 180 struct 181 { 182 /* specialised registers for card initialisation read from MGA BIOS (pins) */ 183 184 /* general card information */ 185 uint32 card_type; /* see card_type enum above */ 186 status_t pins_status; /* B_OK if read correctly, B_ERROR if faked */ 187 bool sdram; /* TRUE if SDRAM card: needed info for 2D acceleration */ 188 189 /* PINS */ 190 float f_ref; /* PLL reference-oscillator frequency (Mhz) */ 191 uint32 max_system_vco; /* graphics engine PLL VCO limits (Mhz) */ 192 uint32 min_system_vco; 193 uint32 max_pixel_vco; /* dac1 PLL VCO limits (Mhz) */ 194 uint32 min_pixel_vco; 195 uint32 max_video_vco; /* dac2, maven PLL VCO limits (Mhz) */ 196 uint32 min_video_vco; 197 uint32 std_engine_clock; /* graphics engine clock speed needed (Mhz) */ 198 uint32 std_engine_clock_dh; 199 uint32 max_dac1_clock; /* dac1 limits (Mhz) */ 200 uint32 max_dac1_clock_8; /* dac1 limits correlated to RAMspeed limits (Mhz) */ 201 uint32 max_dac1_clock_16; 202 uint32 max_dac1_clock_24; 203 uint32 max_dac1_clock_32; 204 uint32 max_dac1_clock_32dh; 205 uint32 max_dac2_clock; /* dac2 limits (Mhz) */ 206 uint32 max_dac2_clock_8; /* dac2, maven limits correlated to RAMspeed limits (Mhz) */ 207 uint32 max_dac2_clock_16; 208 uint32 max_dac2_clock_24; 209 uint32 max_dac2_clock_32; 210 uint32 max_dac2_clock_32dh; 211 bool secondary_head; /* presence of functions */ 212 bool secondary_tvout; 213 bool primary_dvi; 214 bool secondary_dvi; 215 uint32 memory_size; /* memory (Mb) */ 216 uint32 mctlwtst_reg; /* memory control waitstate register */ 217 uint32 memrdbk_reg; /* memory readback register */ 218 uint32 option_reg; /* option register */ 219 uint32 option2_reg; /* option2 register */ 220 uint32 option3_reg; /* option3 register */ 221 uint32 option4_reg; /* option4 register */ 222 uint8 v3_option2_reg; /* pins v3 option2 register, not used for G100 */ 223 uint8 v3_clk_div; /* pins v3 memory and system clock division factors */ 224 uint8 v3_mem_type; /* pins v3 memory type info */ 225 uint16 v5_mem_type; /* pins v5 memory type info */ 226 } ps; 227 228 /* mirror of the ROM (copied in driver, because may not be mapped permanently - only over fb) */ 229 uint8 rom_mirror[32768]; 230 231 /* CRTC delay -> used in timing for MAVEN, depending on which CRTC is driving it */ 232 uint8 crtc_delay; 233 234 /* MAVEN sync polarity offset from 'reset' situation: MAVEN sync polarity setup 235 * works in a serial fashion without readback or handy reset options! */ 236 uint8 maven_syncpol_offset; 237 238 /* On G450/G550 we need this info for secondary head DPMS functionality */ 239 bool crossed_conns; 240 241 /* apsed: some configuration settings from ~/config/settings/kernel/drivers/mga.settings if exists */ 242 settings settings; 243 244 struct 245 { 246 overlay_buffer myBuffer[MAXBUFFERS];/* scaler input buffers */ 247 int_buf_info myBufInfo[MAXBUFFERS]; /* extra info on scaler input buffers */ 248 overlay_token myToken; /* scaler is free/in use */ 249 benaphore lock; /* for creating buffers and aquiring overlay unit routines */ 250 } overlay; 251 252 } shared_info; 253 254 /* Read or write a value in PCI configuration space */ 255 typedef struct { 256 uint32 magic; /* magic number to make sure the caller groks us */ 257 uint32 offset; /* Offset to read/write */ 258 uint32 size; /* Number of bytes to transfer */ 259 uint32 value; /* The value read or written */ 260 } gx00_get_set_pci; 261 262 /* Set some boolean condition (like enabling or disabling interrupts) */ 263 typedef struct { 264 uint32 magic; /* magic number to make sure the caller groks us */ 265 bool do_it; /* state to set */ 266 } gx00_set_bool_state; 267 268 /* Retrieve the area_id of the kernel/accelerant shared info */ 269 typedef struct { 270 uint32 magic; /* magic number to make sure the caller groks us */ 271 area_id shared_info_area; /* area_id containing the shared information */ 272 } gx00_get_private_data; 273 274 /* Retrieve the device name. Usefull for when we have a file handle, but want 275 to know the device name (like when we are cloning the accelerant) */ 276 typedef struct { 277 uint32 magic; /* magic number to make sure the caller groks us */ 278 char *name; /* The name of the device, less the /dev root */ 279 } gx00_device_name; 280 281 enum { 282 GX00_WAIT_FOR_VBLANK = (1 << 0) 283 }; 284 285 #if defined(__cplusplus) 286 } 287 #endif 288 289 290 #endif 291