1 /* 2 * Copyright 2006-2008, Haiku, Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Axel Dörfler, axeld@pinc-software.de 7 */ 8 #ifndef INTEL_EXTREME_H 9 #define INTEL_EXTREME_H 10 11 12 #include "lock.h" 13 14 #include <Accelerant.h> 15 #include <Drivers.h> 16 #include <PCI.h> 17 18 19 #define VENDOR_ID_INTEL 0x8086 20 21 #define INTEL_TYPE_FAMILY_MASK 0xf000 22 #define INTEL_TYPE_GROUP_MASK 0x0fff 23 #define INTEL_TYPE_7xx 0x1000 24 #define INTEL_TYPE_8xx 0x2000 25 #define INTEL_TYPE_9xx 0x4000 26 #define INTEL_TYPE_83x (INTEL_TYPE_8xx | 0x0001) 27 #define INTEL_TYPE_85x (INTEL_TYPE_8xx | 0x0002) 28 #define INTEL_TYPE_91x (INTEL_TYPE_9xx | 0x0010) 29 #define INTEL_TYPE_945 (INTEL_TYPE_9xx | 0x0020) 30 #define INTEL_TYPE_965 (INTEL_TYPE_9xx | 0x0030) 31 #define INTEL_TYPE_G33 (INTEL_TYPE_9xx | 0x0040) 32 33 #define DEVICE_NAME "intel_extreme" 34 #define INTEL_ACCELERANT_NAME "intel_extreme.accelerant" 35 36 // info about PLL on graphics card 37 struct pll_info { 38 uint32 reference_frequency; 39 uint32 max_frequency; 40 uint32 min_frequency; 41 uint32 divisor_register; 42 }; 43 44 struct ring_buffer { 45 struct lock lock; 46 uint32 register_base; 47 uint32 offset; 48 uint32 size; 49 uint32 position; 50 uint32 space_left; 51 uint8 *base; 52 }; 53 54 struct overlay_registers; 55 56 struct intel_shared_info { 57 area_id mode_list_area; // area containing display mode list 58 uint32 mode_count; 59 60 display_mode current_mode; 61 uint32 bytes_per_row; 62 uint32 bits_per_pixel; 63 uint32 dpms_mode; 64 65 area_id registers_area; // area of memory mapped registers 66 uint8 *status_page; 67 addr_t physical_status_page; 68 uint8 *graphics_memory; 69 addr_t physical_graphics_memory; 70 uint32 graphics_memory_size; 71 72 addr_t frame_buffer; 73 uint32 frame_buffer_offset; 74 75 struct lock accelerant_lock; 76 struct lock engine_lock; 77 78 ring_buffer primary_ring_buffer; 79 80 int32 overlay_channel_used; 81 bool overlay_active; 82 uint32 overlay_token; 83 addr_t physical_overlay_registers; 84 uint32 overlay_offset; 85 86 bool hardware_cursor_enabled; 87 sem_id vblank_sem; 88 89 uint8 *cursor_memory; 90 addr_t physical_cursor_memory; 91 uint32 cursor_buffer_offset; 92 uint32 cursor_format; 93 bool cursor_visible; 94 uint16 cursor_hot_x; 95 uint16 cursor_hot_y; 96 97 uint32 device_type; 98 char device_identifier[32]; 99 struct pll_info pll_info; 100 }; 101 102 //----------------- ioctl() interface ---------------- 103 104 // magic code for ioctls 105 #define INTEL_PRIVATE_DATA_MAGIC 'itic' 106 107 // list ioctls 108 enum { 109 INTEL_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1, 110 111 INTEL_GET_DEVICE_NAME, 112 INTEL_ALLOCATE_GRAPHICS_MEMORY, 113 INTEL_FREE_GRAPHICS_MEMORY 114 }; 115 116 // retrieve the area_id of the kernel/accelerant shared info 117 struct intel_get_private_data { 118 uint32 magic; // magic number 119 area_id shared_info_area; 120 }; 121 122 // allocate graphics memory 123 struct intel_allocate_graphics_memory { 124 uint32 magic; 125 uint32 size; 126 uint32 alignment; 127 uint32 flags; 128 uint32 buffer_base; 129 }; 130 131 // free graphics memory 132 struct intel_free_graphics_memory { 133 uint32 magic; 134 uint32 buffer_base; 135 }; 136 137 //---------------------------------------------------------- 138 // Register definitions, taken from X driver 139 140 // PCI bridge memory management 141 #define INTEL_GRAPHICS_MEMORY_CONTROL 0x52 142 #define MEMORY_CONTROL_ENABLED 0x0004 143 #define MEMORY_MASK 0x0001 144 #define STOLEN_MEMORY_MASK 0x0070 145 #define i965_GTT_MASK 0x000e 146 #define G33_GTT_MASK 0x0300 147 148 // models i830 and up 149 #define i830_LOCAL_MEMORY_ONLY 0x10 150 #define i830_STOLEN_512K 0x20 151 #define i830_STOLEN_1M 0x30 152 #define i830_STOLEN_8M 0x40 153 #define i830_FRAME_BUFFER_64M 0x01 154 #define i830_FRAME_BUFFER_128M 0x00 155 156 // models i855 and up 157 #define i855_STOLEN_MEMORY_1M 0x10 158 #define i855_STOLEN_MEMORY_4M 0x20 159 #define i855_STOLEN_MEMORY_8M 0x30 160 #define i855_STOLEN_MEMORY_16M 0x40 161 #define i855_STOLEN_MEMORY_32M 0x50 162 #define i855_STOLEN_MEMORY_48M 0x60 163 #define i855_STOLEN_MEMORY_64M 0x70 164 #define i855_STOLEN_MEMORY_128M 0x80 165 #define i855_STOLEN_MEMORY_256M 0x90 166 167 // graphics page translation table 168 #define INTEL_PAGE_TABLE_CONTROL 0x02020 169 #define PAGE_TABLE_ENABLED 0x00000001 170 #define INTEL_PAGE_TABLE_ERROR 0x02024 171 #define INTEL_HARDWARE_STATUS_PAGE 0x02080 172 #define i915_GTT_BASE 0x1c 173 #define i830_GTT_BASE 0x10000 // (- 0x2ffff) 174 #define i830_GTT_SIZE 0x20000 175 #define i965_GTT_BASE 0x80000 // (- 0xfffff) 176 #define i965_GTT_SIZE 0x80000 177 #define i965_GTT_128K (2 << 1) 178 #define i965_GTT_256K (1 << 1) 179 #define i965_GTT_512K (0 << 1) 180 #define G33_GTT_1M (1 << 8) 181 #define G33_GTT_2M (2 << 8) 182 #define GTT_ENTRY_VALID 0x01 183 #define GTT_ENTRY_LOCAL_MEMORY 0x02 184 #define GTT_PAGE_SHIFT 12 185 186 // interrupts 187 #define INTEL_INTERRUPT_ENABLED 0x020a0 188 #define INTEL_INTERRUPT_IDENTITY 0x020a4 189 #define INTEL_INTERRUPT_MASK 0x020a8 190 #define INTEL_INTERRUPT_STATUS 0x020ac 191 #define INTERRUPT_VBLANK (1 << 7) 192 193 // ring buffer 194 #define INTEL_PRIMARY_RING_BUFFER 0x02030 195 #define INTEL_SECONDARY_RING_BUFFER_0 0x02100 196 #define INTEL_SECONDARY_RING_BUFFER_1 0x02110 197 // offsets for the ring buffer base registers above 198 #define RING_BUFFER_TAIL 0x0 199 #define RING_BUFFER_HEAD 0x4 200 #define RING_BUFFER_START 0x8 201 #define RING_BUFFER_CONTROL 0xc 202 #define INTEL_RING_BUFFER_SIZE_MASK 0x001ff000 203 #define INTEL_RING_BUFFER_HEAD_MASK 0x001ffffc 204 #define INTEL_RING_BUFFER_ENABLED 1 205 206 // display A 207 #define INTEL_DISPLAY_A_HTOTAL 0x60000 208 #define INTEL_DISPLAY_A_HBLANK 0x60004 209 #define INTEL_DISPLAY_A_HSYNC 0x60008 210 #define INTEL_DISPLAY_A_VTOTAL 0x6000c 211 #define INTEL_DISPLAY_A_VBLANK 0x60010 212 #define INTEL_DISPLAY_A_VSYNC 0x60014 213 #define INTEL_DISPLAY_A_IMAGE_SIZE 0x6001c 214 215 #define INTEL_DISPLAY_A_CONTROL 0x70180 216 #define INTEL_DISPLAY_A_BASE 0x70184 217 #define INTEL_DISPLAY_A_BYTES_PER_ROW 0x70188 218 #define INTEL_DISPLAY_A_SURFACE 0x7019c // i965 and up only 219 #define DISPLAY_CONTROL_ENABLED (1UL << 31) 220 #define DISPLAY_CONTROL_GAMMA (1UL << 30) 221 #define DISPLAY_CONTROL_COLOR_MASK (0x0fUL << 26) 222 #define DISPLAY_CONTROL_CMAP8 (2UL << 26) 223 #define DISPLAY_CONTROL_RGB15 (4UL << 26) 224 #define DISPLAY_CONTROL_RGB16 (5UL << 26) 225 #define DISPLAY_CONTROL_RGB32 (6UL << 26) 226 227 #define INTEL_VGA_DISPLAY_CONTROL 0x71400 228 #define VGA_DISPLAY_DISABLED (1UL << 31) 229 230 #define INTEL_DISPLAY_A_PALETTE 0x0a000 231 232 #define INTEL_DISPLAY_A_PIPE_CONTROL 0x70008 233 #define DISPLAY_PIPE_ENABLED (1UL << 31) 234 #define INTEL_DISPLAY_A_PIPE_STATUS 0x70024 235 #define DISPLAY_PIPE_VBLANK_ENABLED (1UL << 17) 236 #define DISPLAY_PIPE_VBLANK_STATUS (1UL << 1) 237 238 #define INTEL_DISPLAY_A_PLL 0x06014 239 #define INTEL_DISPLAY_A_PLL_DIVISOR_0 0x06040 240 #define INTEL_DISPLAY_A_PLL_DIVISOR_1 0x06044 241 #define DISPLAY_PLL_ENABLED (1UL << 31) 242 #define DISPLAY_PLL_2X_CLOCK (1UL << 30) 243 #define DISPLAY_PLL_SYNC_LOCK_ENABLED (1UL << 29) 244 #define DISPLAY_PLL_NO_VGA_CONTROL (1UL << 28) 245 #define DISPLAY_PLL_MODE_ANALOG (1UL << 26) 246 #define DISPLAY_PLL_DIVIDE_HIGH (1UL << 24) 247 #define DISPLAY_PLL_DIVIDE_4X (1UL << 23) 248 #define DISPLAY_PLL_POST1_DIVIDE_2 (1UL << 21) 249 #define DISPLAY_PLL_POST1_DIVISOR_MASK 0x001f0000 250 #define DISPLAY_PLL_9xx_POST1_DIVISOR_MASK 0x00ff0000 251 #define DISPLAY_PLL_POST1_DIVISOR_SHIFT 16 252 #define DISPLAY_PLL_DIVISOR_1 (1UL << 8) 253 #define DISPLAY_PLL_N_DIVISOR_MASK 0x001f0000 254 #define DISPLAY_PLL_M1_DIVISOR_MASK 0x00001f00 255 #define DISPLAY_PLL_M2_DIVISOR_MASK 0x0000001f 256 #define DISPLAY_PLL_N_DIVISOR_SHIFT 16 257 #define DISPLAY_PLL_M1_DIVISOR_SHIFT 8 258 #define DISPLAY_PLL_M2_DIVISOR_SHIFT 0 259 #define DISPLAY_PLL_PULSE_PHASE_SHIFT 9 260 261 #define INTEL_DISPLAY_A_ANALOG_PORT 0x61100 262 #define DISPLAY_MONITOR_PORT_ENABLED (1UL << 31) 263 #define DISPLAY_MONITOR_PIPE_B (1UL << 30) 264 #define DISPLAY_MONITOR_VGA_POLARITY (1UL << 15) 265 #define DISPLAY_MONITOR_MODE_MASK (3UL << 10) 266 #define DISPLAY_MONITOR_ON 0 267 #define DISPLAY_MONITOR_SUSPEND (1UL << 10) 268 #define DISPLAY_MONITOR_STAND_BY (2UL << 10) 269 #define DISPLAY_MONITOR_OFF (3UL << 10) 270 #define DISPLAY_MONITOR_POLARITY_MASK (3UL << 3) 271 #define DISPLAY_MONITOR_POSITIVE_HSYNC (1UL << 3) 272 #define DISPLAY_MONITOR_POSITIVE_VSYNC (2UL << 3) 273 274 // display B 275 #define INTEL_DISPLAY_B_DIGITAL_PORT 0x61140 276 #define INTEL_DISPLAY_B_IMAGE_SIZE 0x6101c 277 278 #define INTEL_DISPLAY_B_PIPE_CONTROL 0x71008 279 280 #define INTEL_DISPLAY_B_CONTROL 0x71180 281 #define INTEL_DISPLAY_B_BASE 0x71184 282 #define INTEL_DISPLAY_B_BYTES_PER_ROW 0x71188 283 #define INTEL_DISPLAY_B_SURFACE 0x7119c // i965 and up only 284 285 #define INTEL_DISPLAY_B_PALETTE 0x0a800 286 287 #define INTEL_DISPLAY_A_DIGITAL_PORT 0x61120 288 #define INTEL_DISPLAY_C_DIGITAL 0x61160 289 #define INTEL_DISPLAY_LVDS_PORT 0x61180 290 291 // cursor 292 #define INTEL_CURSOR_CONTROL 0x70080 293 #define INTEL_CURSOR_BASE 0x70084 294 #define INTEL_CURSOR_POSITION 0x70088 295 #define INTEL_CURSOR_PALETTE 0x70090 // (- 0x7009f) 296 #define INTEL_CURSOR_SIZE 0x700a0 297 #define CURSOR_ENABLED (1UL << 31) 298 #define CURSOR_FORMAT_2_COLORS (0UL << 24) 299 #define CURSOR_FORMAT_3_COLORS (1UL << 24) 300 #define CURSOR_FORMAT_4_COLORS (2UL << 24) 301 #define CURSOR_FORMAT_ARGB (4UL << 24) 302 #define CURSOR_FORMAT_XRGB (5UL << 24) 303 #define CURSOR_POSITION_NEGATIVE 0x8000 304 #define CURSOR_POSITION_MASK 0x3fff 305 306 // ring buffer commands 307 308 #define COMMAND_NOOP 0x00 309 #define COMMAND_WAIT_FOR_EVENT (0x03 << 23) 310 #define COMMAND_WAIT_FOR_OVERLAY_FLIP (1 << 16) 311 312 #define COMMAND_FLUSH (0x04 << 23) 313 314 // overlay flip 315 #define COMMAND_OVERLAY_FLIP (0x11 << 23) 316 #define COMMAND_OVERLAY_CONTINUE (0 << 21) 317 #define COMMAND_OVERLAY_ON (1 << 21) 318 #define COMMAND_OVERLAY_OFF (2 << 21) 319 #define OVERLAY_UPDATE_COEFFICIENTS 0x1 320 321 // 2D acceleration 322 #define XY_COMMAND_SOURCE_BLIT 0x54c00006 323 #define XY_COMMAND_COLOR_BLIT 0x54000004 324 #define XY_COMMAND_SETUP_MONO_PATTERN 0x44400007 325 #define XY_COMMAND_SCANLINE_BLIT 0x49400001 326 #define COMMAND_COLOR_BLIT 0x50000003 327 #define COMMAND_BLIT_RGBA 0x00300000 328 329 #define COMMAND_MODE_SOLID_PATTERN 0x80 330 #define COMMAND_MODE_CMAP8 0x00 331 #define COMMAND_MODE_RGB15 0x02 332 #define COMMAND_MODE_RGB16 0x01 333 #define COMMAND_MODE_RGB32 0x03 334 335 // i2c 336 337 #define INTEL_I2C_IO_A 0x5010 338 #define INTEL_I2C_IO_B 0x5014 339 #define INTEL_I2C_IO_C 0x5018 340 #define INTEL_I2C_IO_D 0x501c 341 #define INTEL_I2C_IO_E 0x5020 342 #define INTEL_I2C_IO_F 0x5024 343 #define INTEL_I2C_IO_G 0x5028 344 #define INTEL_I2C_IO_H 0x502c 345 346 #define I2C_CLOCK_DIRECTION_MASK (1 << 0) 347 #define I2C_CLOCK_DIRECTION_OUT (1 << 1) 348 #define I2C_CLOCK_VALUE_MASK (1 << 2) 349 #define I2C_CLOCK_VALUE_OUT (1 << 3) 350 #define I2C_CLOCK_VALUE_IN (1 << 4) 351 #define I2C_DATA_DIRECTION_MASK (1 << 8) 352 #define I2C_DATA_DIRECTION_OUT (1 << 9) 353 #define I2C_DATA_VALUE_MASK (1 << 10) 354 #define I2C_DATA_VALUE_OUT (1 << 11) 355 #define I2C_DATA_VALUE_IN (1 << 12) 356 #define I2C_RESERVED ((1 << 13) | (1 << 5)) 357 358 // overlay 359 360 #define INTEL_OVERLAY_UPDATE 0x30000 361 #define INTEL_OVERLAY_TEST 0x30004 362 #define INTEL_OVERLAY_STATUS 0x30008 363 #define INTEL_OVERLAY_EXTENDED_STATUS 0x3000c 364 #define INTEL_OVERLAY_GAMMA_5 0x30010 365 #define INTEL_OVERLAY_GAMMA_4 0x30014 366 #define INTEL_OVERLAY_GAMMA_3 0x30018 367 #define INTEL_OVERLAY_GAMMA_2 0x3001c 368 #define INTEL_OVERLAY_GAMMA_1 0x30020 369 #define INTEL_OVERLAY_GAMMA_0 0x30024 370 371 struct overlay_scale { 372 uint32 _reserved0 : 3; 373 uint32 horizontal_scale_fraction : 12; 374 uint32 _reserved1 : 1; 375 uint32 horizontal_downscale_factor : 3; 376 uint32 _reserved2 : 1; 377 uint32 vertical_scale_fraction : 12; 378 }; 379 380 #define OVERLAY_FORMAT_RGB15 0x2 381 #define OVERLAY_FORMAT_RGB16 0x3 382 #define OVERLAY_FORMAT_RGB32 0x1 383 #define OVERLAY_FORMAT_YCbCr422 0x8 384 #define OVERLAY_FORMAT_YCbCr411 0x9 385 #define OVERLAY_FORMAT_YCbCr420 0xc 386 387 #define OVERLAY_MIRROR_NORMAL 0x0 388 #define OVERLAY_MIRROR_HORIZONTAL 0x1 389 #define OVERLAY_MIRROR_VERTICAL 0x2 390 391 // The real overlay registers are written to using an update buffer 392 393 struct overlay_registers { 394 uint32 buffer_rgb0; 395 uint32 buffer_rgb1; 396 uint32 buffer_u0; 397 uint32 buffer_v0; 398 uint32 buffer_u1; 399 uint32 buffer_v1; 400 // (0x18) OSTRIDE - overlay stride 401 uint16 stride_rgb; 402 uint16 stride_uv; 403 // (0x1c) YRGB_VPH - Y/RGB vertical phase 404 uint16 vertical_phase0_rgb; 405 uint16 vertical_phase1_rgb; 406 // (0x20) UV_VPH - UV vertical phase 407 uint16 vertical_phase0_uv; 408 uint16 vertical_phase1_uv; 409 // (0x24) HORZ_PH - horizontal phase 410 uint16 horizontal_phase_rgb; 411 uint16 horizontal_phase_uv; 412 // (0x28) INIT_PHS - initial phase shift 413 uint32 initial_vertical_phase0_shift_rgb0 : 4; 414 uint32 initial_vertical_phase1_shift_rgb0 : 4; 415 uint32 initial_horizontal_phase_shift_rgb0 : 4; 416 uint32 initial_vertical_phase0_shift_uv : 4; 417 uint32 initial_vertical_phase1_shift_uv : 4; 418 uint32 initial_horizontal_phase_shift_uv : 4; 419 uint32 _reserved0 : 8; 420 // (0x2c) DWINPOS - destination window position 421 uint16 window_left; 422 uint16 window_top; 423 // (0x30) DWINSZ - destination window size 424 uint16 window_width; 425 uint16 window_height; 426 // (0x34) SWIDTH - source width 427 uint16 source_width_rgb; 428 uint16 source_width_uv; 429 // (0x38) SWITDHSW - source width in 8 byte steps 430 uint16 source_bytes_per_row_rgb; 431 uint16 source_bytes_per_row_uv; 432 uint16 source_height_rgb; 433 uint16 source_height_uv; 434 overlay_scale scale_rgb; 435 overlay_scale scale_uv; 436 // (0x48) OCLRC0 - overlay color correction 0 437 uint32 brightness_correction : 8; // signed, -128 to 127 438 uint32 _reserved1 : 10; 439 uint32 contrast_correction : 9; // fixed point: 3.6 bits 440 uint32 _reserved2 : 5; 441 // (0x4c) OCLRC1 - overlay color correction 1 442 uint32 saturation_cos_correction : 10; // fixed point: 3.7 bits 443 uint32 _reserved3 : 6; 444 uint32 saturation_sin_correction : 11; // signed fixed point: 3.7 bits 445 uint32 _reserved4 : 5; 446 // (0x50) DCLRKV - destination color key value 447 uint32 color_key_blue : 8; 448 uint32 color_key_green : 8; 449 uint32 color_key_red : 8; 450 uint32 _reserved5 : 8; 451 // (0x54) DCLRKM - destination color key mask 452 uint32 color_key_mask_blue : 8; 453 uint32 color_key_mask_green : 8; 454 uint32 color_key_mask_red : 8; 455 uint32 _reserved6 : 7; 456 uint32 color_key_enabled : 1; 457 // (0x58) SCHRKVH - source chroma key high value 458 uint32 source_chroma_key_high_red : 8; 459 uint32 source_chroma_key_high_blue : 8; 460 uint32 source_chroma_key_high_green : 8; 461 uint32 _reserved7 : 8; 462 // (0x5c) SCHRKVL - source chroma key low value 463 uint32 source_chroma_key_low_red : 8; 464 uint32 source_chroma_key_low_blue : 8; 465 uint32 source_chroma_key_low_green : 8; 466 uint32 _reserved8 : 8; 467 // (0x60) SCHRKEN - source chroma key enable 468 uint32 _reserved9 : 24; 469 uint32 source_chroma_key_red_enabled : 1; 470 uint32 source_chroma_key_blue_enabled : 1; 471 uint32 source_chroma_key_green_enabled : 1; 472 uint32 _reserved10 : 5; 473 // (0x64) OCONFIG - overlay configuration 474 uint32 _reserved11 : 3; 475 uint32 color_control_output_mode : 1; 476 uint32 yuv_to_rgb_bypass : 1; 477 uint32 _reserved12 : 11; 478 uint32 gamma2_enabled : 1; 479 uint32 _reserved13 : 1; 480 uint32 select_pipe : 1; 481 uint32 slot_time : 8; 482 uint32 _reserved14 : 5; 483 // (0x68) OCOMD - overlay command 484 uint32 overlay_enabled : 1; 485 uint32 active_field : 1; 486 uint32 active_buffer : 2; 487 uint32 test_mode : 1; 488 uint32 buffer_field_mode : 1; 489 uint32 _reserved15 : 1; 490 uint32 tv_flip_field_enabled : 1; 491 uint32 _reserved16 : 1; 492 uint32 tv_flip_field_parity : 1; 493 uint32 source_format : 4; 494 uint32 ycbcr422_order : 2; 495 uint32 _reserved18 : 1; 496 uint32 mirroring_mode : 2; 497 uint32 _reserved19 : 13; 498 499 uint32 _reserved20; 500 501 uint32 start_0y; 502 uint32 start_1y; 503 uint32 start_0u; 504 uint32 start_0v; 505 uint32 start_1u; 506 uint32 start_1v; 507 uint32 _reserved21[6]; 508 #if 0 509 // (0x70) AWINPOS - alpha blend window position 510 uint32 awinpos; 511 // (0x74) AWINSZ - alpha blend window size 512 uint32 awinsz; 513 514 uint32 _reserved21[10]; 515 #endif 516 517 // (0xa0) FASTHSCALE - fast horizontal downscale (strangely enough, 518 // the next two registers switch the usual Y/RGB vs. UV order) 519 uint16 horizontal_scale_uv; 520 uint16 horizontal_scale_rgb; 521 // (0xa4) UVSCALEV - vertical downscale 522 uint16 vertical_scale_uv; 523 uint16 vertical_scale_rgb; 524 525 uint32 _reserved22[86]; 526 527 // (0x200) polyphase filter coefficients 528 uint16 vertical_coefficients_rgb[128]; 529 uint16 horizontal_coefficients_rgb[128]; 530 531 uint32 _reserved23[64]; 532 533 // (0x500) 534 uint16 vertical_coefficients_uv[128]; 535 uint16 horizontal_coefficients_uv[128]; 536 }; 537 538 // i965 overlay support is currently realized using its 3D hardware 539 #define INTEL_i965_OVERLAY_STATE_SIZE 36864 540 #define INTEL_i965_3D_CONTEXT_SIZE 32768 541 542 inline bool 543 intel_uses_physical_overlay(intel_shared_info &info) 544 { 545 return info.device_type != INTEL_TYPE_G33; 546 } 547 548 549 struct hardware_status { 550 uint32 interrupt_status_register; 551 uint32 _reserved0[3]; 552 void *primary_ring_head_storage; 553 uint32 _reserved1[3]; 554 void *secondary_ring_0_head_storage; 555 void *secondary_ring_1_head_storage; 556 uint32 _reserved2[2]; 557 void *binning_head_storage; 558 uint32 _reserved3[3]; 559 uint32 store[1008]; 560 }; 561 562 #endif /* INTEL_EXTREME_H */ 563