1 /* 2 * Copyright 2006-2016, Haiku, Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Axel Dörfler, axeld@pinc-software.de 7 * Alexander von Gluck, kallisti5@unixzen.com 8 */ 9 #ifndef INTEL_EXTREME_H 10 #define INTEL_EXTREME_H 11 12 13 #include "lock.h" 14 15 #include <Accelerant.h> 16 #include <Drivers.h> 17 #include <PCI.h> 18 19 #include <edid.h> 20 21 22 #define VENDOR_ID_INTEL 0x8086 23 24 #define INTEL_FAMILY_MASK 0x00ff0000 25 #define INTEL_GROUP_MASK 0x00fffff0 26 #define INTEL_MODEL_MASK 0x00ffffff 27 #define INTEL_TYPE_MASK 0x0000000f 28 // families 29 #define INTEL_FAMILY_7xx 0x00010000 // First Gen 30 #define INTEL_FAMILY_8xx 0x00020000 // Second Gen 31 #define INTEL_FAMILY_9xx 0x00040000 // Third Gen + 32 #define INTEL_FAMILY_SER5 0x00080000 // Intel5 Series 33 #define INTEL_FAMILY_POVR 0x00100000 // PowerVR (uugh) 34 #define INTEL_FAMILY_SOC0 0x00200000 // Atom SOC 35 #define INTEL_FAMILY_LAKE 0x00400000 // Intel Lakes 36 // groups 37 #define INTEL_GROUP_83x (INTEL_FAMILY_8xx | 0x0010) 38 #define INTEL_GROUP_85x (INTEL_FAMILY_8xx | 0x0020) 39 #define INTEL_GROUP_91x (INTEL_FAMILY_9xx | 0x0010) 40 #define INTEL_GROUP_94x (INTEL_FAMILY_9xx | 0x0020) 41 #define INTEL_GROUP_96x (INTEL_FAMILY_9xx | 0x0040) 42 #define INTEL_GROUP_Gxx (INTEL_FAMILY_9xx | 0x0080) 43 #define INTEL_GROUP_G4x (INTEL_FAMILY_9xx | 0x0100) 44 #define INTEL_GROUP_PIN (INTEL_FAMILY_9xx | 0x0200) // PineView 45 #define INTEL_GROUP_ILK (INTEL_FAMILY_SER5 | 0x0010) // IronLake 46 #define INTEL_GROUP_SNB (INTEL_FAMILY_SER5 | 0x0020) // SandyBridge 47 #define INTEL_GROUP_IVB (INTEL_FAMILY_SER5 | 0x0040) // IvyBridge 48 #define INTEL_GROUP_HAS (INTEL_FAMILY_SER5 | 0x0080) // Haswell 49 #define INTEL_GROUP_SLT (INTEL_FAMILY_POVR | 0x0010) // Saltwell 50 #define INTEL_GROUP_FSM (INTEL_FAMILY_POVR | 0x0020) // Fu.Silvermont 51 #define INTEL_GROUP_VLV (INTEL_FAMILY_SOC0 | 0x0010) // ValleyView 52 #define INTEL_GROUP_CHV (INTEL_FAMILY_SOC0 | 0x0020) // CherryView 53 #define INTEL_GROUP_BXT (INTEL_FAMILY_SOC0 | 0x0040) // Broxton 54 #define INTEL_GROUP_SKY (INTEL_FAMILY_LAKE | 0x0010) // SkyLake 55 #define INTEL_GROUP_KBY (INTEL_FAMILY_LAKE | 0x0020) // KabyLake 56 // models 57 #define INTEL_TYPE_SERVER 0x0004 58 #define INTEL_TYPE_MOBILE 0x0008 59 #define INTEL_MODEL_915 (INTEL_GROUP_91x) 60 #define INTEL_MODEL_915M (INTEL_GROUP_91x | INTEL_TYPE_MOBILE) 61 #define INTEL_MODEL_945 (INTEL_GROUP_94x) 62 #define INTEL_MODEL_945M (INTEL_GROUP_94x | INTEL_TYPE_MOBILE) 63 #define INTEL_MODEL_965 (INTEL_GROUP_96x) 64 #define INTEL_MODEL_965M (INTEL_GROUP_96x | INTEL_TYPE_MOBILE) 65 #define INTEL_MODEL_G33 (INTEL_GROUP_Gxx) 66 #define INTEL_MODEL_G45 (INTEL_GROUP_G4x) 67 #define INTEL_MODEL_GM45 (INTEL_GROUP_G4x | INTEL_TYPE_MOBILE) 68 #define INTEL_MODEL_PINE (INTEL_GROUP_PIN) 69 #define INTEL_MODEL_PINEM (INTEL_GROUP_PIN | INTEL_TYPE_MOBILE) 70 #define INTEL_MODEL_ILKG (INTEL_GROUP_ILK) 71 #define INTEL_MODEL_ILKGM (INTEL_GROUP_ILK | INTEL_TYPE_MOBILE) 72 #define INTEL_MODEL_SNBG (INTEL_GROUP_SNB) 73 #define INTEL_MODEL_SNBGM (INTEL_GROUP_SNB | INTEL_TYPE_MOBILE) 74 #define INTEL_MODEL_SNBGS (INTEL_GROUP_SNB | INTEL_TYPE_SERVER) 75 #define INTEL_MODEL_IVBG (INTEL_GROUP_IVB) 76 #define INTEL_MODEL_IVBGM (INTEL_GROUP_IVB | INTEL_TYPE_MOBILE) 77 #define INTEL_MODEL_IVBGS (INTEL_GROUP_IVB | INTEL_TYPE_SERVER) 78 #define INTEL_MODEL_HAS (INTEL_GROUP_HAS) 79 #define INTEL_MODEL_HASM (INTEL_GROUP_HAS | INTEL_TYPE_MOBILE) 80 #define INTEL_MODEL_VLV (INTEL_GROUP_VLV) 81 #define INTEL_MODEL_VLVM (INTEL_GROUP_VLV | INTEL_TYPE_MOBILE) 82 #define INTEL_MODEL_SKY (INTEL_GROUP_SKY) 83 #define INTEL_MODEL_SKYM (INTEL_GROUP_SKY | INTEL_TYPE_MOBILE) 84 #define INTEL_MODEL_SKYS (INTEL_GROUP_SKY | INTEL_TYPE_SERVER) 85 86 #define INTEL_PCH_DEVICE_ID_MASK 0xff00 87 #define INTEL_PCH_IBX_DEVICE_ID 0x3b00 88 #define INTEL_PCH_CPT_DEVICE_ID 0x1c00 89 #define INTEL_PCH_PPT_DEVICE_ID 0x1e00 90 #define INTEL_PCH_LPT_DEVICE_ID 0x8c00 91 #define INTEL_PCH_LPT_LP_DEVICE_ID 0x9c00 92 #define INTEL_PCH_SPT_DEVICE_ID 0xa100 93 #define INTEL_PCH_SPT_LP_DEVICE_ID 0x9d00 94 #define INTEL_PCH_P2X_DEVICE_ID 0x7100 95 #define INTEL_PCH_P3X_DEVICE_ID 0x7000 96 97 // ValleyView MMIO offset 98 #define VLV_DISPLAY_BASE 0x180000 99 100 #define DEVICE_NAME "intel_extreme" 101 #define INTEL_ACCELERANT_NAME "intel_extreme.accelerant" 102 103 // We encode the register block into the value and extract/translate it when 104 // actually accessing. 105 #define REGISTER_BLOCK_COUNT 6 106 #define REGISTER_BLOCK_SHIFT 24 107 #define REGISTER_BLOCK_MASK 0xff000000 108 #define REGISTER_REGISTER_MASK 0x00ffffff 109 #define REGISTER_BLOCK(x) ((x & REGISTER_BLOCK_MASK) >> REGISTER_BLOCK_SHIFT) 110 #define REGISTER_REGISTER(x) (x & REGISTER_REGISTER_MASK) 111 112 #define REGS_FLAT (0 << REGISTER_BLOCK_SHIFT) 113 #define REGS_NORTH_SHARED (1 << REGISTER_BLOCK_SHIFT) 114 #define REGS_NORTH_PIPE_AND_PORT (2 << REGISTER_BLOCK_SHIFT) 115 #define REGS_NORTH_PLANE_CONTROL (3 << REGISTER_BLOCK_SHIFT) 116 #define REGS_SOUTH_SHARED (4 << REGISTER_BLOCK_SHIFT) 117 #define REGS_SOUTH_TRANSCODER_PORT (5 << REGISTER_BLOCK_SHIFT) 118 119 // register blocks for (G)MCH/ICH based platforms 120 #define MCH_SHARED_REGISTER_BASE 0x00000 121 #define MCH_PIPE_AND_PORT_REGISTER_BASE 0x60000 122 #define MCH_PLANE_CONTROL_REGISTER_BASE 0x70000 123 124 #define ICH_SHARED_REGISTER_BASE 0x00000 125 #define ICH_PORT_REGISTER_BASE 0x60000 126 127 // PCH - Platform Control Hub - Some hardware moves from a MCH/ICH based 128 // setup to a PCH based one, that means anything that used to communicate via 129 // (G)MCH registers needs to use different ones on PCH based platforms 130 // (Ironlake, SandyBridge, IvyBridge, Some Haswell). 131 #define PCH_NORTH_SHARED_REGISTER_BASE 0x40000 132 #define PCH_NORTH_PIPE_AND_PORT_REGISTER_BASE 0x60000 133 #define PCH_NORTH_PLANE_CONTROL_REGISTER_BASE 0x70000 134 #define PCH_SOUTH_SHARED_REGISTER_BASE 0xc0000 135 #define PCH_SOUTH_TRANSCODER_AND_PORT_REGISTER_BASE 0xe0000 136 137 138 struct DeviceType { 139 uint32 type; 140 141 DeviceType(int t) 142 { 143 type = t; 144 } 145 146 DeviceType& operator=(int t) 147 { 148 type = t; 149 return *this; 150 } 151 152 bool InFamily(uint32 family) const 153 { 154 return (type & INTEL_FAMILY_MASK) == family; 155 } 156 157 bool InGroup(uint32 group) const 158 { 159 return (type & INTEL_GROUP_MASK) == group; 160 } 161 162 bool IsModel(uint32 model) const 163 { 164 return (type & INTEL_MODEL_MASK) == model; 165 } 166 167 bool IsMobile() const 168 { 169 return (type & INTEL_TYPE_MASK) == INTEL_TYPE_MOBILE; 170 } 171 172 bool SupportsHDMI() const 173 { 174 return InGroup(INTEL_GROUP_G4x) || InFamily(INTEL_FAMILY_SER5) 175 || InFamily(INTEL_FAMILY_SOC0); 176 } 177 178 bool HasDDI() const 179 { 180 // Intel Digital Display Interface 181 return InGroup(INTEL_GROUP_HAS) || (Generation() >= 8); 182 } 183 184 int Generation() const 185 { 186 if (InFamily(INTEL_FAMILY_7xx)) 187 return 1; 188 if (InFamily(INTEL_FAMILY_8xx)) 189 return 2; 190 if (InGroup(INTEL_GROUP_91x) || InGroup(INTEL_GROUP_94x) 191 || IsModel(INTEL_MODEL_G33) || InGroup(INTEL_GROUP_PIN)) 192 return 3; 193 if (InFamily(INTEL_FAMILY_9xx)) 194 return 4; 195 if (InGroup(INTEL_GROUP_ILK)) 196 return 5; 197 if (InGroup(INTEL_GROUP_SNB)) 198 return 6; 199 if (InFamily(INTEL_FAMILY_SER5) || InGroup(INTEL_GROUP_VLV)) 200 return 7; 201 if (InGroup(INTEL_GROUP_CHV)) 202 return 8; 203 if (InGroup(INTEL_GROUP_BXT) || InFamily(INTEL_FAMILY_LAKE)) 204 return 9; 205 206 // Generation 0 means somethins is wrong :-) 207 return 0; 208 } 209 }; 210 211 enum pch_info { 212 INTEL_PCH_NONE = 0, // No PCH present 213 INTEL_PCH_IBX, // Ibexpeak 214 INTEL_PCH_CPT, // Cougarpoint 215 INTEL_PCH_LPT, // Lynxpoint 216 INTEL_PCH_SPT, // Sunrisepoint 217 INTEL_PCH_NOP 218 }; 219 220 // info about PLL on graphics card 221 struct pll_info { 222 uint32 reference_frequency; 223 uint32 max_frequency; 224 uint32 min_frequency; 225 uint32 divisor_register; 226 }; 227 228 struct ring_buffer { 229 struct lock lock; 230 uint32 register_base; 231 uint32 offset; 232 uint32 size; 233 uint32 position; 234 uint32 space_left; 235 uint8* base; 236 }; 237 238 struct overlay_registers; 239 240 struct intel_shared_info { 241 area_id mode_list_area; // area containing display mode list 242 uint32 mode_count; 243 244 display_mode panel_mode; // VBIOS VBT panel mode 245 uint32 bytes_per_row; 246 uint32 bits_per_pixel; 247 uint32 dpms_mode; 248 249 area_id registers_area; // area of memory mapped registers 250 uint32 register_blocks[REGISTER_BLOCK_COUNT]; 251 252 uint8* status_page; 253 phys_addr_t physical_status_page; 254 uint8* graphics_memory; 255 phys_addr_t physical_graphics_memory; 256 uint32 graphics_memory_size; 257 258 addr_t frame_buffer; 259 uint32 frame_buffer_offset; 260 261 uint32 fdi_link_frequency; // In Mhz 262 263 bool got_vbt; 264 bool single_head_locked; 265 266 struct lock accelerant_lock; 267 struct lock engine_lock; 268 269 ring_buffer primary_ring_buffer; 270 271 int32 overlay_channel_used; 272 bool overlay_active; 273 uintptr_t overlay_token; 274 phys_addr_t physical_overlay_registers; 275 uint32 overlay_offset; 276 277 bool hardware_cursor_enabled; 278 sem_id vblank_sem; 279 280 uint8* cursor_memory; 281 phys_addr_t physical_cursor_memory; 282 uint32 cursor_buffer_offset; 283 uint32 cursor_format; 284 bool cursor_visible; 285 uint16 cursor_hot_x; 286 uint16 cursor_hot_y; 287 288 DeviceType device_type; 289 char device_identifier[32]; 290 struct pll_info pll_info; 291 292 enum pch_info pch_info; 293 294 edid1_info vesa_edid_info; 295 bool has_vesa_edid_info; 296 }; 297 298 enum pipe_index { 299 INTEL_PIPE_ANY, 300 INTEL_PIPE_A, 301 INTEL_PIPE_B 302 }; 303 304 //----------------- ioctl() interface ---------------- 305 306 // magic code for ioctls 307 #define INTEL_PRIVATE_DATA_MAGIC 'itic' 308 309 // list ioctls 310 enum { 311 INTEL_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1, 312 313 INTEL_GET_DEVICE_NAME, 314 INTEL_ALLOCATE_GRAPHICS_MEMORY, 315 INTEL_FREE_GRAPHICS_MEMORY 316 }; 317 318 // retrieve the area_id of the kernel/accelerant shared info 319 struct intel_get_private_data { 320 uint32 magic; // magic number 321 area_id shared_info_area; 322 }; 323 324 // allocate graphics memory 325 struct intel_allocate_graphics_memory { 326 uint32 magic; 327 uint32 size; 328 uint32 alignment; 329 uint32 flags; 330 addr_t buffer_base; 331 }; 332 333 // free graphics memory 334 struct intel_free_graphics_memory { 335 uint32 magic; 336 addr_t buffer_base; 337 }; 338 339 //---------------------------------------------------------- 340 // Register definitions, taken from X driver 341 342 // PCI bridge memory management 343 #define INTEL_GRAPHICS_MEMORY_CONTROL 0x52 // i830+ 344 345 // GGC - (G)MCH Graphics Control Register 346 #define MEMORY_CONTROL_ENABLED 0x0004 347 #define MEMORY_MASK 0x0001 348 #define STOLEN_MEMORY_MASK 0x00f0 349 #define i965_GTT_MASK 0x000e 350 #define G33_GTT_MASK 0x0300 351 #define G4X_GTT_MASK 0x0f00 // GGMS (GSM Memory Size) mask 352 353 // models i830 and up 354 #define i830_LOCAL_MEMORY_ONLY 0x10 355 #define i830_STOLEN_512K 0x20 356 #define i830_STOLEN_1M 0x30 357 #define i830_STOLEN_8M 0x40 358 #define i830_FRAME_BUFFER_64M 0x01 359 #define i830_FRAME_BUFFER_128M 0x00 360 361 // models i855 and up 362 #define i855_STOLEN_MEMORY_1M 0x10 363 #define i855_STOLEN_MEMORY_4M 0x20 364 #define i855_STOLEN_MEMORY_8M 0x30 365 #define i855_STOLEN_MEMORY_16M 0x40 366 #define i855_STOLEN_MEMORY_32M 0x50 367 #define i855_STOLEN_MEMORY_48M 0x60 368 #define i855_STOLEN_MEMORY_64M 0x70 369 #define i855_STOLEN_MEMORY_128M 0x80 370 #define i855_STOLEN_MEMORY_256M 0x90 371 372 #define G4X_STOLEN_MEMORY_96MB 0xa0 // GMS - Graphics Mode Select 373 #define G4X_STOLEN_MEMORY_160MB 0xb0 374 #define G4X_STOLEN_MEMORY_224MB 0xc0 375 #define G4X_STOLEN_MEMORY_352MB 0xd0 376 377 // SandyBridge (SNB) 378 379 #define SNB_GRAPHICS_MEMORY_CONTROL 0x50 380 381 #define SNB_STOLEN_MEMORY_MASK 0xf8 382 #define SNB_STOLEN_MEMORY_32MB (1 << 3) 383 #define SNB_STOLEN_MEMORY_64MB (2 << 3) 384 #define SNB_STOLEN_MEMORY_96MB (3 << 3) 385 #define SNB_STOLEN_MEMORY_128MB (4 << 3) 386 #define SNB_STOLEN_MEMORY_160MB (5 << 3) 387 #define SNB_STOLEN_MEMORY_192MB (6 << 3) 388 #define SNB_STOLEN_MEMORY_224MB (7 << 3) 389 #define SNB_STOLEN_MEMORY_256MB (8 << 3) 390 #define SNB_STOLEN_MEMORY_288MB (9 << 3) 391 #define SNB_STOLEN_MEMORY_320MB (10 << 3) 392 #define SNB_STOLEN_MEMORY_352MB (11 << 3) 393 #define SNB_STOLEN_MEMORY_384MB (12 << 3) 394 #define SNB_STOLEN_MEMORY_416MB (13 << 3) 395 #define SNB_STOLEN_MEMORY_448MB (14 << 3) 396 #define SNB_STOLEN_MEMORY_480MB (15 << 3) 397 #define SNB_STOLEN_MEMORY_512MB (16 << 3) 398 399 #define SNB_GTT_SIZE_MASK (3 << 8) 400 #define SNB_GTT_SIZE_NONE (0 << 8) 401 #define SNB_GTT_SIZE_1MB (1 << 8) 402 #define SNB_GTT_SIZE_2MB (2 << 8) 403 404 // graphics page translation table 405 #define INTEL_PAGE_TABLE_CONTROL 0x02020 406 #define PAGE_TABLE_ENABLED 0x00000001 407 #define INTEL_PAGE_TABLE_ERROR 0x02024 408 #define INTEL_HARDWARE_STATUS_PAGE 0x02080 409 #define i915_GTT_BASE 0x1c 410 #define i830_GTT_BASE 0x10000 // (- 0x2ffff) 411 #define i830_GTT_SIZE 0x20000 412 #define i965_GTT_BASE 0x80000 // (- 0xfffff) 413 #define i965_GTT_SIZE 0x80000 414 #define i965_GTT_128K (2 << 1) 415 #define i965_GTT_256K (1 << 1) 416 #define i965_GTT_512K (0 << 1) 417 #define G33_GTT_1M (1 << 8) 418 #define G33_GTT_2M (2 << 8) 419 #define G4X_GTT_NONE 0x000 // GGMS - GSM Memory Size 420 #define G4X_GTT_1M_NO_IVT 0x100 // no Intel Virtualization Tech. 421 #define G4X_GTT_2M_NO_IVT 0x300 422 #define G4X_GTT_2M_IVT 0x900 // with Intel Virt. Tech. 423 #define G4X_GTT_3M_IVT 0xa00 424 #define G4X_GTT_4M_IVT 0xb00 425 426 427 #define GTT_ENTRY_VALID 0x01 428 #define GTT_ENTRY_LOCAL_MEMORY 0x02 429 #define GTT_PAGE_SHIFT 12 430 431 432 // ring buffer 433 #define INTEL_PRIMARY_RING_BUFFER 0x02030 434 #define INTEL_SECONDARY_RING_BUFFER_0 0x02100 435 #define INTEL_SECONDARY_RING_BUFFER_1 0x02110 436 // offsets for the ring buffer base registers above 437 #define RING_BUFFER_TAIL 0x0 438 #define RING_BUFFER_HEAD 0x4 439 #define RING_BUFFER_START 0x8 440 #define RING_BUFFER_CONTROL 0xc 441 #define INTEL_RING_BUFFER_SIZE_MASK 0x001ff000 442 #define INTEL_RING_BUFFER_HEAD_MASK 0x001ffffc 443 #define INTEL_RING_BUFFER_ENABLED 1 444 445 // interrupts 446 #define INTEL_INTERRUPT_ENABLED 0x020a0 447 #define INTEL_INTERRUPT_IDENTITY 0x020a4 448 #define INTEL_INTERRUPT_MASK 0x020a8 449 #define INTEL_INTERRUPT_STATUS 0x020ac 450 #define INTERRUPT_VBLANK_PIPEA (1 << 7) 451 #define INTERRUPT_VBLANK_PIPEB (1 << 5) 452 453 // PCH interrupts 454 #define PCH_INTERRUPT_STATUS 0x44000 455 #define PCH_INTERRUPT_MASK 0x44004 456 #define PCH_INTERRUPT_IDENTITY 0x44008 457 #define PCH_INTERRUPT_ENABLED 0x4400c 458 459 #define PCH_INTERRUPT_VBLANK_PIPEA (1 << 0) 460 #define PCH_INTERRUPT_VBLANK_PIPEB (1 << 5) 461 #define PCH_INTERRUPT_VBLANK_PIPEC (1 << 10) 462 463 // SandyBridge had only two pipes, and things were shuffled aroud again with 464 // the introduction of pipe C. 465 #define PCH_INTERRUPT_VBLANK_PIPEA_SNB (1 << 7) 466 #define PCH_INTERRUPT_VBLANK_PIPEB_SNB (1 << 15) 467 #define PCH_INTERRUPT_GLOBAL_SNB (1 << 31) 468 469 // graphics port control 470 #define DISPLAY_MONITOR_PORT_ENABLED (1UL << 31) 471 #define DISPLAY_MONITOR_PIPE_B (1UL << 30) 472 #define DISPLAY_MONITOR_VGA_POLARITY (1UL << 15) 473 #define DISPLAY_MONITOR_MODE_MASK (3UL << 10) 474 #define DISPLAY_MONITOR_ON 0 475 #define DISPLAY_MONITOR_SUSPEND (1UL << 10) 476 #define DISPLAY_MONITOR_STAND_BY (2UL << 10) 477 #define DISPLAY_MONITOR_OFF (3UL << 10) 478 #define DISPLAY_MONITOR_POLARITY_MASK (3UL << 3) 479 #define DISPLAY_MONITOR_POSITIVE_HSYNC (1UL << 3) 480 #define DISPLAY_MONITOR_POSITIVE_VSYNC (2UL << 3) 481 #define DISPLAY_MONITOR_PORT_DETECTED (1UL << 2) // TMDS/DisplayPort only 482 483 #define LVDS_POST2_RATE_SLOW 14 // PLL Divisors 484 #define LVDS_POST2_RATE_FAST 7 485 #define LVDS_B0B3_POWER_MASK (3UL << 2) 486 #define LVDS_B0B3_POWER_UP (3UL << 2) 487 #define LVDS_CLKB_POWER_MASK (3UL << 4) 488 #define LVDS_CLKB_POWER_UP (3UL << 4) 489 #define LVDS_A3_POWER_MASK (3UL << 6) 490 #define LVDS_A3_POWER_UP (3UL << 6) 491 #define LVDS_A0A2_CLKA_POWER_UP (3UL << 8) 492 #define LVDS_BORDER_ENABLE (1UL << 15) 493 #define LVDS_HSYNC_POLARITY (1UL << 20) 494 #define LVDS_VSYNC_POLARITY (1UL << 21) 495 #define LVDS_18BIT_DITHER (1UL << 25) 496 #define LVDS_PORT_EN (1UL << 31) 497 498 // PLL flags 499 #define DISPLAY_PLL_ENABLED (1UL << 31) 500 #define DISPLAY_PLL_2X_CLOCK (1UL << 30) 501 #define DISPLAY_PLL_SYNC_LOCK_ENABLED (1UL << 29) 502 #define DISPLAY_PLL_NO_VGA_CONTROL (1UL << 28) 503 #define DISPLAY_PLL_MODE_NORMAL (1UL << 26) 504 #define DISPLAY_PLL_MODE_LVDS (2UL << 26) 505 #define DISPLAY_PLL_DIVIDE_HIGH (1UL << 24) 506 #define DISPLAY_PLL_DIVIDE_4X (1UL << 23) 507 #define DISPLAY_PLL_POST1_DIVIDE_2 (1UL << 21) 508 #define DISPLAY_PLL_POST1_DIVISOR_MASK 0x001f0000 509 #define DISPLAY_PLL_9xx_POST1_DIVISOR_MASK 0x00ff0000 510 #define DISPLAY_PLL_IGD_POST1_DIVISOR_MASK 0x00ff8000 511 #define DISPLAY_PLL_POST1_DIVISOR_SHIFT 16 512 #define DISPLAY_PLL_IGD_POST1_DIVISOR_SHIFT 15 513 #define DISPLAY_PLL_DIVISOR_1 (1UL << 8) 514 #define DISPLAY_PLL_N_DIVISOR_MASK 0x001f0000 515 #define DISPLAY_PLL_IGD_N_DIVISOR_MASK 0x00ff0000 516 #define DISPLAY_PLL_M1_DIVISOR_MASK 0x00001f00 517 #define DISPLAY_PLL_M2_DIVISOR_MASK 0x0000001f 518 #define DISPLAY_PLL_IGD_M2_DIVISOR_MASK 0x000000ff 519 #define DISPLAY_PLL_N_DIVISOR_SHIFT 16 520 #define DISPLAY_PLL_M1_DIVISOR_SHIFT 8 521 #define DISPLAY_PLL_M2_DIVISOR_SHIFT 0 522 #define DISPLAY_PLL_PULSE_PHASE_SHIFT 9 523 524 // display 525 526 #define INTEL_DISPLAY_OFFSET 0x1000 527 528 #define INTEL_DISPLAY_A_HTOTAL (0x0000 | REGS_NORTH_PIPE_AND_PORT) 529 #define INTEL_DISPLAY_A_HBLANK (0x0004 | REGS_NORTH_PIPE_AND_PORT) 530 #define INTEL_DISPLAY_A_HSYNC (0x0008 | REGS_NORTH_PIPE_AND_PORT) 531 #define INTEL_DISPLAY_A_VTOTAL (0x000c | REGS_NORTH_PIPE_AND_PORT) 532 #define INTEL_DISPLAY_A_VBLANK (0x0010 | REGS_NORTH_PIPE_AND_PORT) 533 #define INTEL_DISPLAY_A_VSYNC (0x0014 | REGS_NORTH_PIPE_AND_PORT) 534 #define INTEL_DISPLAY_B_HTOTAL (0x1000 | REGS_NORTH_PIPE_AND_PORT) 535 #define INTEL_DISPLAY_B_HBLANK (0x1004 | REGS_NORTH_PIPE_AND_PORT) 536 #define INTEL_DISPLAY_B_HSYNC (0x1008 | REGS_NORTH_PIPE_AND_PORT) 537 #define INTEL_DISPLAY_B_VTOTAL (0x100c | REGS_NORTH_PIPE_AND_PORT) 538 #define INTEL_DISPLAY_B_VBLANK (0x1010 | REGS_NORTH_PIPE_AND_PORT) 539 #define INTEL_DISPLAY_B_VSYNC (0x1014 | REGS_NORTH_PIPE_AND_PORT) 540 541 #define INTEL_DISPLAY_A_IMAGE_SIZE (0x001c | REGS_NORTH_PIPE_AND_PORT) 542 #define INTEL_DISPLAY_B_IMAGE_SIZE (0x101c | REGS_NORTH_PIPE_AND_PORT) 543 544 // Cougar Point transcoder pipe selection 545 #define PORT_TRANS_A_SEL_CPT 0 546 #define PORT_TRANS_B_SEL_CPT (1<<29) 547 #define PORT_TRANS_C_SEL_CPT (2<<29) 548 #define PORT_TRANS_SEL_MASK (3<<29) 549 550 // on PCH we also have to set the transcoder 551 #define INTEL_TRANSCODER_A_HTOTAL (0x0000 | REGS_SOUTH_TRANSCODER_PORT) 552 #define INTEL_TRANSCODER_A_HBLANK (0x0004 | REGS_SOUTH_TRANSCODER_PORT) 553 #define INTEL_TRANSCODER_A_HSYNC (0x0008 | REGS_SOUTH_TRANSCODER_PORT) 554 #define INTEL_TRANSCODER_A_VTOTAL (0x000c | REGS_SOUTH_TRANSCODER_PORT) 555 #define INTEL_TRANSCODER_A_VBLANK (0x0010 | REGS_SOUTH_TRANSCODER_PORT) 556 #define INTEL_TRANSCODER_A_VSYNC (0x0014 | REGS_SOUTH_TRANSCODER_PORT) 557 #define INTEL_TRANSCODER_B_HTOTAL (0x1000 | REGS_SOUTH_TRANSCODER_PORT) 558 #define INTEL_TRANSCODER_B_HBLANK (0x1004 | REGS_SOUTH_TRANSCODER_PORT) 559 #define INTEL_TRANSCODER_B_HSYNC (0x1008 | REGS_SOUTH_TRANSCODER_PORT) 560 #define INTEL_TRANSCODER_B_VTOTAL (0x100c | REGS_SOUTH_TRANSCODER_PORT) 561 #define INTEL_TRANSCODER_B_VBLANK (0x1010 | REGS_SOUTH_TRANSCODER_PORT) 562 #define INTEL_TRANSCODER_B_VSYNC (0x1014 | REGS_SOUTH_TRANSCODER_PORT) 563 564 #define INTEL_TRANSCODER_A_IMAGE_SIZE (0x001c | REGS_SOUTH_TRANSCODER_PORT) 565 #define INTEL_TRANSCODER_B_IMAGE_SIZE (0x101c | REGS_SOUTH_TRANSCODER_PORT) 566 567 // TODO: Is there consolidation that could happen here with digital ports? 568 569 #define INTEL_ANALOG_PORT (0x1100 | REGS_SOUTH_TRANSCODER_PORT) 570 #define INTEL_DIGITAL_PORT_A (0x1120 | REGS_SOUTH_TRANSCODER_PORT) 571 #define INTEL_DIGITAL_PORT_B (0x1140 | REGS_SOUTH_TRANSCODER_PORT) 572 #define INTEL_DIGITAL_PORT_C (0x1160 | REGS_SOUTH_TRANSCODER_PORT) 573 #define INTEL_DIGITAL_LVDS_PORT (0x1180 | REGS_SOUTH_TRANSCODER_PORT) 574 575 #define INTEL_HDMI_PORT_B (0x1140 | REGS_SOUTH_TRANSCODER_PORT) 576 #define INTEL_HDMI_PORT_C (0x1160 | REGS_SOUTH_TRANSCODER_PORT) 577 578 #define PCH_HDMI_PORT_B (0x1140 | REGS_SOUTH_TRANSCODER_PORT) 579 #define PCH_HDMI_PORT_C (0x1150 | REGS_SOUTH_TRANSCODER_PORT) 580 #define PCH_HDMI_PORT_D (0x1160 | REGS_SOUTH_TRANSCODER_PORT) 581 582 #define GEN4_HDMI_PORT_B (0x1140 | REGS_SOUTH_TRANSCODER_PORT) 583 #define GEN4_HDMI_PORT_C (0x1160 | REGS_SOUTH_TRANSCODER_PORT) 584 #define CHV_HDMI_PORT_D (0x116C | REGS_SOUTH_TRANSCODER_PORT) 585 586 // DDI Buffer Control (This replaces DP on Haswell+) 587 #define DDI_BUF_CTL_A (0x4000 | REGS_NORTH_PIPE_AND_PORT) 588 #define DDI_BUF_CTL_B (0x4100 | REGS_NORTH_PIPE_AND_PORT) 589 #define DDI_BUF_CTL_C (0x4200 | REGS_NORTH_PIPE_AND_PORT) 590 #define DDI_BUF_CTL_D (0x4300 | REGS_NORTH_PIPE_AND_PORT) 591 #define DDI_BUF_CTL_E (0x4400 | REGS_NORTH_PIPE_AND_PORT) 592 #define DDI_BUF_CTL_ENABLE (1 << 31) 593 #define DDI_BUF_TRANS_SELECT(n) ((n) << 24) 594 #define DDI_BUF_EMP_MASK (0xf << 24) 595 #define DDI_BUF_PORT_REVERSAL (1 << 16) 596 #define DDI_BUF_IS_IDLE (1 << 7) 597 #define DDI_A_4_LANES (1 << 4) 598 #define DDI_PORT_WIDTH(width) (((width) - 1) << 1) 599 #define DDI_INIT_DISPLAY_DETECTED (1 << 0) 600 601 // DP_A always @ 6xxxx, DP_B-DP_D move with PCH 602 #define INTEL_DISPLAY_PORT_A (0x4000 | REGS_NORTH_PIPE_AND_PORT) 603 #define INTEL_DISPLAY_PORT_B (0x4100 | REGS_SOUTH_TRANSCODER_PORT) 604 #define INTEL_DISPLAY_PORT_C (0x4200 | REGS_SOUTH_TRANSCODER_PORT) 605 #define INTEL_DISPLAY_PORT_D (0x4300 | REGS_SOUTH_TRANSCODER_PORT) 606 607 // Unless you're a damn Valley/CherryView unicorn :-( 608 #define VLV_DISPLAY_PORT_B (VLV_DISPLAY_BASE + 0x64100) 609 #define VLV_DISPLAY_PORT_C (VLV_DISPLAY_BASE + 0x64200) 610 #define CHV_DISPLAY_PORT_D (VLV_DISPLAY_BASE + 0x64300) 611 612 // DP AUX channels 613 #define INTEL_DP_AUX_CTL_A (0x4010 | REGS_NORTH_PIPE_AND_PORT) 614 #define INTEL_DP_AUX_CTL_B (0x4110 | REGS_SOUTH_TRANSCODER_PORT) 615 #define INTEL_DP_AUX_CTL_C (0x4210 | REGS_SOUTH_TRANSCODER_PORT) 616 #define INTEL_DP_AUX_CTL_D (0x4310 | REGS_SOUTH_TRANSCODER_PORT) 617 618 #define VLV_DP_AUX_CTL_B (VLV_DISPLAY_BASE + 0x64110) 619 #define VLV_DP_AUX_CTL_C (VLV_DISPLAY_BASE + 0x64210) 620 #define CHV_DP_AUX_CTL_D (VLV_DISPLAY_BASE + 0x64310) 621 622 #define INTEL_DP_AUX_CTL_BUSY (1 << 31) 623 #define INTEL_DP_AUX_CTL_DONE (1 << 30) 624 #define INTEL_DP_AUX_CTL_INTERRUPT (1 << 29) 625 #define INTEL_DP_AUX_CTL_TIMEOUT_ERROR (1 << 28) 626 #define INTEL_DP_AUX_CTL_TIMEOUT_400us (0 << 26) 627 #define INTEL_DP_AUX_CTL_TIMEOUT_600us (1 << 26) 628 #define INTEL_DP_AUX_CTL_TIMEOUT_800us (2 << 26) 629 #define INTEL_DP_AUX_CTL_TIMEOUT_1600us (3 << 26) 630 #define INTEL_DP_AUX_CTL_TIMEOUT_MASK (3 << 26) 631 #define INTEL_DP_AUX_CTL_RECEIVE_ERROR (1 << 25) 632 #define INTEL_DP_AUX_CTL_MSG_SIZE_MASK (0x1f << 20) 633 #define INTEL_DP_AUX_CTL_MSG_SIZE_SHIFT 20 634 #define INTEL_DP_AUX_CTL_PRECHARGE_2US_MASK (0xf << 16) 635 #define INTEL_DP_AUX_CTL_PRECHARGE_2US_SHIFT 16 636 #define INTEL_DP_AUX_CTL_BIT_CLOCK_2X_MASK (0x7ff) 637 #define INTEL_DP_AUX_CTL_BIT_CLOCK_2X_SHIFT 0 638 #define INTEL_DP_AUX_CTL_SYNC_PULSE_SKL(c) ((c) - 1) 639 640 // planes 641 #define INTEL_PIPE_ENABLED (1UL << 31) 642 #define INTEL_PIPE_CONTROL 0x0008 643 #define INTEL_PIPE_STATUS 0x0024 644 645 #define INTEL_PLANE_OFFSET 0x1000 646 647 #define INTEL_DISPLAY_A_PIPE_CONTROL (0x0008 | REGS_NORTH_PLANE_CONTROL) 648 #define INTEL_DISPLAY_B_PIPE_CONTROL (0x1008 | REGS_NORTH_PLANE_CONTROL) 649 #define INTEL_DISPLAY_A_PIPE_STATUS (0x0024 | REGS_NORTH_PLANE_CONTROL) 650 #define INTEL_DISPLAY_B_PIPE_STATUS (0x1024 | REGS_NORTH_PLANE_CONTROL) 651 652 #define DISPLAY_PIPE_VBLANK_ENABLED (1UL << 17) 653 #define DISPLAY_PIPE_VBLANK_STATUS (1UL << 1) 654 655 #define INTEL_DISPLAY_A_CONTROL (0x0180 | REGS_NORTH_PLANE_CONTROL) 656 #define INTEL_DISPLAY_A_BASE (0x0184 | REGS_NORTH_PLANE_CONTROL) 657 #define INTEL_DISPLAY_A_BYTES_PER_ROW (0x0188 | REGS_NORTH_PLANE_CONTROL) 658 #define INTEL_DISPLAY_A_POS (0x018c | REGS_NORTH_PLANE_CONTROL) 659 // reserved on A 660 #define INTEL_DISPLAY_A_PIPE_SIZE (0x0190 | REGS_NORTH_PLANE_CONTROL) 661 #define INTEL_DISPLAY_A_SURFACE (0x019c | REGS_NORTH_PLANE_CONTROL) 662 // i965 and up only 663 664 #define INTEL_DISPLAY_B_CONTROL (0x1180 | REGS_NORTH_PLANE_CONTROL) 665 #define INTEL_DISPLAY_B_BASE (0x1184 | REGS_NORTH_PLANE_CONTROL) 666 #define INTEL_DISPLAY_B_BYTES_PER_ROW (0x1188 | REGS_NORTH_PLANE_CONTROL) 667 #define INTEL_DISPLAY_B_POS (0x118c | REGS_NORTH_PLANE_CONTROL) 668 #define INTEL_DISPLAY_B_PIPE_SIZE (0x1190 | REGS_NORTH_PLANE_CONTROL) 669 #define INTEL_DISPLAY_B_SURFACE (0x119c | REGS_NORTH_PLANE_CONTROL) 670 // i965 and up only 671 672 // INTEL_DISPLAY_A_CONTROL source pixel format 673 #define DISPLAY_CONTROL_ENABLED (1UL << 31) 674 #define DISPLAY_CONTROL_GAMMA (1UL << 30) 675 #define DISPLAY_CONTROL_COLOR_MASK (0x0fUL << 26) 676 #define DISPLAY_CONTROL_CMAP8 (2UL << 26) 677 #define DISPLAY_CONTROL_RGB15 (4UL << 26) 678 #define DISPLAY_CONTROL_RGB16 (5UL << 26) 679 #define DISPLAY_CONTROL_RGB32 (6UL << 26) 680 681 // INTEL_DISPLAY_A_PIPE_CONTROL ILK+ 682 #define INTEL_PIPE_DITHER_TYPE_MASK (0x0000000c) 683 #define INTEL_PIPE_DITHER_TYPE_SP (0 << 2) 684 #define INTEL_PIPE_DITHER_TYPE_ST1 (1 << 2) 685 #define INTEL_PIPE_DITHER_TYPE_ST2 (2 << 2) 686 #define INTEL_PIPE_DITHER_TYPE_TEMP (3 << 2) 687 #define INTEL_PIPE_DITHER_EN (1 << 4) 688 #define INTEL_PIPE_8BPC (0 << 5) 689 #define INTEL_PIPE_10BPC (1 << 5) 690 #define INTEL_PIPE_6BPC (2 << 5) 691 #define INTEL_PIPE_12BPC (3 << 5) 692 #define INTEL_PIPE_PROGRESSIVE (0 << 21) 693 694 // cursors 695 #define INTEL_CURSOR_CONTROL (0x0080 | REGS_NORTH_PLANE_CONTROL) 696 #define INTEL_CURSOR_BASE (0x0084 | REGS_NORTH_PLANE_CONTROL) 697 #define INTEL_CURSOR_POSITION (0x0088 | REGS_NORTH_PLANE_CONTROL) 698 #define INTEL_CURSOR_PALETTE (0x0090 | REGS_NORTH_PLANE_CONTROL) 699 // (- 0x009f) 700 #define INTEL_CURSOR_SIZE (0x00a0 | REGS_NORTH_PLANE_CONTROL) 701 #define CURSOR_ENABLED (1UL << 31) 702 #define CURSOR_FORMAT_2_COLORS (0UL << 24) 703 #define CURSOR_FORMAT_3_COLORS (1UL << 24) 704 #define CURSOR_FORMAT_4_COLORS (2UL << 24) 705 #define CURSOR_FORMAT_ARGB (4UL << 24) 706 #define CURSOR_FORMAT_XRGB (5UL << 24) 707 #define CURSOR_POSITION_NEGATIVE 0x8000 708 #define CURSOR_POSITION_MASK 0x3fff 709 710 // palette registers 711 #define INTEL_DISPLAY_A_PALETTE (0xa000 | REGS_NORTH_SHARED) 712 #define INTEL_DISPLAY_B_PALETTE (0xa800 | REGS_NORTH_SHARED) 713 714 // PLL registers 715 #define INTEL_DISPLAY_A_PLL (0x6014 | REGS_SOUTH_SHARED) 716 #define INTEL_DISPLAY_B_PLL (0x6018 | REGS_SOUTH_SHARED) 717 #define CHV_DISPLAY_C_PLL (0x6030 | REGS_SOUTH_SHARED) 718 719 // Ironlake PCH reference clk control 720 #define PCH_DREF_CONTROL (0x6200 | REGS_SOUTH_SHARED) 721 #define DREF_CONTROL_MASK 0x7fc3 722 #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0 << 13) 723 #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2 << 13) 724 #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3 << 13) 725 #define DREF_CPU_SOURCE_OUTPUT_MASK (3 << 13) 726 #define DREF_SSC_SOURCE_DISABLE (0 << 11) 727 #define DREF_SSC_SOURCE_ENABLE (2 << 11) 728 #define DREF_SSC_SOURCE_MASK (3 << 11) 729 #define DREF_NONSPREAD_SOURCE_DISABLE (0 << 9) 730 #define DREF_NONSPREAD_CK505_ENABLE (1 << 9) 731 #define DREF_NONSPREAD_SOURCE_ENABLE (2 << 9) 732 #define DREF_NONSPREAD_SOURCE_MASK (3 << 9) 733 #define DREF_SUPERSPREAD_SOURCE_DISABLE (0 << 7) 734 #define DREF_SUPERSPREAD_SOURCE_ENABLE (2 << 7) 735 #define DREF_SUPERSPREAD_SOURCE_MASK (3 << 7) 736 #define DREF_SSC4_DOWNSPREAD (0 << 6) 737 #define DREF_SSC4_CENTERSPREAD (1 << 6) 738 #define DREF_SSC1_DISABLE (0 << 1) 739 #define DREF_SSC1_ENABLE (1 << 1) 740 #define DREF_SSC4_DISABLE (0 << 0) 741 #define DREF_SSC4_ENABLE (1 << 0) 742 743 // Multiplier Divisor 744 #define INTEL_DISPLAY_A_PLL_MD (0x601C | REGS_SOUTH_SHARED) 745 #define INTEL_DISPLAY_B_PLL_MD (0x6020 | REGS_SOUTH_SHARED) 746 #define CHV_DISPLAY_B_PLL_MD (0x603C | REGS_SOUTH_SHARED) 747 748 #define INTEL_DISPLAY_A_PLL_DIVISOR_0 (0x6040 | REGS_SOUTH_SHARED) 749 #define INTEL_DISPLAY_A_PLL_DIVISOR_1 (0x6044 | REGS_SOUTH_SHARED) 750 #define INTEL_DISPLAY_B_PLL_DIVISOR_0 (0x6048 | REGS_SOUTH_SHARED) 751 #define INTEL_DISPLAY_B_PLL_DIVISOR_1 (0x604c | REGS_SOUTH_SHARED) 752 753 // i2c 754 #define INTEL_I2C_IO_A (0x5010 | REGS_SOUTH_SHARED) 755 #define INTEL_I2C_IO_B (0x5014 | REGS_SOUTH_SHARED) 756 #define INTEL_I2C_IO_C (0x5018 | REGS_SOUTH_SHARED) 757 #define INTEL_I2C_IO_D (0x501c | REGS_SOUTH_SHARED) 758 #define INTEL_I2C_IO_E (0x5020 | REGS_SOUTH_SHARED) 759 #define INTEL_I2C_IO_F (0x5024 | REGS_SOUTH_SHARED) 760 #define INTEL_I2C_IO_G (0x5028 | REGS_SOUTH_SHARED) 761 #define INTEL_I2C_IO_H (0x502c | REGS_SOUTH_SHARED) 762 763 #define I2C_CLOCK_DIRECTION_MASK (1 << 0) 764 #define I2C_CLOCK_DIRECTION_OUT (1 << 1) 765 #define I2C_CLOCK_VALUE_MASK (1 << 2) 766 #define I2C_CLOCK_VALUE_OUT (1 << 3) 767 #define I2C_CLOCK_VALUE_IN (1 << 4) 768 #define I2C_DATA_DIRECTION_MASK (1 << 8) 769 #define I2C_DATA_DIRECTION_OUT (1 << 9) 770 #define I2C_DATA_VALUE_MASK (1 << 10) 771 #define I2C_DATA_VALUE_OUT (1 << 11) 772 #define I2C_DATA_VALUE_IN (1 << 12) 773 #define I2C_RESERVED ((1 << 13) | (1 << 5)) 774 775 // TODO: on IronLake this is in the north shared block at 0x41000 776 #define INTEL_VGA_DISPLAY_CONTROL (0x1400 | REGS_NORTH_PLANE_CONTROL) 777 #define VGA_DISPLAY_DISABLED (1UL << 31) 778 779 // LVDS panel 780 #define INTEL_PANEL_STATUS (0x1200 | REGS_NORTH_PIPE_AND_PORT) 781 #define INTEL_PANEL_CONTROL (0x1204 | REGS_NORTH_PIPE_AND_PORT) 782 #define INTEL_PANEL_FIT_CONTROL (0x1230 | REGS_NORTH_PIPE_AND_PORT) 783 #define INTEL_PANEL_FIT_RATIOS (0x1234 | REGS_NORTH_PIPE_AND_PORT) 784 785 // LVDS on IronLake and up 786 #define PCH_PANEL_STATUS (0x7200 | REGS_SOUTH_SHARED) 787 #define PCH_PANEL_CONTROL (0x7204 | REGS_SOUTH_SHARED) 788 #define PCH_PANEL_ON_DELAYS (0x7208 | REGS_SOUTH_SHARED) 789 #define PCH_PANEL_OFF_DELAYS (0x720c | REGS_SOUTH_SHARED) 790 #define PCH_PANEL_DIVISOR (0x7210 | REGS_SOUTH_SHARED) 791 #define PCH_LVDS_DETECTED (1 << 1) 792 793 #define PANEL_STATUS_POWER_ON (1UL << 31) 794 #define PANEL_CONTROL_POWER_TARGET_OFF (0UL << 0) 795 #define PANEL_CONTROL_POWER_TARGET_ON (1UL << 0) 796 #define PANEL_CONTROL_POWER_TARGET_RST (1UL << 1) 797 #define PANEL_REGISTER_UNLOCK (0xabcd << 16) 798 799 // PCH_PANEL_ON_DELAYS 800 #define PANEL_DELAY_PORT_SELECT_MASK (3 << 30) 801 #define PANEL_DELAY_PORT_SELECT_LVDS (0 << 30) 802 #define PANEL_DELAY_PORT_SELECT_DPA (1 << 30) 803 #define PANEL_DELAY_PORT_SELECT_DPC (2 << 30) 804 #define PANEL_DELAY_PORT_SELECT_DPD (3 << 30) 805 806 // PCH_PANEL_DIVISOR 807 #define PANEL_DIVISOR_REFERENCE_DIV_MASK 0xffffff00 808 #define PANEL_DIVISOR_REFERENCE_DIV_SHIFT 8 809 #define PANEL_DIVISOR_POW_CYCLE_DLY_MASK 0x1f 810 #define PANEL_DIVISOR_POW_CYCLE_DLY_SHIFT 0x1f 811 812 // ring buffer commands 813 814 #define COMMAND_NOOP 0x00 815 #define COMMAND_WAIT_FOR_EVENT (0x03 << 23) 816 #define COMMAND_WAIT_FOR_OVERLAY_FLIP (1 << 16) 817 818 #define COMMAND_FLUSH (0x04 << 23) 819 820 // overlay flip 821 #define COMMAND_OVERLAY_FLIP (0x11 << 23) 822 #define COMMAND_OVERLAY_CONTINUE (0 << 21) 823 #define COMMAND_OVERLAY_ON (1 << 21) 824 #define COMMAND_OVERLAY_OFF (2 << 21) 825 #define OVERLAY_UPDATE_COEFFICIENTS 0x1 826 827 // 2D acceleration 828 #define XY_COMMAND_SOURCE_BLIT 0x54c00006 829 #define XY_COMMAND_COLOR_BLIT 0x54000004 830 #define XY_COMMAND_SETUP_MONO_PATTERN 0x44400007 831 #define XY_COMMAND_SCANLINE_BLIT 0x49400001 832 #define COMMAND_COLOR_BLIT 0x50000003 833 #define COMMAND_BLIT_RGBA 0x00300000 834 835 #define COMMAND_MODE_SOLID_PATTERN 0x80 836 #define COMMAND_MODE_CMAP8 0x00 837 #define COMMAND_MODE_RGB15 0x02 838 #define COMMAND_MODE_RGB16 0x01 839 #define COMMAND_MODE_RGB32 0x03 840 841 // overlay 842 #define INTEL_OVERLAY_UPDATE 0x30000 843 #define INTEL_OVERLAY_TEST 0x30004 844 #define INTEL_OVERLAY_STATUS 0x30008 845 #define INTEL_OVERLAY_EXTENDED_STATUS 0x3000c 846 #define INTEL_OVERLAY_GAMMA_5 0x30010 847 #define INTEL_OVERLAY_GAMMA_4 0x30014 848 #define INTEL_OVERLAY_GAMMA_3 0x30018 849 #define INTEL_OVERLAY_GAMMA_2 0x3001c 850 #define INTEL_OVERLAY_GAMMA_1 0x30020 851 #define INTEL_OVERLAY_GAMMA_0 0x30024 852 853 // FDI - Flexible Display Interface, the interface between the (CPU-internal) 854 // GPU and the PCH display outputs. Proprietary interface, based on DisplayPort 855 // though, so similar link training and all... 856 // There's an FDI transmitter (TX) on the CPU and an FDI receiver (RX) on the 857 // PCH for each display pipe. 858 // FDI receiver A is hooked up to transcoder A, FDI receiver B is hooked up to 859 // transcoder B, so we have the same mapping as with the display pipes. 860 #define PCH_FDI_RX_BASE_REGISTER 0xf0000 861 #define PCH_FDI_RX_PIPE_OFFSET 0x01000 862 #define PCH_FDI_RX_CONTROL 0x00c 863 #define PCH_FDI_RX_MISC 0x010 864 #define PCH_FDI_RX_IIR 0x014 865 #define PCH_FDI_RX_IMR 0x018 866 867 #define FDI_RX_ENABLE (1 << 31) 868 #define FDI_RX_PLL_ENABLED (1 << 13) 869 870 // FDI_tX interrupt register 871 #define FDI_RX_INTER_LANE_ALIGN (1 << 10) 872 #define FDI_RX_SYMBOL_LOCK (1 << 9) 873 #define FDI_RX_BIT_LOCK (1 << 8) 874 #define FDI_RX_TRAIN_PATTERN_2_FAIL (1 << 7) 875 #define FDI_RX_FS_CODE_ERR (1 << 6) 876 #define FDI_RX_FE_CODE_ERR (1 << 5) 877 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1 << 4) 878 #define FDI_RX_HDCP_LINK_FAIL (1 << 3) 879 #define FDI_RX_PIXEL_FIFO_OVERFLOW (1 << 2) 880 #define FDI_RX_CROSS_CLOCK_OVERFLOW (1 << 1) 881 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1 << 0) 882 883 #define FDI_FS_ERRC_ENABLE (1 << 27) 884 #define FDI_FE_ERRC_ENABLE (1 << 26) 885 886 #define PCH_FDI_RX_TRANS_UNIT_SIZE_1 0x30 887 #define PCH_FDI_RX_TRANS_UNIT_SIZE_2 0x38 888 #define FDI_RX_TRANS_UNIT_SIZE(x) ((x - 1) << 25) 889 #define FDI_RX_TRANS_UNIT_MASK 0x7e000000 890 891 #define FDI_RX_ENHANCE_FRAME_ENABLE (1 << 6) 892 #define FDI_RX_CLOCK_MASK (1 << 4) 893 #define FDI_RX_CLOCK_RAW (0 << 4) 894 #define FDI_RX_CLOCK_PCD (1 << 4) 895 896 // FDI RX MISC 897 #define FDI_RX_PWRDN_LANE1_MASK (3 << 26) 898 #define FDI_RX_PWRDN_LANE1_VAL(x) ((x) << 26) 899 #define FDI_RX_PWRDN_LANE0_MASK (3 << 24) 900 #define FDI_RX_PWRDN_LANE0_VAL(x) ((x) << 24) 901 #define FDI_RX_TP1_TO_TP2_48 (2 << 20) 902 #define FDI_RX_TP1_TO_TP2_64 (3 << 20) 903 #define FDI_RX_FDI_DELAY_90 (0x90 << 0) 904 905 #define PCH_FDI_TX_BASE_REGISTER 0x60000 906 #define PCH_FDI_TX_PIPE_OFFSET 0x01000 907 #define PCH_FDI_TX_CONTROL 0x100 908 #define FDI_TX_ENABLE (1 << 31) 909 #define FDI_LINK_TRAIN_PATTERN_1 (0 << 28) 910 #define FDI_LINK_TRAIN_PATTERN_2 (1 << 28) 911 #define FDI_LINK_TRAIN_PATTERN_IDLE (2 << 28) 912 #define FDI_LINK_TRAIN_NONE (3 << 28) 913 #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0 << 25) 914 #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1 << 25) 915 #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2 << 25) 916 #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3 << 25) 917 #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0 << 22) 918 #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1 << 22) 919 #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2 << 22) 920 #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3 << 22) 921 922 // SNB A stepping 923 #define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22) 924 #define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22) 925 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22) 926 #define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x00 << 22) 927 928 // SNB B stepping 929 #define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x00 << 22) 930 #define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a << 22) 931 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39 << 22) 932 #define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38 << 22) 933 #define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f << 22) 934 #define FDI_TX_ENHANCE_FRAME_ENABLE (1 << 18) 935 #define FDI_TX_PLL_ENABLED (1 << 14) 936 937 #define FDI_DP_PORT_WIDTH_SHIFT 19 938 #define FDI_DP_PORT_WIDTH_MASK (7 << FDI_DP_PORT_WIDTH_SHIFT) 939 #define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT) 940 941 #define FDI_PLL_BIOS_0 0x46000 942 #define FDI_PLL_FB_CLOCK_MASK 0xff 943 #define FDI_PLL_BIOS_1 0x46004 944 #define FDI_PLL_BIOS_2 0x46008 945 946 #define FDI_AUTO_TRAINING (1 << 10) 947 #define FDI_AUTO_TRAIN_DONE (1 << 1) 948 949 #define FDI_LINK_TRAIN_PATTERN_1_CPT (0 << 8) 950 #define FDI_LINK_TRAIN_PATTERN_2_CPT (1 << 8) 951 #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2 << 8) 952 #define FDI_LINK_TRAIN_NORMAL_CPT (3 << 8) 953 #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3 << 8) 954 955 // IvyBridge changes it up because... they hate developers? 956 #define FDI_LINK_TRAIN_PATTERN_1_IVB (0 << 8) 957 #define FDI_LINK_TRAIN_PATTERN_2_IVB (1 << 8) 958 #define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2 << 8) 959 #define FDI_LINK_TRAIN_NONE_IVB (3 << 8) 960 961 #define PCH_FDI_RXA_CHICKEN (0x200c | REGS_SOUTH_SHARED) 962 #define PCH_FDI_RXB_CHICKEN (0x2010 | REGS_SOUTH_SHARED) 963 #define FDI_RX_PHASE_SYNC_POINTER_EN (1 << 0) 964 #define FDI_RX_PHASE_SYNC_POINTER_OVR (1 << 1) 965 966 // CPU Panel Fitters - These are for IronLake and up and are the CPU internal 967 // panel fitters. 968 #define PCH_PANEL_FITTER_BASE_REGISTER 0x68000 969 #define PCH_PANEL_FITTER_PIPE_OFFSET 0x00800 970 971 #define PCH_PANEL_FITTER_WINDOW_POS 0x70 972 #define PCH_PANEL_FITTER_WINDOW_SIZE 0x74 973 #define PCH_PANEL_FITTER_CONTROL 0x80 974 #define PCH_PANEL_FITTER_V_SCALE 0x84 975 #define PCH_PANEL_FITTER_H_SCALE 0x90 976 977 #define PANEL_FITTER_ENABLED (1 << 31) 978 #define PANEL_FITTER_FILTER_MASK (3 << 23) 979 980 struct overlay_scale { 981 uint32 _reserved0 : 3; 982 uint32 horizontal_scale_fraction : 12; 983 uint32 _reserved1 : 1; 984 uint32 horizontal_downscale_factor : 3; 985 uint32 _reserved2 : 1; 986 uint32 vertical_scale_fraction : 12; 987 }; 988 989 #define OVERLAY_FORMAT_RGB15 0x2 990 #define OVERLAY_FORMAT_RGB16 0x3 991 #define OVERLAY_FORMAT_RGB32 0x1 992 #define OVERLAY_FORMAT_YCbCr422 0x8 993 #define OVERLAY_FORMAT_YCbCr411 0x9 994 #define OVERLAY_FORMAT_YCbCr420 0xc 995 996 #define OVERLAY_MIRROR_NORMAL 0x0 997 #define OVERLAY_MIRROR_HORIZONTAL 0x1 998 #define OVERLAY_MIRROR_VERTICAL 0x2 999 1000 // The real overlay registers are written to using an update buffer 1001 1002 struct overlay_registers { 1003 uint32 buffer_rgb0; 1004 uint32 buffer_rgb1; 1005 uint32 buffer_u0; 1006 uint32 buffer_v0; 1007 uint32 buffer_u1; 1008 uint32 buffer_v1; 1009 // (0x18) OSTRIDE - overlay stride 1010 uint16 stride_rgb; 1011 uint16 stride_uv; 1012 // (0x1c) YRGB_VPH - Y/RGB vertical phase 1013 uint16 vertical_phase0_rgb; 1014 uint16 vertical_phase1_rgb; 1015 // (0x20) UV_VPH - UV vertical phase 1016 uint16 vertical_phase0_uv; 1017 uint16 vertical_phase1_uv; 1018 // (0x24) HORZ_PH - horizontal phase 1019 uint16 horizontal_phase_rgb; 1020 uint16 horizontal_phase_uv; 1021 // (0x28) INIT_PHS - initial phase shift 1022 uint32 initial_vertical_phase0_shift_rgb0 : 4; 1023 uint32 initial_vertical_phase1_shift_rgb0 : 4; 1024 uint32 initial_horizontal_phase_shift_rgb0 : 4; 1025 uint32 initial_vertical_phase0_shift_uv : 4; 1026 uint32 initial_vertical_phase1_shift_uv : 4; 1027 uint32 initial_horizontal_phase_shift_uv : 4; 1028 uint32 _reserved0 : 8; 1029 // (0x2c) DWINPOS - destination window position 1030 uint16 window_left; 1031 uint16 window_top; 1032 // (0x30) DWINSZ - destination window size 1033 uint16 window_width; 1034 uint16 window_height; 1035 // (0x34) SWIDTH - source width 1036 uint16 source_width_rgb; 1037 uint16 source_width_uv; 1038 // (0x38) SWITDHSW - source width in 8 byte steps 1039 uint16 source_bytes_per_row_rgb; 1040 uint16 source_bytes_per_row_uv; 1041 uint16 source_height_rgb; 1042 uint16 source_height_uv; 1043 overlay_scale scale_rgb; 1044 overlay_scale scale_uv; 1045 // (0x48) OCLRC0 - overlay color correction 0 1046 uint32 brightness_correction : 8; // signed, -128 to 127 1047 uint32 _reserved1 : 10; 1048 uint32 contrast_correction : 9; // fixed point: 3.6 bits 1049 uint32 _reserved2 : 5; 1050 // (0x4c) OCLRC1 - overlay color correction 1 1051 uint32 saturation_cos_correction : 10; // fixed point: 3.7 bits 1052 uint32 _reserved3 : 6; 1053 uint32 saturation_sin_correction : 11; // signed fixed point: 3.7 bits 1054 uint32 _reserved4 : 5; 1055 // (0x50) DCLRKV - destination color key value 1056 uint32 color_key_blue : 8; 1057 uint32 color_key_green : 8; 1058 uint32 color_key_red : 8; 1059 uint32 _reserved5 : 8; 1060 // (0x54) DCLRKM - destination color key mask 1061 uint32 color_key_mask_blue : 8; 1062 uint32 color_key_mask_green : 8; 1063 uint32 color_key_mask_red : 8; 1064 uint32 _reserved6 : 7; 1065 uint32 color_key_enabled : 1; 1066 // (0x58) SCHRKVH - source chroma key high value 1067 uint32 source_chroma_key_high_red : 8; 1068 uint32 source_chroma_key_high_blue : 8; 1069 uint32 source_chroma_key_high_green : 8; 1070 uint32 _reserved7 : 8; 1071 // (0x5c) SCHRKVL - source chroma key low value 1072 uint32 source_chroma_key_low_red : 8; 1073 uint32 source_chroma_key_low_blue : 8; 1074 uint32 source_chroma_key_low_green : 8; 1075 uint32 _reserved8 : 8; 1076 // (0x60) SCHRKEN - source chroma key enable 1077 uint32 _reserved9 : 24; 1078 uint32 source_chroma_key_red_enabled : 1; 1079 uint32 source_chroma_key_blue_enabled : 1; 1080 uint32 source_chroma_key_green_enabled : 1; 1081 uint32 _reserved10 : 5; 1082 // (0x64) OCONFIG - overlay configuration 1083 uint32 _reserved11 : 3; 1084 uint32 color_control_output_mode : 1; 1085 uint32 yuv_to_rgb_bypass : 1; 1086 uint32 _reserved12 : 11; 1087 uint32 gamma2_enabled : 1; 1088 uint32 _reserved13 : 1; 1089 uint32 select_pipe : 1; 1090 uint32 slot_time : 8; 1091 uint32 _reserved14 : 5; 1092 // (0x68) OCOMD - overlay command 1093 uint32 overlay_enabled : 1; 1094 uint32 active_field : 1; 1095 uint32 active_buffer : 2; 1096 uint32 test_mode : 1; 1097 uint32 buffer_field_mode : 1; 1098 uint32 _reserved15 : 1; 1099 uint32 tv_flip_field_enabled : 1; 1100 uint32 _reserved16 : 1; 1101 uint32 tv_flip_field_parity : 1; 1102 uint32 source_format : 4; 1103 uint32 ycbcr422_order : 2; 1104 uint32 _reserved18 : 1; 1105 uint32 mirroring_mode : 2; 1106 uint32 _reserved19 : 13; 1107 1108 uint32 _reserved20; 1109 1110 uint32 start_0y; 1111 uint32 start_1y; 1112 uint32 start_0u; 1113 uint32 start_0v; 1114 uint32 start_1u; 1115 uint32 start_1v; 1116 uint32 _reserved21[6]; 1117 #if 0 1118 // (0x70) AWINPOS - alpha blend window position 1119 uint32 awinpos; 1120 // (0x74) AWINSZ - alpha blend window size 1121 uint32 awinsz; 1122 1123 uint32 _reserved21[10]; 1124 #endif 1125 1126 // (0xa0) FASTHSCALE - fast horizontal downscale (strangely enough, 1127 // the next two registers switch the usual Y/RGB vs. UV order) 1128 uint16 horizontal_scale_uv; 1129 uint16 horizontal_scale_rgb; 1130 // (0xa4) UVSCALEV - vertical downscale 1131 uint16 vertical_scale_uv; 1132 uint16 vertical_scale_rgb; 1133 1134 uint32 _reserved22[86]; 1135 1136 // (0x200) polyphase filter coefficients 1137 uint16 vertical_coefficients_rgb[128]; 1138 uint16 horizontal_coefficients_rgb[128]; 1139 1140 uint32 _reserved23[64]; 1141 1142 // (0x500) 1143 uint16 vertical_coefficients_uv[128]; 1144 uint16 horizontal_coefficients_uv[128]; 1145 }; 1146 1147 // i965 overlay support is currently realized using its 3D hardware 1148 #define INTEL_i965_OVERLAY_STATE_SIZE 36864 1149 #define INTEL_i965_3D_CONTEXT_SIZE 32768 1150 1151 inline bool 1152 intel_uses_physical_overlay(intel_shared_info &info) 1153 { 1154 return !info.device_type.InGroup(INTEL_GROUP_Gxx); 1155 } 1156 1157 1158 struct hardware_status { 1159 uint32 interrupt_status_register; 1160 uint32 _reserved0[3]; 1161 void* primary_ring_head_storage; 1162 uint32 _reserved1[3]; 1163 void* secondary_ring_0_head_storage; 1164 void* secondary_ring_1_head_storage; 1165 uint32 _reserved2[2]; 1166 void* binning_head_storage; 1167 uint32 _reserved3[3]; 1168 uint32 store[1008]; 1169 }; 1170 1171 #endif /* INTEL_EXTREME_H */ 1172