1 /* 2 * Copyright 2006-2009, Haiku, Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Axel Dörfler, axeld@pinc-software.de 7 */ 8 #ifndef INTEL_EXTREME_H 9 #define INTEL_EXTREME_H 10 11 12 #include "lock.h" 13 14 #include <Accelerant.h> 15 #include <Drivers.h> 16 #include <PCI.h> 17 18 19 #define VENDOR_ID_INTEL 0x8086 20 21 #define INTEL_TYPE_FAMILY_MASK 0x000f0000 22 #define INTEL_TYPE_GROUP_MASK 0x000ffff0 23 #define INTEL_TYPE_MODEL_MASK 0x000fffff 24 // families 25 #define INTEL_TYPE_7xx 0x00010000 26 #define INTEL_TYPE_8xx 0x00020000 27 #define INTEL_TYPE_9xx 0x00040000 28 // groups 29 #define INTEL_TYPE_83x (INTEL_TYPE_8xx | 0x0010) 30 #define INTEL_TYPE_85x (INTEL_TYPE_8xx | 0x0020) 31 #define INTEL_TYPE_91x (INTEL_TYPE_9xx | 0x0040) 32 #define INTEL_TYPE_94x (INTEL_TYPE_9xx | 0x0080) 33 #define INTEL_TYPE_96x (INTEL_TYPE_9xx | 0x0100) 34 #define INTEL_TYPE_Gxx (INTEL_TYPE_9xx | 0x0200) 35 #define INTEL_TYPE_G4x (INTEL_TYPE_9xx | 0x0400) 36 #define INTEL_TYPE_IGD (INTEL_TYPE_9xx | 0x0800) 37 #define INTEL_TYPE_ILK (INTEL_TYPE_9xx | 0x1000) 38 #define INTEL_TYPE_SNB (INTEL_TYPE_9xx | 0x2000) 39 #define INTEL_TYPE_IVB (INTEL_TYPE_9xx | 0x4000) 40 // models 41 #define INTEL_TYPE_SERVER 0x0004 42 #define INTEL_TYPE_MOBILE 0x0008 43 #define INTEL_TYPE_915 (INTEL_TYPE_91x) 44 #define INTEL_TYPE_915M (INTEL_TYPE_91x | INTEL_TYPE_MOBILE) 45 #define INTEL_TYPE_945 (INTEL_TYPE_94x) 46 #define INTEL_TYPE_945M (INTEL_TYPE_94x | INTEL_TYPE_MOBILE) 47 #define INTEL_TYPE_965 (INTEL_TYPE_96x) 48 #define INTEL_TYPE_965M (INTEL_TYPE_96x | INTEL_TYPE_MOBILE) 49 #define INTEL_TYPE_G33 (INTEL_TYPE_Gxx) 50 #define INTEL_TYPE_G45 (INTEL_TYPE_G4x) 51 #define INTEL_TYPE_GM45 (INTEL_TYPE_G4x | INTEL_TYPE_MOBILE) 52 #define INTEL_TYPE_IGDG (INTEL_TYPE_IGD) 53 #define INTEL_TYPE_IGDGM (INTEL_TYPE_IGD | INTEL_TYPE_MOBILE) 54 #define INTEL_TYPE_ILKG (INTEL_TYPE_ILK) 55 #define INTEL_TYPE_ILKGM (INTEL_TYPE_ILK | INTEL_TYPE_MOBILE) 56 #define INTEL_TYPE_SNBG (INTEL_TYPE_SNB) 57 #define INTEL_TYPE_SNBGM (INTEL_TYPE_SNB | INTEL_TYPE_MOBILE) 58 #define INTEL_TYPE_SNBGS (INTEL_TYPE_SNB | INTEL_TYPE_SERVER) 59 #define INTEL_TYPE_IVBG (INTEL_TYPE_IVB) 60 #define INTEL_TYPE_IVBGM (INTEL_TYPE_IVB | INTEL_TYPE_MOBILE) 61 #define INTEL_TYPE_IVBGS (INTEL_TYPE_IVB | INTEL_TYPE_SERVER) 62 63 #define DEVICE_NAME "intel_extreme" 64 #define INTEL_ACCELERANT_NAME "intel_extreme.accelerant" 65 66 // We encode the register block into the value and extract/translate it when 67 // actually accessing. 68 #define REGISTER_BLOCK_COUNT 6 69 #define REGISTER_BLOCK_SHIFT 24 70 #define REGISTER_BLOCK_MASK 0xff000000 71 #define REGISTER_REGISTER_MASK 0x00ffffff 72 #define REGISTER_BLOCK(x) ((x & REGISTER_BLOCK_MASK) >> REGISTER_BLOCK_SHIFT) 73 #define REGISTER_REGISTER(x) (x & REGISTER_REGISTER_MASK) 74 75 #define REGS_FLAT (0 << REGISTER_BLOCK_SHIFT) 76 #define REGS_NORTH_SHARED (1 << REGISTER_BLOCK_SHIFT) 77 #define REGS_NORTH_PIPE_AND_PORT (2 << REGISTER_BLOCK_SHIFT) 78 #define REGS_NORTH_PLANE_CONTROL (3 << REGISTER_BLOCK_SHIFT) 79 #define REGS_SOUTH_SHARED (4 << REGISTER_BLOCK_SHIFT) 80 #define REGS_SOUTH_TRANSCODER_PORT (5 << REGISTER_BLOCK_SHIFT) 81 82 // register blocks for (G)MCH/ICH based platforms 83 #define MCH_SHARED_REGISTER_BASE 0x00000 84 #define MCH_PIPE_AND_PORT_REGISTER_BASE 0x60000 85 #define MCH_PLANE_CONTROL_REGISTER_BASE 0x70000 86 #define ICH_SHARED_REGISTER_BASE 0x00000 87 #define ICH_PORT_REGISTER_BASE 0x60000 88 89 // PCH - Platform Control Hub - Newer hardware moves from a MCH/ICH based setup 90 // to a PCH based one, that means anything that used to communicate via (G)MCH 91 // registers needs to use different ones on PCH based platforms (Ironlake and 92 // up, SandyBridge, etc.). 93 #define PCH_NORTH_SHARED_REGISTER_BASE 0x40000 94 #define PCH_NORTH_PIPE_AND_PORT_REGISTER_BASE 0x60000 95 #define PCH_NORTH_PLANE_CONTROL_REGISTER_BASE 0x70000 96 #define PCH_SOUTH_SHARED_REGISTER_BASE 0xc0000 97 #define PCH_SOUTH_TRANSCODER_AND_PORT_REGISTER_BASE 0xe0000 98 99 100 struct DeviceType { 101 uint32 type; 102 103 DeviceType(int t) 104 { 105 type = t; 106 } 107 108 DeviceType& operator=(int t) 109 { 110 type = t; 111 return *this; 112 } 113 114 bool InFamily(uint32 family) const 115 { 116 return (type & INTEL_TYPE_FAMILY_MASK) == family; 117 } 118 119 bool InGroup(uint32 group) const 120 { 121 return (type & INTEL_TYPE_GROUP_MASK) == group; 122 } 123 124 bool IsModel(uint32 model) const 125 { 126 return (type & INTEL_TYPE_MODEL_MASK) == model; 127 } 128 129 bool HasPlatformControlHub() const 130 { 131 return InGroup(INTEL_TYPE_ILK) || InGroup(INTEL_TYPE_SNB) 132 || InGroup(INTEL_TYPE_IVB); 133 } 134 }; 135 136 // info about PLL on graphics card 137 struct pll_info { 138 uint32 reference_frequency; 139 uint32 max_frequency; 140 uint32 min_frequency; 141 uint32 divisor_register; 142 }; 143 144 struct ring_buffer { 145 struct lock lock; 146 uint32 register_base; 147 uint32 offset; 148 uint32 size; 149 uint32 position; 150 uint32 space_left; 151 uint8* base; 152 }; 153 154 struct overlay_registers; 155 156 struct intel_shared_info { 157 area_id mode_list_area; // area containing display mode list 158 uint32 mode_count; 159 160 display_mode current_mode; 161 uint32 bytes_per_row; 162 uint32 bits_per_pixel; 163 uint32 dpms_mode; 164 165 area_id registers_area; // area of memory mapped registers 166 uint32 register_blocks[REGISTER_BLOCK_COUNT]; 167 uint8* status_page; 168 phys_addr_t physical_status_page; 169 uint8* graphics_memory; 170 phys_addr_t physical_graphics_memory; 171 uint32 graphics_memory_size; 172 173 addr_t frame_buffer; 174 uint32 frame_buffer_offset; 175 176 bool got_vbt; 177 bool single_head_locked; 178 179 struct lock accelerant_lock; 180 struct lock engine_lock; 181 182 ring_buffer primary_ring_buffer; 183 184 int32 overlay_channel_used; 185 bool overlay_active; 186 uint32 overlay_token; 187 phys_addr_t physical_overlay_registers; 188 uint32 overlay_offset; 189 190 bool hardware_cursor_enabled; 191 sem_id vblank_sem; 192 193 uint8* cursor_memory; 194 phys_addr_t physical_cursor_memory; 195 uint32 cursor_buffer_offset; 196 uint32 cursor_format; 197 bool cursor_visible; 198 uint16 cursor_hot_x; 199 uint16 cursor_hot_y; 200 201 DeviceType device_type; 202 char device_identifier[32]; 203 struct pll_info pll_info; 204 }; 205 206 //----------------- ioctl() interface ---------------- 207 208 // magic code for ioctls 209 #define INTEL_PRIVATE_DATA_MAGIC 'itic' 210 211 // list ioctls 212 enum { 213 INTEL_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1, 214 215 INTEL_GET_DEVICE_NAME, 216 INTEL_ALLOCATE_GRAPHICS_MEMORY, 217 INTEL_FREE_GRAPHICS_MEMORY 218 }; 219 220 // retrieve the area_id of the kernel/accelerant shared info 221 struct intel_get_private_data { 222 uint32 magic; // magic number 223 area_id shared_info_area; 224 }; 225 226 // allocate graphics memory 227 struct intel_allocate_graphics_memory { 228 uint32 magic; 229 uint32 size; 230 uint32 alignment; 231 uint32 flags; 232 addr_t buffer_base; 233 }; 234 235 // free graphics memory 236 struct intel_free_graphics_memory { 237 uint32 magic; 238 addr_t buffer_base; 239 }; 240 241 //---------------------------------------------------------- 242 // Register definitions, taken from X driver 243 244 // PCI bridge memory management 245 #define INTEL_GRAPHICS_MEMORY_CONTROL 0x52 246 // GGC - (G)MCH Graphics Control Register 247 #define MEMORY_CONTROL_ENABLED 0x0004 248 #define MEMORY_MASK 0x0001 249 #define STOLEN_MEMORY_MASK 0x00f0 250 #define i965_GTT_MASK 0x000e 251 #define G33_GTT_MASK 0x0300 252 #define G4X_GTT_MASK 0x0f00 // GGMS (GSM Memory Size) mask 253 254 // models i830 and up 255 #define i830_LOCAL_MEMORY_ONLY 0x10 256 #define i830_STOLEN_512K 0x20 257 #define i830_STOLEN_1M 0x30 258 #define i830_STOLEN_8M 0x40 259 #define i830_FRAME_BUFFER_64M 0x01 260 #define i830_FRAME_BUFFER_128M 0x00 261 262 // models i855 and up 263 #define i855_STOLEN_MEMORY_1M 0x10 264 #define i855_STOLEN_MEMORY_4M 0x20 265 #define i855_STOLEN_MEMORY_8M 0x30 266 #define i855_STOLEN_MEMORY_16M 0x40 267 #define i855_STOLEN_MEMORY_32M 0x50 268 #define i855_STOLEN_MEMORY_48M 0x60 269 #define i855_STOLEN_MEMORY_64M 0x70 270 #define i855_STOLEN_MEMORY_128M 0x80 271 #define i855_STOLEN_MEMORY_256M 0x90 272 273 #define G4X_STOLEN_MEMORY_96MB 0xa0 // GMS - Graphics Mode Select 274 #define G4X_STOLEN_MEMORY_160MB 0xb0 275 #define G4X_STOLEN_MEMORY_224MB 0xc0 276 #define G4X_STOLEN_MEMORY_352MB 0xd0 277 278 // SandyBridge (SNB) 279 #define SNB_GRAPHICS_MEMORY_CONTROL 0x50 280 281 #define SNB_STOLEN_MEMORY_MASK 0xf8 282 #define SNB_STOLEN_MEMORY_32MB (1 << 3) 283 #define SNB_STOLEN_MEMORY_64MB (2 << 3) 284 #define SNB_STOLEN_MEMORY_96MB (3 << 3) 285 #define SNB_STOLEN_MEMORY_128MB (4 << 3) 286 #define SNB_STOLEN_MEMORY_160MB (5 << 3) 287 #define SNB_STOLEN_MEMORY_192MB (6 << 3) 288 #define SNB_STOLEN_MEMORY_224MB (7 << 3) 289 #define SNB_STOLEN_MEMORY_256MB (8 << 3) 290 #define SNB_STOLEN_MEMORY_288MB (9 << 3) 291 #define SNB_STOLEN_MEMORY_320MB (10 << 3) 292 #define SNB_STOLEN_MEMORY_352MB (11 << 3) 293 #define SNB_STOLEN_MEMORY_384MB (12 << 3) 294 #define SNB_STOLEN_MEMORY_416MB (13 << 3) 295 #define SNB_STOLEN_MEMORY_448MB (14 << 3) 296 #define SNB_STOLEN_MEMORY_480MB (15 << 3) 297 #define SNB_STOLEN_MEMORY_512MB (16 << 3) 298 299 #define SNB_GTT_SIZE_MASK (3 << 8) 300 #define SNB_GTT_SIZE_NONE (0 << 8) 301 #define SNB_GTT_SIZE_1MB (1 << 8) 302 #define SNB_GTT_SIZE_2MB (2 << 8) 303 304 // graphics page translation table 305 #define INTEL_PAGE_TABLE_CONTROL 0x02020 306 #define PAGE_TABLE_ENABLED 0x00000001 307 #define INTEL_PAGE_TABLE_ERROR 0x02024 308 #define INTEL_HARDWARE_STATUS_PAGE 0x02080 309 #define i915_GTT_BASE 0x1c 310 #define i830_GTT_BASE 0x10000 // (- 0x2ffff) 311 #define i830_GTT_SIZE 0x20000 312 #define i965_GTT_BASE 0x80000 // (- 0xfffff) 313 #define i965_GTT_SIZE 0x80000 314 #define i965_GTT_128K (2 << 1) 315 #define i965_GTT_256K (1 << 1) 316 #define i965_GTT_512K (0 << 1) 317 #define G33_GTT_1M (1 << 8) 318 #define G33_GTT_2M (2 << 8) 319 #define G4X_GTT_NONE 0x000 // GGMS - GSM Memory Size 320 #define G4X_GTT_1M_NO_IVT 0x100 // no Intel Virtualization Tech. 321 #define G4X_GTT_2M_NO_IVT 0x300 322 #define G4X_GTT_2M_IVT 0x900 // with Intel Virt. Tech. 323 #define G4X_GTT_3M_IVT 0xa00 324 #define G4X_GTT_4M_IVT 0xb00 325 326 327 #define GTT_ENTRY_VALID 0x01 328 #define GTT_ENTRY_LOCAL_MEMORY 0x02 329 #define GTT_PAGE_SHIFT 12 330 331 332 // ring buffer 333 #define INTEL_PRIMARY_RING_BUFFER 0x02030 334 #define INTEL_SECONDARY_RING_BUFFER_0 0x02100 335 #define INTEL_SECONDARY_RING_BUFFER_1 0x02110 336 // offsets for the ring buffer base registers above 337 #define RING_BUFFER_TAIL 0x0 338 #define RING_BUFFER_HEAD 0x4 339 #define RING_BUFFER_START 0x8 340 #define RING_BUFFER_CONTROL 0xc 341 #define INTEL_RING_BUFFER_SIZE_MASK 0x001ff000 342 #define INTEL_RING_BUFFER_HEAD_MASK 0x001ffffc 343 #define INTEL_RING_BUFFER_ENABLED 1 344 345 // interrupts 346 #define INTEL_INTERRUPT_ENABLED 0x020a0 347 #define INTEL_INTERRUPT_IDENTITY 0x020a4 348 #define INTEL_INTERRUPT_MASK 0x020a8 349 #define INTEL_INTERRUPT_STATUS 0x020ac 350 #define INTERRUPT_VBLANK_PIPEA (1 << 7) 351 #define INTERRUPT_VBLANK_PIPEB (1 << 5) 352 353 // PCH interrupts 354 #define PCH_INTERRUPT_STATUS 0x44000 355 #define PCH_INTERRUPT_MASK 0x44004 356 #define PCH_INTERRUPT_IDENTITY 0x44008 357 #define PCH_INTERRUPT_ENABLED 0x4400c 358 #define PCH_INTERRUPT_VBLANK_PIPEA (1 << 7) 359 #define PCH_INTERRUPT_VBLANK_PIPEB (1 << 15) 360 361 // display ports 362 #define INTEL_DISPLAY_A_ANALOG_PORT (0x1100 | REGS_SOUTH_TRANSCODER_PORT) 363 #define DISPLAY_MONITOR_PORT_ENABLED (1UL << 31) 364 #define DISPLAY_MONITOR_PIPE_B (1UL << 30) 365 #define DISPLAY_MONITOR_VGA_POLARITY (1UL << 15) 366 #define DISPLAY_MONITOR_MODE_MASK (3UL << 10) 367 #define DISPLAY_MONITOR_ON 0 368 #define DISPLAY_MONITOR_SUSPEND (1UL << 10) 369 #define DISPLAY_MONITOR_STAND_BY (2UL << 10) 370 #define DISPLAY_MONITOR_OFF (3UL << 10) 371 #define DISPLAY_MONITOR_POLARITY_MASK (3UL << 3) 372 #define DISPLAY_MONITOR_POSITIVE_HSYNC (1UL << 3) 373 #define DISPLAY_MONITOR_POSITIVE_VSYNC (2UL << 3) 374 #define INTEL_DISPLAY_A_DIGITAL_PORT (0x1120 | REGS_SOUTH_TRANSCODER_PORT) 375 #define INTEL_DISPLAY_C_DIGITAL (0x1160 | REGS_SOUTH_TRANSCODER_PORT) 376 #define INTEL_DISPLAY_LVDS_PORT (0x1180 | REGS_SOUTH_TRANSCODER_PORT) 377 #define LVDS_POST2_RATE_SLOW 14 // PLL Divisors 378 #define LVDS_POST2_RATE_FAST 7 379 #define LVDS_CLKB_POWER_MASK (3 << 4) 380 #define LVDS_CLKB_POWER_UP (3 << 4) 381 #define LVDS_PORT_EN (1 << 31) 382 #define LVDS_A0A2_CLKA_POWER_UP (3 << 8) 383 #define LVDS_PIPEB_SELECT (1 << 30) 384 #define LVDS_B0B3PAIRS_POWER_UP (3 << 2) 385 #define LVDS_PLL_MODE_LVDS (2 << 26) 386 #define LVDS_18BIT_DITHER (1 << 25) 387 388 // PLL flags 389 #define DISPLAY_PLL_ENABLED (1UL << 31) 390 #define DISPLAY_PLL_2X_CLOCK (1UL << 30) 391 #define DISPLAY_PLL_SYNC_LOCK_ENABLED (1UL << 29) 392 #define DISPLAY_PLL_NO_VGA_CONTROL (1UL << 28) 393 #define DISPLAY_PLL_MODE_ANALOG (1UL << 26) 394 #define DISPLAY_PLL_DIVIDE_HIGH (1UL << 24) 395 #define DISPLAY_PLL_DIVIDE_4X (1UL << 23) 396 #define DISPLAY_PLL_POST1_DIVIDE_2 (1UL << 21) 397 #define DISPLAY_PLL_POST1_DIVISOR_MASK 0x001f0000 398 #define DISPLAY_PLL_9xx_POST1_DIVISOR_MASK 0x00ff0000 399 #define DISPLAY_PLL_IGD_POST1_DIVISOR_MASK 0x00ff8000 400 #define DISPLAY_PLL_POST1_DIVISOR_SHIFT 16 401 #define DISPLAY_PLL_IGD_POST1_DIVISOR_SHIFT 15 402 #define DISPLAY_PLL_DIVISOR_1 (1UL << 8) 403 #define DISPLAY_PLL_N_DIVISOR_MASK 0x001f0000 404 #define DISPLAY_PLL_IGD_N_DIVISOR_MASK 0x00ff0000 405 #define DISPLAY_PLL_M1_DIVISOR_MASK 0x00001f00 406 #define DISPLAY_PLL_M2_DIVISOR_MASK 0x0000001f 407 #define DISPLAY_PLL_IGD_M2_DIVISOR_MASK 0x000000ff 408 #define DISPLAY_PLL_N_DIVISOR_SHIFT 16 409 #define DISPLAY_PLL_M1_DIVISOR_SHIFT 8 410 #define DISPLAY_PLL_M2_DIVISOR_SHIFT 0 411 #define DISPLAY_PLL_PULSE_PHASE_SHIFT 9 412 413 // display 414 #define INTEL_DISPLAY_A_HTOTAL (0x0000 | REGS_SOUTH_TRANSCODER_PORT) 415 #define INTEL_DISPLAY_A_HBLANK (0x0004 | REGS_SOUTH_TRANSCODER_PORT) 416 #define INTEL_DISPLAY_A_HSYNC (0x0008 | REGS_SOUTH_TRANSCODER_PORT) 417 #define INTEL_DISPLAY_A_VTOTAL (0x000c | REGS_SOUTH_TRANSCODER_PORT) 418 #define INTEL_DISPLAY_A_VBLANK (0x0010 | REGS_SOUTH_TRANSCODER_PORT) 419 #define INTEL_DISPLAY_A_VSYNC (0x0014 | REGS_SOUTH_TRANSCODER_PORT) 420 #define INTEL_DISPLAY_B_HTOTAL (0x1000 | REGS_SOUTH_TRANSCODER_PORT) 421 #define INTEL_DISPLAY_B_HBLANK (0x1004 | REGS_SOUTH_TRANSCODER_PORT) 422 #define INTEL_DISPLAY_B_HSYNC (0x1008 | REGS_SOUTH_TRANSCODER_PORT) 423 #define INTEL_DISPLAY_B_VTOTAL (0x100c | REGS_SOUTH_TRANSCODER_PORT) 424 #define INTEL_DISPLAY_B_VBLANK (0x1010 | REGS_SOUTH_TRANSCODER_PORT) 425 #define INTEL_DISPLAY_B_VSYNC (0x1014 | REGS_SOUTH_TRANSCODER_PORT) 426 427 #define INTEL_DISPLAY_A_IMAGE_SIZE (0x001c | REGS_NORTH_PIPE_AND_PORT) 428 #define INTEL_DISPLAY_B_IMAGE_SIZE (0x101c | REGS_NORTH_PIPE_AND_PORT) 429 430 #define INTEL_DISPLAY_B_DIGITAL_PORT (0x1140 | REGS_SOUTH_TRANSCODER_PORT) 431 432 // planes 433 #define INTEL_DISPLAY_A_PIPE_CONTROL (0x0008 | REGS_NORTH_PLANE_CONTROL) 434 #define INTEL_DISPLAY_B_PIPE_CONTROL (0x1008 | REGS_NORTH_PLANE_CONTROL) 435 #define DISPLAY_PIPE_ENABLED (1UL << 31) 436 437 #define INTEL_DISPLAY_A_PIPE_STATUS (0x0024 | REGS_NORTH_PLANE_CONTROL) 438 #define INTEL_DISPLAY_B_PIPE_STATUS (0x1024 | REGS_NORTH_PLANE_CONTROL) 439 #define DISPLAY_PIPE_VBLANK_ENABLED (1UL << 17) 440 #define DISPLAY_PIPE_VBLANK_STATUS (1UL << 1) 441 442 #define INTEL_DISPLAY_A_CONTROL (0x0180 | REGS_NORTH_PLANE_CONTROL) 443 #define INTEL_DISPLAY_A_BASE (0x0184 | REGS_NORTH_PLANE_CONTROL) 444 #define INTEL_DISPLAY_A_BYTES_PER_ROW (0x0188 | REGS_NORTH_PLANE_CONTROL) 445 #define INTEL_DISPLAY_A_POS (0x018c | REGS_NORTH_PLANE_CONTROL) 446 // reserved on A 447 #define INTEL_DISPLAY_A_PIPE_SIZE (0x0190 | REGS_NORTH_PLANE_CONTROL) 448 #define INTEL_DISPLAY_A_SURFACE (0x019c | REGS_NORTH_PLANE_CONTROL) 449 // i965 and up only 450 451 #define INTEL_DISPLAY_B_CONTROL (0x1180 | REGS_NORTH_PLANE_CONTROL) 452 #define INTEL_DISPLAY_B_BASE (0x1184 | REGS_NORTH_PLANE_CONTROL) 453 #define INTEL_DISPLAY_B_BYTES_PER_ROW (0x1188 | REGS_NORTH_PLANE_CONTROL) 454 #define INTEL_DISPLAY_B_POS (0x118c | REGS_NORTH_PLANE_CONTROL) 455 #define INTEL_DISPLAY_B_PIPE_SIZE (0x1190 | REGS_NORTH_PLANE_CONTROL) 456 #define INTEL_DISPLAY_B_SURFACE (0x119c | REGS_NORTH_PLANE_CONTROL) 457 // i965 and up only 458 459 #define DISPLAY_CONTROL_ENABLED (1UL << 31) 460 #define DISPLAY_CONTROL_GAMMA (1UL << 30) 461 #define DISPLAY_CONTROL_COLOR_MASK (0x0fUL << 26) 462 #define DISPLAY_CONTROL_CMAP8 (2UL << 26) 463 #define DISPLAY_CONTROL_RGB15 (4UL << 26) 464 #define DISPLAY_CONTROL_RGB16 (5UL << 26) 465 #define DISPLAY_CONTROL_RGB32 (6UL << 26) 466 467 // cursors 468 #define INTEL_CURSOR_CONTROL (0x0080 | REGS_NORTH_PLANE_CONTROL) 469 #define INTEL_CURSOR_BASE (0x0084 | REGS_NORTH_PLANE_CONTROL) 470 #define INTEL_CURSOR_POSITION (0x0088 | REGS_NORTH_PLANE_CONTROL) 471 #define INTEL_CURSOR_PALETTE (0x0090 | REGS_NORTH_PLANE_CONTROL) 472 // (- 0x009f) 473 #define INTEL_CURSOR_SIZE (0x00a0 | REGS_NORTH_PLANE_CONTROL) 474 #define CURSOR_ENABLED (1UL << 31) 475 #define CURSOR_FORMAT_2_COLORS (0UL << 24) 476 #define CURSOR_FORMAT_3_COLORS (1UL << 24) 477 #define CURSOR_FORMAT_4_COLORS (2UL << 24) 478 #define CURSOR_FORMAT_ARGB (4UL << 24) 479 #define CURSOR_FORMAT_XRGB (5UL << 24) 480 #define CURSOR_POSITION_NEGATIVE 0x8000 481 #define CURSOR_POSITION_MASK 0x3fff 482 483 // palette registers 484 #define INTEL_DISPLAY_A_PALETTE (0xa000 | REGS_NORTH_SHARED) 485 #define INTEL_DISPLAY_B_PALETTE (0xa800 | REGS_NORTH_SHARED) 486 487 // PLL registers 488 #define INTEL_DISPLAY_A_PLL (0x6014 | REGS_SOUTH_SHARED) 489 #define INTEL_DISPLAY_B_PLL (0x6018 | REGS_SOUTH_SHARED) 490 #define INTEL_DISPLAY_A_PLL_MULTIPLIER_DIVISOR \ 491 (0x601c | REGS_SOUTH_SHARED) 492 #define INTEL_DISPLAY_B_PLL_MULTIPLIER_DIVISOR \ 493 (0x6020 | REGS_SOUTH_SHARED) 494 #define INTEL_DISPLAY_A_PLL_DIVISOR_0 (0x6040 | REGS_SOUTH_SHARED) 495 #define INTEL_DISPLAY_A_PLL_DIVISOR_1 (0x6044 | REGS_SOUTH_SHARED) 496 #define INTEL_DISPLAY_B_PLL_DIVISOR_0 (0x6048 | REGS_SOUTH_SHARED) 497 #define INTEL_DISPLAY_B_PLL_DIVISOR_1 (0x604c | REGS_SOUTH_SHARED) 498 499 // i2c 500 #define INTEL_I2C_IO_A (0x5010 | REGS_SOUTH_SHARED) 501 #define INTEL_I2C_IO_B (0x5014 | REGS_SOUTH_SHARED) 502 #define INTEL_I2C_IO_C (0x5018 | REGS_SOUTH_SHARED) 503 #define INTEL_I2C_IO_D (0x501c | REGS_SOUTH_SHARED) 504 #define INTEL_I2C_IO_E (0x5020 | REGS_SOUTH_SHARED) 505 #define INTEL_I2C_IO_F (0x5024 | REGS_SOUTH_SHARED) 506 #define INTEL_I2C_IO_G (0x5028 | REGS_SOUTH_SHARED) 507 #define INTEL_I2C_IO_H (0x502c | REGS_SOUTH_SHARED) 508 509 #define I2C_CLOCK_DIRECTION_MASK (1 << 0) 510 #define I2C_CLOCK_DIRECTION_OUT (1 << 1) 511 #define I2C_CLOCK_VALUE_MASK (1 << 2) 512 #define I2C_CLOCK_VALUE_OUT (1 << 3) 513 #define I2C_CLOCK_VALUE_IN (1 << 4) 514 #define I2C_DATA_DIRECTION_MASK (1 << 8) 515 #define I2C_DATA_DIRECTION_OUT (1 << 9) 516 #define I2C_DATA_VALUE_MASK (1 << 10) 517 #define I2C_DATA_VALUE_OUT (1 << 11) 518 #define I2C_DATA_VALUE_IN (1 << 12) 519 #define I2C_RESERVED ((1 << 13) | (1 << 5)) 520 521 // TODO: on IronLake this is in the north shared block at 0x41000 522 #define INTEL_VGA_DISPLAY_CONTROL 0x71400 523 #define VGA_DISPLAY_DISABLED (1UL << 31) 524 525 // LVDS panel 526 #define INTEL_PANEL_STATUS 0x61200 527 #define PANEL_STATUS_POWER_ON (1UL << 31) 528 #define INTEL_PANEL_CONTROL 0x61204 529 #define PANEL_CONTROL_POWER_TARGET_ON (1UL << 0) 530 #define INTEL_PANEL_FIT_CONTROL 0x61230 531 #define INTEL_PANEL_FIT_RATIOS 0x61234 532 533 // LVDS on IronLake and up 534 #define PCH_PANEL_CONTROL 0xc7200 535 #define PCH_PANEL_STATUS 0xc7204 536 #define PANEL_REGISTER_UNLOCK (0xabcd << 16) 537 #define PCH_LVDS_DETECTED (1 << 1) 538 539 540 // ring buffer commands 541 542 #define COMMAND_NOOP 0x00 543 #define COMMAND_WAIT_FOR_EVENT (0x03 << 23) 544 #define COMMAND_WAIT_FOR_OVERLAY_FLIP (1 << 16) 545 546 #define COMMAND_FLUSH (0x04 << 23) 547 548 // overlay flip 549 #define COMMAND_OVERLAY_FLIP (0x11 << 23) 550 #define COMMAND_OVERLAY_CONTINUE (0 << 21) 551 #define COMMAND_OVERLAY_ON (1 << 21) 552 #define COMMAND_OVERLAY_OFF (2 << 21) 553 #define OVERLAY_UPDATE_COEFFICIENTS 0x1 554 555 // 2D acceleration 556 #define XY_COMMAND_SOURCE_BLIT 0x54c00006 557 #define XY_COMMAND_COLOR_BLIT 0x54000004 558 #define XY_COMMAND_SETUP_MONO_PATTERN 0x44400007 559 #define XY_COMMAND_SCANLINE_BLIT 0x49400001 560 #define COMMAND_COLOR_BLIT 0x50000003 561 #define COMMAND_BLIT_RGBA 0x00300000 562 563 #define COMMAND_MODE_SOLID_PATTERN 0x80 564 #define COMMAND_MODE_CMAP8 0x00 565 #define COMMAND_MODE_RGB15 0x02 566 #define COMMAND_MODE_RGB16 0x01 567 #define COMMAND_MODE_RGB32 0x03 568 569 // overlay 570 #define INTEL_OVERLAY_UPDATE 0x30000 571 #define INTEL_OVERLAY_TEST 0x30004 572 #define INTEL_OVERLAY_STATUS 0x30008 573 #define INTEL_OVERLAY_EXTENDED_STATUS 0x3000c 574 #define INTEL_OVERLAY_GAMMA_5 0x30010 575 #define INTEL_OVERLAY_GAMMA_4 0x30014 576 #define INTEL_OVERLAY_GAMMA_3 0x30018 577 #define INTEL_OVERLAY_GAMMA_2 0x3001c 578 #define INTEL_OVERLAY_GAMMA_1 0x30020 579 #define INTEL_OVERLAY_GAMMA_0 0x30024 580 581 struct overlay_scale { 582 uint32 _reserved0 : 3; 583 uint32 horizontal_scale_fraction : 12; 584 uint32 _reserved1 : 1; 585 uint32 horizontal_downscale_factor : 3; 586 uint32 _reserved2 : 1; 587 uint32 vertical_scale_fraction : 12; 588 }; 589 590 #define OVERLAY_FORMAT_RGB15 0x2 591 #define OVERLAY_FORMAT_RGB16 0x3 592 #define OVERLAY_FORMAT_RGB32 0x1 593 #define OVERLAY_FORMAT_YCbCr422 0x8 594 #define OVERLAY_FORMAT_YCbCr411 0x9 595 #define OVERLAY_FORMAT_YCbCr420 0xc 596 597 #define OVERLAY_MIRROR_NORMAL 0x0 598 #define OVERLAY_MIRROR_HORIZONTAL 0x1 599 #define OVERLAY_MIRROR_VERTICAL 0x2 600 601 // The real overlay registers are written to using an update buffer 602 603 struct overlay_registers { 604 uint32 buffer_rgb0; 605 uint32 buffer_rgb1; 606 uint32 buffer_u0; 607 uint32 buffer_v0; 608 uint32 buffer_u1; 609 uint32 buffer_v1; 610 // (0x18) OSTRIDE - overlay stride 611 uint16 stride_rgb; 612 uint16 stride_uv; 613 // (0x1c) YRGB_VPH - Y/RGB vertical phase 614 uint16 vertical_phase0_rgb; 615 uint16 vertical_phase1_rgb; 616 // (0x20) UV_VPH - UV vertical phase 617 uint16 vertical_phase0_uv; 618 uint16 vertical_phase1_uv; 619 // (0x24) HORZ_PH - horizontal phase 620 uint16 horizontal_phase_rgb; 621 uint16 horizontal_phase_uv; 622 // (0x28) INIT_PHS - initial phase shift 623 uint32 initial_vertical_phase0_shift_rgb0 : 4; 624 uint32 initial_vertical_phase1_shift_rgb0 : 4; 625 uint32 initial_horizontal_phase_shift_rgb0 : 4; 626 uint32 initial_vertical_phase0_shift_uv : 4; 627 uint32 initial_vertical_phase1_shift_uv : 4; 628 uint32 initial_horizontal_phase_shift_uv : 4; 629 uint32 _reserved0 : 8; 630 // (0x2c) DWINPOS - destination window position 631 uint16 window_left; 632 uint16 window_top; 633 // (0x30) DWINSZ - destination window size 634 uint16 window_width; 635 uint16 window_height; 636 // (0x34) SWIDTH - source width 637 uint16 source_width_rgb; 638 uint16 source_width_uv; 639 // (0x38) SWITDHSW - source width in 8 byte steps 640 uint16 source_bytes_per_row_rgb; 641 uint16 source_bytes_per_row_uv; 642 uint16 source_height_rgb; 643 uint16 source_height_uv; 644 overlay_scale scale_rgb; 645 overlay_scale scale_uv; 646 // (0x48) OCLRC0 - overlay color correction 0 647 uint32 brightness_correction : 8; // signed, -128 to 127 648 uint32 _reserved1 : 10; 649 uint32 contrast_correction : 9; // fixed point: 3.6 bits 650 uint32 _reserved2 : 5; 651 // (0x4c) OCLRC1 - overlay color correction 1 652 uint32 saturation_cos_correction : 10; // fixed point: 3.7 bits 653 uint32 _reserved3 : 6; 654 uint32 saturation_sin_correction : 11; // signed fixed point: 3.7 bits 655 uint32 _reserved4 : 5; 656 // (0x50) DCLRKV - destination color key value 657 uint32 color_key_blue : 8; 658 uint32 color_key_green : 8; 659 uint32 color_key_red : 8; 660 uint32 _reserved5 : 8; 661 // (0x54) DCLRKM - destination color key mask 662 uint32 color_key_mask_blue : 8; 663 uint32 color_key_mask_green : 8; 664 uint32 color_key_mask_red : 8; 665 uint32 _reserved6 : 7; 666 uint32 color_key_enabled : 1; 667 // (0x58) SCHRKVH - source chroma key high value 668 uint32 source_chroma_key_high_red : 8; 669 uint32 source_chroma_key_high_blue : 8; 670 uint32 source_chroma_key_high_green : 8; 671 uint32 _reserved7 : 8; 672 // (0x5c) SCHRKVL - source chroma key low value 673 uint32 source_chroma_key_low_red : 8; 674 uint32 source_chroma_key_low_blue : 8; 675 uint32 source_chroma_key_low_green : 8; 676 uint32 _reserved8 : 8; 677 // (0x60) SCHRKEN - source chroma key enable 678 uint32 _reserved9 : 24; 679 uint32 source_chroma_key_red_enabled : 1; 680 uint32 source_chroma_key_blue_enabled : 1; 681 uint32 source_chroma_key_green_enabled : 1; 682 uint32 _reserved10 : 5; 683 // (0x64) OCONFIG - overlay configuration 684 uint32 _reserved11 : 3; 685 uint32 color_control_output_mode : 1; 686 uint32 yuv_to_rgb_bypass : 1; 687 uint32 _reserved12 : 11; 688 uint32 gamma2_enabled : 1; 689 uint32 _reserved13 : 1; 690 uint32 select_pipe : 1; 691 uint32 slot_time : 8; 692 uint32 _reserved14 : 5; 693 // (0x68) OCOMD - overlay command 694 uint32 overlay_enabled : 1; 695 uint32 active_field : 1; 696 uint32 active_buffer : 2; 697 uint32 test_mode : 1; 698 uint32 buffer_field_mode : 1; 699 uint32 _reserved15 : 1; 700 uint32 tv_flip_field_enabled : 1; 701 uint32 _reserved16 : 1; 702 uint32 tv_flip_field_parity : 1; 703 uint32 source_format : 4; 704 uint32 ycbcr422_order : 2; 705 uint32 _reserved18 : 1; 706 uint32 mirroring_mode : 2; 707 uint32 _reserved19 : 13; 708 709 uint32 _reserved20; 710 711 uint32 start_0y; 712 uint32 start_1y; 713 uint32 start_0u; 714 uint32 start_0v; 715 uint32 start_1u; 716 uint32 start_1v; 717 uint32 _reserved21[6]; 718 #if 0 719 // (0x70) AWINPOS - alpha blend window position 720 uint32 awinpos; 721 // (0x74) AWINSZ - alpha blend window size 722 uint32 awinsz; 723 724 uint32 _reserved21[10]; 725 #endif 726 727 // (0xa0) FASTHSCALE - fast horizontal downscale (strangely enough, 728 // the next two registers switch the usual Y/RGB vs. UV order) 729 uint16 horizontal_scale_uv; 730 uint16 horizontal_scale_rgb; 731 // (0xa4) UVSCALEV - vertical downscale 732 uint16 vertical_scale_uv; 733 uint16 vertical_scale_rgb; 734 735 uint32 _reserved22[86]; 736 737 // (0x200) polyphase filter coefficients 738 uint16 vertical_coefficients_rgb[128]; 739 uint16 horizontal_coefficients_rgb[128]; 740 741 uint32 _reserved23[64]; 742 743 // (0x500) 744 uint16 vertical_coefficients_uv[128]; 745 uint16 horizontal_coefficients_uv[128]; 746 }; 747 748 // i965 overlay support is currently realized using its 3D hardware 749 #define INTEL_i965_OVERLAY_STATE_SIZE 36864 750 #define INTEL_i965_3D_CONTEXT_SIZE 32768 751 752 inline bool 753 intel_uses_physical_overlay(intel_shared_info &info) 754 { 755 return !info.device_type.InGroup(INTEL_TYPE_Gxx); 756 } 757 758 759 struct hardware_status { 760 uint32 interrupt_status_register; 761 uint32 _reserved0[3]; 762 void* primary_ring_head_storage; 763 uint32 _reserved1[3]; 764 void* secondary_ring_0_head_storage; 765 void* secondary_ring_1_head_storage; 766 uint32 _reserved2[2]; 767 void* binning_head_storage; 768 uint32 _reserved3[3]; 769 uint32 store[1008]; 770 }; 771 772 #endif /* INTEL_EXTREME_H */ 773