1 /* 2 * Copyright 2006-2016, Haiku, Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Axel Dörfler, axeld@pinc-software.de 7 * Alexander von Gluck, kallisti5@unixzen.com 8 */ 9 #ifndef INTEL_EXTREME_H 10 #define INTEL_EXTREME_H 11 12 13 #include "lock.h" 14 15 #include <Accelerant.h> 16 #include <Drivers.h> 17 #include <PCI.h> 18 19 #include <edid.h> 20 21 22 #define VENDOR_ID_INTEL 0x8086 23 24 #define INTEL_FAMILY_MASK 0x00ff0000 25 #define INTEL_GROUP_MASK 0x00fffff0 26 #define INTEL_MODEL_MASK 0x00ffffff 27 #define INTEL_TYPE_MASK 0x0000000f 28 29 // families 30 #define INTEL_FAMILY_8xx 0x00020000 // Second Gen 31 #define INTEL_FAMILY_9xx 0x00040000 // Third Gen + 32 #define INTEL_FAMILY_SER5 0x00080000 // Intel5 Series 33 #define INTEL_FAMILY_SOC0 0x00200000 // Atom SOC 34 #define INTEL_FAMILY_LAKE 0x00400000 // Intel Lakes 35 36 // groups 37 #define INTEL_GROUP_83x (INTEL_FAMILY_8xx | 0x0010) 38 #define INTEL_GROUP_85x (INTEL_FAMILY_8xx | 0x0020) 39 #define INTEL_GROUP_91x (INTEL_FAMILY_9xx | 0x0010) 40 #define INTEL_GROUP_94x (INTEL_FAMILY_9xx | 0x0020) 41 #define INTEL_GROUP_96x (INTEL_FAMILY_9xx | 0x0040) 42 #define INTEL_GROUP_Gxx (INTEL_FAMILY_9xx | 0x0080) 43 #define INTEL_GROUP_G4x (INTEL_FAMILY_9xx | 0x0100) 44 #define INTEL_GROUP_PIN (INTEL_FAMILY_9xx | 0x0200) // PineView 45 #define INTEL_GROUP_ILK (INTEL_FAMILY_SER5 | 0x0010) // IronLake 46 #define INTEL_GROUP_SNB (INTEL_FAMILY_SER5 | 0x0020) // SandyBridge 47 #define INTEL_GROUP_IVB (INTEL_FAMILY_SER5 | 0x0040) // IvyBridge 48 #define INTEL_GROUP_HAS (INTEL_FAMILY_SER5 | 0x0080) // Haswell 49 #define INTEL_GROUP_VLV (INTEL_FAMILY_SOC0 | 0x0010) // ValleyView 50 #define INTEL_GROUP_CHV (INTEL_FAMILY_SOC0 | 0x0020) // CherryView 51 #define INTEL_GROUP_BDW (INTEL_FAMILY_SOC0 | 0x0040) // Broadwell 52 #define INTEL_GROUP_SKY (INTEL_FAMILY_LAKE | 0x0010) // SkyLake 53 #define INTEL_GROUP_KBY (INTEL_FAMILY_LAKE | 0x0020) // KabyLake 54 #define INTEL_GROUP_CFL (INTEL_FAMILY_LAKE | 0x0040) // CoffeeLake 55 #define INTEL_GROUP_CML (INTEL_FAMILY_LAKE | 0x0080) // CometLake 56 #define INTEL_GROUP_JSL (INTEL_FAMILY_LAKE | 0x0100) // JasperLake 57 #define INTEL_GROUP_TGL (INTEL_FAMILY_LAKE | 0x0200) // TigerLake 58 // models 59 #define INTEL_TYPE_SERVER 0x0004 60 #define INTEL_TYPE_MOBILE 0x0008 61 #define INTEL_MODEL_915 (INTEL_GROUP_91x) 62 #define INTEL_MODEL_915M (INTEL_GROUP_91x | INTEL_TYPE_MOBILE) 63 #define INTEL_MODEL_945 (INTEL_GROUP_94x) 64 #define INTEL_MODEL_945M (INTEL_GROUP_94x | INTEL_TYPE_MOBILE) 65 #define INTEL_MODEL_965 (INTEL_GROUP_96x) 66 #define INTEL_MODEL_965M (INTEL_GROUP_96x | INTEL_TYPE_MOBILE) 67 #define INTEL_MODEL_G33 (INTEL_GROUP_Gxx) 68 #define INTEL_MODEL_G45 (INTEL_GROUP_G4x) 69 #define INTEL_MODEL_GM45 (INTEL_GROUP_G4x | INTEL_TYPE_MOBILE) 70 #define INTEL_MODEL_PINE (INTEL_GROUP_PIN) 71 #define INTEL_MODEL_PINEM (INTEL_GROUP_PIN | INTEL_TYPE_MOBILE) 72 #define INTEL_MODEL_ILKG (INTEL_GROUP_ILK) 73 #define INTEL_MODEL_ILKGM (INTEL_GROUP_ILK | INTEL_TYPE_MOBILE) 74 #define INTEL_MODEL_SNBG (INTEL_GROUP_SNB) 75 #define INTEL_MODEL_SNBGM (INTEL_GROUP_SNB | INTEL_TYPE_MOBILE) 76 #define INTEL_MODEL_SNBGS (INTEL_GROUP_SNB | INTEL_TYPE_SERVER) 77 #define INTEL_MODEL_IVBG (INTEL_GROUP_IVB) 78 #define INTEL_MODEL_IVBGM (INTEL_GROUP_IVB | INTEL_TYPE_MOBILE) 79 #define INTEL_MODEL_IVBGS (INTEL_GROUP_IVB | INTEL_TYPE_SERVER) 80 #define INTEL_MODEL_HAS (INTEL_GROUP_HAS) 81 #define INTEL_MODEL_HASM (INTEL_GROUP_HAS | INTEL_TYPE_MOBILE) 82 #define INTEL_MODEL_VLV (INTEL_GROUP_VLV) 83 #define INTEL_MODEL_VLVM (INTEL_GROUP_VLV | INTEL_TYPE_MOBILE) 84 #define INTEL_MODEL_BDW (INTEL_GROUP_BDW) 85 #define INTEL_MODEL_BDWM (INTEL_GROUP_BDW | INTEL_TYPE_MOBILE) 86 #define INTEL_MODEL_BDWS (INTEL_GROUP_BDW | INTEL_TYPE_SERVER) 87 #define INTEL_MODEL_SKY (INTEL_GROUP_SKY) 88 #define INTEL_MODEL_SKYM (INTEL_GROUP_SKY | INTEL_TYPE_MOBILE) 89 #define INTEL_MODEL_SKYS (INTEL_GROUP_SKY | INTEL_TYPE_SERVER) 90 #define INTEL_MODEL_KBY (INTEL_GROUP_KBY) 91 #define INTEL_MODEL_KBYM (INTEL_GROUP_KBY | INTEL_TYPE_MOBILE) 92 #define INTEL_MODEL_CFL (INTEL_GROUP_CFL) 93 #define INTEL_MODEL_CFLM (INTEL_GROUP_CFL | INTEL_TYPE_MOBILE) 94 #define INTEL_MODEL_CML (INTEL_GROUP_CML) 95 #define INTEL_MODEL_JSL (INTEL_GROUP_JSL) 96 #define INTEL_MODEL_JSLM (INTEL_GROUP_JSL | INTEL_TYPE_MOBILE) 97 #define INTEL_MODEL_TGLM (INTEL_GROUP_TGL | INTEL_TYPE_MOBILE) 98 99 #define INTEL_PCH_DEVICE_ID_MASK 0xff80 100 #define INTEL_PCH_IBX_DEVICE_ID 0x3b00 101 #define INTEL_PCH_CPT_DEVICE_ID 0x1c00 102 #define INTEL_PCH_PPT_DEVICE_ID 0x1e00 103 #define INTEL_PCH_LPT_DEVICE_ID 0x8c00 104 #define INTEL_PCH_LPT_LP_DEVICE_ID 0x9c00 105 #define INTEL_PCH_WPT_DEVICE_ID 0x8c80 106 #define INTEL_PCH_WPT_LP_DEVICE_ID 0x9c80 107 #define INTEL_PCH_SPT_DEVICE_ID 0xa100 108 #define INTEL_PCH_SPT_LP_DEVICE_ID 0x9d00 109 #define INTEL_PCH_KBP_DEVICE_ID 0xa280 110 #define INTEL_PCH_CNP_DEVICE_ID 0xa300 111 #define INTEL_PCH_CNP_LP_DEVICE_ID 0x9d80 112 #define INTEL_PCH_CMP_DEVICE_ID 0x0280 113 #define INTEL_PCH_CMP2_DEVICE_ID 0x0680 114 #define INTEL_PCH_CMP_V_DEVICE_ID 0xa380 115 #define INTEL_PCH_ICP_DEVICE_ID 0x3480 116 #define INTEL_PCH_MCC_DEVICE_ID 0x4b00 117 #define INTEL_PCH_TGP_DEVICE_ID 0xa080 118 #define INTEL_PCH_TGP2_DEVICE_ID 0x4380 119 #define INTEL_PCH_JSP_DEVICE_ID 0x4d80 120 #define INTEL_PCH_JSP2_DEVICE_ID 0x3880 121 #define INTEL_PCH_ADP_DEVICE_ID 0x7a80 122 #define INTEL_PCH_ADP2_DEVICE_ID 0x5180 123 #define INTEL_PCH_P2X_DEVICE_ID 0x7100 124 #define INTEL_PCH_P3X_DEVICE_ID 0x7000 125 126 // ValleyView MMIO offset 127 #define VLV_DISPLAY_BASE 0x180000 128 129 #define DEVICE_NAME "intel_extreme" 130 #define INTEL_ACCELERANT_NAME "intel_extreme.accelerant" 131 132 // We encode the register block into the value and extract/translate it when 133 // actually accessing. 134 #define REGISTER_BLOCK_COUNT 6 135 #define REGISTER_BLOCK_SHIFT 24 136 #define REGISTER_BLOCK_MASK 0xff000000 137 #define REGISTER_REGISTER_MASK 0x00ffffff 138 #define REGISTER_BLOCK(x) ((x & REGISTER_BLOCK_MASK) >> REGISTER_BLOCK_SHIFT) 139 #define REGISTER_REGISTER(x) (x & REGISTER_REGISTER_MASK) 140 141 #define REGS_FLAT (0 << REGISTER_BLOCK_SHIFT) 142 #define REGS_NORTH_SHARED (1 << REGISTER_BLOCK_SHIFT) 143 #define REGS_NORTH_PIPE_AND_PORT (2 << REGISTER_BLOCK_SHIFT) 144 #define REGS_NORTH_PLANE_CONTROL (3 << REGISTER_BLOCK_SHIFT) 145 #define REGS_SOUTH_SHARED (4 << REGISTER_BLOCK_SHIFT) 146 #define REGS_SOUTH_TRANSCODER_PORT (5 << REGISTER_BLOCK_SHIFT) 147 148 // register blocks for (G)MCH/ICH based platforms 149 #define MCH_SHARED_REGISTER_BASE 0x00000 150 #define MCH_PIPE_AND_PORT_REGISTER_BASE 0x60000 151 #define MCH_PLANE_CONTROL_REGISTER_BASE 0x70000 152 153 #define ICH_SHARED_REGISTER_BASE 0x00000 154 #define ICH_PORT_REGISTER_BASE 0x60000 155 156 // PCH - Platform Control Hub - Some hardware moves from a MCH/ICH based 157 // setup to a PCH based one, that means anything that used to communicate via 158 // (G)MCH registers needs to use different ones on PCH based platforms 159 // (Ironlake, SandyBridge, IvyBridge, Some Haswell). 160 #define PCH_NORTH_SHARED_REGISTER_BASE 0x40000 161 #define PCH_NORTH_PIPE_AND_PORT_REGISTER_BASE 0x60000 162 #define PCH_NORTH_PLANE_CONTROL_REGISTER_BASE 0x70000 163 #define PCH_SOUTH_SHARED_REGISTER_BASE 0xc0000 164 #define PCH_SOUTH_TRANSCODER_AND_PORT_REGISTER_BASE 0xe0000 165 166 167 struct DeviceType { 168 uint32 type; 169 170 DeviceType(int t) 171 { 172 type = t; 173 } 174 175 DeviceType& operator=(int t) 176 { 177 type = t; 178 return *this; 179 } 180 181 bool InFamily(uint32 family) const 182 { 183 return (type & INTEL_FAMILY_MASK) == family; 184 } 185 186 bool InGroup(uint32 group) const 187 { 188 return (type & INTEL_GROUP_MASK) == group; 189 } 190 191 bool IsModel(uint32 model) const 192 { 193 return (type & INTEL_MODEL_MASK) == model; 194 } 195 196 bool IsMobile() const 197 { 198 return (type & INTEL_TYPE_MASK) == INTEL_TYPE_MOBILE; 199 } 200 201 bool SupportsHDMI() const 202 { 203 return InGroup(INTEL_GROUP_G4x) || InFamily(INTEL_FAMILY_SER5) 204 || InFamily(INTEL_FAMILY_SOC0); 205 } 206 207 bool HasDDI() const 208 { 209 // Intel Digital Display Interface 210 return InGroup(INTEL_GROUP_HAS) || (Generation() >= 8); 211 } 212 213 int Generation() const 214 { 215 if (InFamily(INTEL_FAMILY_8xx)) 216 return 2; 217 if (InGroup(INTEL_GROUP_91x) || InGroup(INTEL_GROUP_94x) 218 || IsModel(INTEL_MODEL_G33) || InGroup(INTEL_GROUP_PIN)) 219 return 3; 220 if (InFamily(INTEL_FAMILY_9xx)) 221 return 4; 222 if (InGroup(INTEL_GROUP_ILK)) 223 return 5; 224 if (InGroup(INTEL_GROUP_SNB)) 225 return 6; 226 if (InFamily(INTEL_FAMILY_SER5) || InGroup(INTEL_GROUP_VLV)) 227 return 7; 228 if (InGroup(INTEL_GROUP_CHV) || InGroup(INTEL_GROUP_BDW)) 229 return 8; 230 if (InGroup(INTEL_GROUP_JSL)) 231 return 11; 232 if (InGroup(INTEL_GROUP_TGL)) 233 return 12; 234 if (InFamily(INTEL_FAMILY_LAKE)) 235 return 9; 236 237 // Generation 0 means something is wrong :-) 238 return 0; 239 } 240 }; 241 242 enum port_index { 243 INTEL_PORT_ANY, // wildcard for lookup functions 244 INTEL_PORT_A, 245 INTEL_PORT_B, 246 INTEL_PORT_C, 247 INTEL_PORT_D, 248 INTEL_PORT_E, 249 INTEL_PORT_F 250 }; 251 252 enum pch_info { 253 INTEL_PCH_NONE = 0, // No PCH present 254 INTEL_PCH_IBX, // Ibexpeak 255 INTEL_PCH_CPT, // Cougarpoint 256 INTEL_PCH_LPT, // Lynxpoint 257 INTEL_PCH_SPT, // SunrisePoint 258 INTEL_PCH_CNP, // CannonLake 259 INTEL_PCH_ICP, // IceLake 260 INTEL_PCH_JSP, // JasperLake 261 INTEL_PCH_MCC, // Mule Creek Canyon 262 INTEL_PCH_TGP, // TigerLake 263 INTEL_PCH_ADP, // AlderLake 264 INTEL_PCH_NOP 265 }; 266 267 // info about PLL on graphics card 268 struct pll_info { 269 uint32 reference_frequency; 270 uint32 max_frequency; 271 uint32 min_frequency; 272 uint32 divisor_register; 273 }; 274 275 struct ring_buffer { 276 struct lock lock; 277 uint32 register_base; 278 uint32 offset; 279 uint32 size; 280 uint32 position; 281 uint32 space_left; 282 uint8* base; 283 }; 284 285 struct overlay_registers; 286 287 struct intel_shared_info { 288 area_id mode_list_area; // area containing display mode list 289 uint32 mode_count; 290 291 display_mode current_mode; // pretty much a hack until per-display modes 292 display_timing panel_timing; // Hardware timings of the LVDS panel, extracted from BIOS 293 uint32 bytes_per_row; 294 uint32 bits_per_pixel; 295 uint32 dpms_mode; 296 uint16 min_brightness; 297 298 area_id registers_area; // area of memory mapped registers 299 uint32 register_blocks[REGISTER_BLOCK_COUNT]; 300 301 uint8* status_page; 302 phys_addr_t physical_status_page; 303 uint8* graphics_memory; 304 phys_addr_t physical_graphics_memory; 305 uint32 graphics_memory_size; 306 307 addr_t frame_buffer; 308 uint32 frame_buffer_offset; 309 310 uint32 fdi_link_frequency; // In Mhz 311 312 bool got_vbt; 313 bool single_head_locked; 314 315 struct lock accelerant_lock; 316 struct lock engine_lock; 317 318 ring_buffer primary_ring_buffer; 319 320 int32 overlay_channel_used; 321 bool overlay_active; 322 uintptr_t overlay_token; 323 phys_addr_t physical_overlay_registers; 324 uint32 overlay_offset; 325 326 bool hardware_cursor_enabled; 327 sem_id vblank_sem; 328 329 uint8* cursor_memory; 330 phys_addr_t physical_cursor_memory; 331 uint32 cursor_buffer_offset; 332 uint32 cursor_format; 333 bool cursor_visible; 334 uint16 cursor_hot_x; 335 uint16 cursor_hot_y; 336 337 DeviceType device_type; 338 char device_identifier[32]; 339 struct pll_info pll_info; 340 341 enum pch_info pch_info; 342 343 edid1_info vesa_edid_info; 344 bool has_vesa_edid_info; 345 }; 346 347 enum pipe_index { 348 INTEL_PIPE_ANY, 349 INTEL_PIPE_A, 350 INTEL_PIPE_B, 351 INTEL_PIPE_C, 352 INTEL_PIPE_D 353 }; 354 355 class pipes { 356 public: 357 pipes() : bitmask(0) {} 358 359 bool HasPipe(pipe_index pipe) 360 { 361 if (pipe == INTEL_PIPE_ANY) 362 return bitmask != 0; 363 364 return (bitmask & (1 << pipe)) != 0; 365 } 366 367 void SetPipe(pipe_index pipe) 368 { 369 if (pipe == INTEL_PIPE_ANY) { 370 bitmask = ~1; 371 // first bit corresponds to INTEL_PIPE_ANY but it's never used, 372 // so it should be 0 373 } 374 bitmask |= (1 << pipe); 375 } 376 377 void ClearPipe(pipe_index pipe) 378 { 379 if (pipe == INTEL_PIPE_ANY) 380 bitmask = 0; 381 382 bitmask &= ~(1 << pipe); 383 } 384 385 private: 386 uint8 bitmask; 387 }; 388 389 //----------------- ioctl() interface ---------------- 390 391 // magic code for ioctls 392 #define INTEL_PRIVATE_DATA_MAGIC 'itic' 393 394 // list ioctls 395 enum { 396 INTEL_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1, 397 398 INTEL_GET_DEVICE_NAME, 399 INTEL_ALLOCATE_GRAPHICS_MEMORY, 400 INTEL_FREE_GRAPHICS_MEMORY 401 }; 402 403 // retrieve the area_id of the kernel/accelerant shared info 404 struct intel_get_private_data { 405 uint32 magic; // magic number 406 area_id shared_info_area; 407 }; 408 409 // allocate graphics memory 410 struct intel_allocate_graphics_memory { 411 uint32 magic; 412 uint32 size; 413 uint32 alignment; 414 uint32 flags; 415 addr_t buffer_base; 416 }; 417 418 // free graphics memory 419 struct intel_free_graphics_memory { 420 uint32 magic; 421 addr_t buffer_base; 422 }; 423 424 //---------------------------------------------------------- 425 // Register definitions, taken from X driver 426 427 // PCI bridge memory management 428 #define INTEL_GRAPHICS_MEMORY_CONTROL 0x52 // i830+ 429 430 // GGC - (G)MCH Graphics Control Register 431 #define MEMORY_CONTROL_ENABLED 0x0004 432 #define MEMORY_MASK 0x0001 433 #define STOLEN_MEMORY_MASK 0x00f0 434 #define i965_GTT_MASK 0x000e 435 #define G33_GTT_MASK 0x0300 436 #define G4X_GTT_MASK 0x0f00 // GGMS (GSM Memory Size) mask 437 438 // models i830 and up 439 #define i830_LOCAL_MEMORY_ONLY 0x10 440 #define i830_STOLEN_512K 0x20 441 #define i830_STOLEN_1M 0x30 442 #define i830_STOLEN_8M 0x40 443 #define i830_FRAME_BUFFER_64M 0x01 444 #define i830_FRAME_BUFFER_128M 0x00 445 446 // models i855 and up 447 #define i855_STOLEN_MEMORY_1M 0x10 448 #define i855_STOLEN_MEMORY_4M 0x20 449 #define i855_STOLEN_MEMORY_8M 0x30 450 #define i855_STOLEN_MEMORY_16M 0x40 451 #define i855_STOLEN_MEMORY_32M 0x50 452 #define i855_STOLEN_MEMORY_48M 0x60 453 #define i855_STOLEN_MEMORY_64M 0x70 454 #define i855_STOLEN_MEMORY_128M 0x80 455 #define i855_STOLEN_MEMORY_256M 0x90 456 457 #define G4X_STOLEN_MEMORY_96MB 0xa0 // GMS - Graphics Mode Select 458 #define G4X_STOLEN_MEMORY_160MB 0xb0 459 #define G4X_STOLEN_MEMORY_224MB 0xc0 460 #define G4X_STOLEN_MEMORY_352MB 0xd0 461 462 // SandyBridge (SNB) 463 464 #define SNB_GRAPHICS_MEMORY_CONTROL 0x50 465 466 #define SNB_STOLEN_MEMORY_MASK 0xf8 467 #define SNB_STOLEN_MEMORY_32MB (1 << 3) 468 #define SNB_STOLEN_MEMORY_64MB (2 << 3) 469 #define SNB_STOLEN_MEMORY_96MB (3 << 3) 470 #define SNB_STOLEN_MEMORY_128MB (4 << 3) 471 #define SNB_STOLEN_MEMORY_160MB (5 << 3) 472 #define SNB_STOLEN_MEMORY_192MB (6 << 3) 473 #define SNB_STOLEN_MEMORY_224MB (7 << 3) 474 #define SNB_STOLEN_MEMORY_256MB (8 << 3) 475 #define SNB_STOLEN_MEMORY_288MB (9 << 3) 476 #define SNB_STOLEN_MEMORY_320MB (10 << 3) 477 #define SNB_STOLEN_MEMORY_352MB (11 << 3) 478 #define SNB_STOLEN_MEMORY_384MB (12 << 3) 479 #define SNB_STOLEN_MEMORY_416MB (13 << 3) 480 #define SNB_STOLEN_MEMORY_448MB (14 << 3) 481 #define SNB_STOLEN_MEMORY_480MB (15 << 3) 482 #define SNB_STOLEN_MEMORY_512MB (16 << 3) 483 484 #define SNB_GTT_SIZE_MASK (3 << 8) 485 #define SNB_GTT_SIZE_NONE (0 << 8) 486 #define SNB_GTT_SIZE_1MB (1 << 8) 487 #define SNB_GTT_SIZE_2MB (2 << 8) 488 489 // BDW+ (GGC_0_0_0_PCI) 490 491 #define BDW_GRAPHICS_MEMORY_CONTROL 0x50 492 493 #define BDW_STOLEN_MEMORY_MASK 0xff00 494 #define BDW_STOLEN_MEMORY_32MB (1 << 8) 495 #define BDW_STOLEN_MEMORY_64MB (2 << 8) 496 #define BDW_STOLEN_MEMORY_96MB (3 << 8) 497 #define BDW_STOLEN_MEMORY_128MB (4 << 8) 498 #define BDW_STOLEN_MEMORY_160MB (5 << 8) 499 #define BDW_STOLEN_MEMORY_192MB (6 << 8) 500 #define BDW_STOLEN_MEMORY_224MB (7 << 8) 501 #define BDW_STOLEN_MEMORY_256MB (8 << 8) 502 #define BDW_STOLEN_MEMORY_288MB (9 << 8) 503 #define BDW_STOLEN_MEMORY_320MB (10 << 8) 504 #define BDW_STOLEN_MEMORY_352MB (11 << 8) 505 #define BDW_STOLEN_MEMORY_384MB (12 << 8) 506 #define BDW_STOLEN_MEMORY_416MB (13 << 8) 507 #define BDW_STOLEN_MEMORY_448MB (14 << 8) 508 #define BDW_STOLEN_MEMORY_480MB (15 << 8) 509 #define BDW_STOLEN_MEMORY_512MB (16 << 8) 510 #define BDW_STOLEN_MEMORY_1024MB (32 << 8) 511 #define BDW_STOLEN_MEMORY_1536MB (48 << 8) 512 #define BDW_STOLEN_MEMORY_2016MB (63 << 8) 513 #define SKL_STOLEN_MEMORY_2048MB (64 << 8) 514 #define SKL_STOLEN_MEMORY_4MB (240 << 8) 515 #define SKL_STOLEN_MEMORY_8MB (241 << 8) 516 #define SKL_STOLEN_MEMORY_12MB (242 << 8) 517 #define SKL_STOLEN_MEMORY_16MB (243 << 8) 518 #define SKL_STOLEN_MEMORY_20MB (244 << 8) 519 #define SKL_STOLEN_MEMORY_24MB (245 << 8) 520 #define SKL_STOLEN_MEMORY_28MB (246 << 8) 521 #define SKL_STOLEN_MEMORY_32MB (247 << 8) 522 #define SKL_STOLEN_MEMORY_36MB (248 << 8) 523 #define SKL_STOLEN_MEMORY_40MB (249 << 8) 524 #define SKL_STOLEN_MEMORY_44MB (250 << 8) 525 #define SKL_STOLEN_MEMORY_48MB (251 << 8) 526 #define SKL_STOLEN_MEMORY_52MB (252 << 8) 527 #define SKL_STOLEN_MEMORY_56MB (253 << 8) 528 #define SKL_STOLEN_MEMORY_60MB (254 << 8) 529 530 531 #define BDW_GTT_SIZE_MASK (3 << 6) 532 #define BDW_GTT_SIZE_NONE (0 << 6) 533 #define BDW_GTT_SIZE_2MB (1 << 6) 534 #define BDW_GTT_SIZE_4MB (2 << 6) 535 #define BDW_GTT_SIZE_8MB (3 << 6) 536 537 // graphics page translation table 538 #define INTEL_PAGE_TABLE_CONTROL 0x02020 539 #define PAGE_TABLE_ENABLED 0x00000001 540 #define INTEL_PAGE_TABLE_ERROR 0x02024 541 #define INTEL_HARDWARE_STATUS_PAGE 0x02080 542 #define i915_GTT_BASE 0x1c 543 #define i830_GTT_BASE 0x10000 // (- 0x2ffff) 544 #define i830_GTT_SIZE 0x20000 545 #define i965_GTT_BASE 0x80000 // (- 0xfffff) 546 #define i965_GTT_SIZE 0x80000 547 #define i965_GTT_128K (2 << 1) 548 #define i965_GTT_256K (1 << 1) 549 #define i965_GTT_512K (0 << 1) 550 #define G33_GTT_1M (1 << 8) 551 #define G33_GTT_2M (2 << 8) 552 #define G4X_GTT_NONE 0x000 // GGMS - GSM Memory Size 553 #define G4X_GTT_1M_NO_IVT 0x100 // no Intel Virtualization Tech. 554 #define G4X_GTT_2M_NO_IVT 0x300 555 #define G4X_GTT_2M_IVT 0x900 // with Intel Virt. Tech. 556 #define G4X_GTT_3M_IVT 0xa00 557 #define G4X_GTT_4M_IVT 0xb00 558 559 560 #define GTT_ENTRY_VALID 0x01 561 #define GTT_ENTRY_LOCAL_MEMORY 0x02 562 #define GTT_PAGE_SHIFT 12 563 564 565 // ring buffer 566 #define INTEL_PRIMARY_RING_BUFFER 0x02030 567 #define INTEL_SECONDARY_RING_BUFFER_0 0x02100 568 #define INTEL_SECONDARY_RING_BUFFER_1 0x02110 569 // offsets for the ring buffer base registers above 570 #define RING_BUFFER_TAIL 0x0 571 #define RING_BUFFER_HEAD 0x4 572 #define RING_BUFFER_START 0x8 573 #define RING_BUFFER_CONTROL 0xc 574 #define INTEL_RING_BUFFER_SIZE_MASK 0x001ff000 575 #define INTEL_RING_BUFFER_HEAD_MASK 0x001ffffc 576 #define INTEL_RING_BUFFER_ENABLED 1 577 578 // interrupts 579 #define INTEL_INTERRUPT_ENABLED 0x020a0 580 #define INTEL_INTERRUPT_IDENTITY 0x020a4 581 #define INTEL_INTERRUPT_MASK 0x020a8 582 #define INTEL_INTERRUPT_STATUS 0x020ac 583 #define INTERRUPT_VBLANK_PIPEA (1 << 7) 584 #define INTERRUPT_VBLANK_PIPEB (1 << 5) 585 586 // PCH interrupts 587 #define PCH_INTERRUPT_STATUS 0x44000 588 #define PCH_INTERRUPT_MASK 0x44004 589 #define PCH_INTERRUPT_IDENTITY 0x44008 590 #define PCH_INTERRUPT_ENABLED 0x4400c 591 592 #define PCH_INTERRUPT_VBLANK_PIPEA (1 << 0) 593 #define PCH_INTERRUPT_VBLANK_PIPEB (1 << 5) 594 #define PCH_INTERRUPT_VBLANK_PIPEC (1 << 10) 595 596 // SandyBridge had only two pipes, and things were shuffled aroud again with 597 // the introduction of pipe C. 598 #define PCH_INTERRUPT_VBLANK_PIPEA_SNB (1 << 7) 599 #define PCH_INTERRUPT_VBLANK_PIPEB_SNB (1 << 15) 600 #define PCH_INTERRUPT_GLOBAL_SNB (1 << 31) 601 602 #define PCH_MASTER_INT_CTL_BDW 0x44200 603 604 #define PCH_MASTER_INT_CTL_PIPE_PENDING_BDW(pipe) (1 << (15 + pipe)) 605 #define GEN8_DE_PORT_IRQ (1 << 20) 606 #define PCH_MASTER_INT_CTL_GLOBAL_BDW (1 << 31) 607 608 #define PCH_INTERRUPT_PIPE_STATUS_BDW(pipe) (0x44400 + (pipe - 1) * 0x10) // GEN8_DE_PIPE_ISR 609 #define PCH_INTERRUPT_PIPE_MASK_BDW(pipe) (0x44404 + (pipe - 1) * 0x10) // GEN8_DE_PIPE_IMR 610 #define PCH_INTERRUPT_PIPE_IDENTITY_BDW(pipe) (0x44408 + (pipe - 1) * 0x10) // GEN8_DE_PIPE_IIR 611 #define PCH_INTERRUPT_PIPE_ENABLED_BDW(pipe) (0x4440c + (pipe - 1) * 0x10) // GEN8_DE_PIPE_IER 612 613 #define GEN8_DE_PORT_ISR 0x44440 614 #define GEN8_DE_PORT_IMR 0x44444 615 #define GEN8_DE_PORT_IIR 0x44448 616 #define GEN8_DE_PORT_IER 0x4444c 617 #define GEN8_AUX_CHANNEL_A (1 << 0) 618 #define GEN9_AUX_CHANNEL_B (1 << 25) 619 #define GEN9_AUX_CHANNEL_C (1 << 26) 620 #define GEN9_AUX_CHANNEL_D (1 << 27) 621 #define CNL_AUX_CHANNEL_F (1 << 28) 622 #define ICL_AUX_CHANNEL_E (1 << 29) 623 624 #define GEN8_DE_MISC_ISR 0x44460 625 #define GEN8_DE_MISC_IMR 0x44464 626 #define GEN8_DE_MISC_IIR 0x44468 627 #define GEN8_DE_MISC_IER 0x4446c 628 #define GEN8_DE_EDP_PSR (1 << 19) 629 630 #define PCH_INTERRUPT_VBLANK_BDW (1 << 0) // GEN8_PIPE_VBLANK 631 #define GEN8_PIPE_VSYNC (1 << 1) 632 #define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2) 633 634 #define GEN11_DISPLAY_INT_CTL 0x44200 // same as PCH_MASTER_INT_CTL_BDW 635 #define GEN11_GFX_MSTR_IRQ 0x190010 636 #define GEN11_MASTER_IRQ (1 << 31) 637 #define GEN11_DISPLAY_IRQ (1 << 16) 638 #define GEN11_GT_DW1_IRQ (1 << 1) 639 #define GEN11_GT_DW0_IRQ (1 << 0) 640 641 #define GEN11_GT_INTR_DW0 0x190018 642 #define GEN11_GT_INTR_DW1 0x19001c 643 644 #define GEN11_GU_MISC_IMR 0x444f4 645 #define GEN11_GU_MISC_IIR 0x444f8 646 #define GEN11_GU_MISC_IER 0x444fc 647 #define GEN11_GU_MISC_GSE (1 << 27) 648 649 650 // graphics port control (i.e. G45) 651 #define DISPLAY_MONITOR_PORT_ENABLED (1UL << 31) 652 #define DISPLAY_MONITOR_PIPE_B (1UL << 30) 653 #define DISPLAY_MONITOR_VGA_POLARITY (1UL << 15) 654 #define DISPLAY_MONITOR_MODE_MASK (3UL << 10) 655 #define DISPLAY_MONITOR_ON 0 656 #define DISPLAY_MONITOR_SUSPEND (1UL << 10) 657 #define DISPLAY_MONITOR_STAND_BY (2UL << 10) 658 #define DISPLAY_MONITOR_OFF (3UL << 10) 659 #define DISPLAY_MONITOR_POLARITY_MASK (3UL << 3) 660 #define DISPLAY_MONITOR_POSITIVE_HSYNC (1UL << 3) 661 #define DISPLAY_MONITOR_POSITIVE_VSYNC (2UL << 3) 662 #define DISPLAY_MONITOR_PORT_DETECTED (1UL << 2) // TMDS/DisplayPort only 663 664 // Cougar Point transcoder pipe selection 665 // (replaces DISPLAY_MONITOR_PIPE_B) 666 #define PORT_TRANS_A_SEL_CPT 0 667 #define PORT_TRANS_B_SEL_CPT (1<<29) 668 #define PORT_TRANS_C_SEL_CPT (2<<29) 669 #define PORT_TRANS_SEL_MASK (3<<29) 670 671 #define LVDS_POST2_RATE_SLOW 14 // PLL Divisors 672 #define LVDS_POST2_RATE_FAST 7 673 #define LVDS_B0B3_POWER_MASK (3UL << 2) 674 #define LVDS_B0B3_POWER_UP (3UL << 2) 675 #define LVDS_CLKB_POWER_MASK (3UL << 4) 676 #define LVDS_CLKB_POWER_UP (3UL << 4) 677 #define LVDS_A3_POWER_MASK (3UL << 6) 678 #define LVDS_A3_POWER_UP (3UL << 6) 679 #define LVDS_A0A2_CLKA_POWER_UP (3UL << 8) 680 #define LVDS_BORDER_ENABLE (1UL << 15) 681 #define LVDS_HSYNC_POLARITY (1UL << 20) 682 #define LVDS_VSYNC_POLARITY (1UL << 21) 683 #define LVDS_18BIT_DITHER (1UL << 25) 684 #define LVDS_PORT_EN (1UL << 31) 685 686 // PLL flags (pre-DDI) 687 #define DISPLAY_PLL_ENABLED (1UL << 31) 688 #define DISPLAY_PLL_2X_CLOCK (1UL << 30) 689 #define DISPLAY_PLL_SYNC_LOCK_ENABLED (1UL << 29) 690 #define DISPLAY_PLL_NO_VGA_CONTROL (1UL << 28) 691 #define DISPLAY_PLL_MODE_NORMAL (1UL << 26) 692 #define DISPLAY_PLL_MODE_LVDS (2UL << 26) 693 #define DISPLAY_PLL_DIVIDE_HIGH (1UL << 24) 694 #define DISPLAY_PLL_DIVIDE_4X (1UL << 23) 695 #define DISPLAY_PLL_POST1_DIVIDE_2 (1UL << 21) 696 #define DISPLAY_PLL_POST1_DIVISOR_MASK 0x001f0000 697 #define DISPLAY_PLL_9xx_POST1_DIVISOR_MASK 0x00ff0000 698 #define DISPLAY_PLL_SNB_FP0_POST1_DIVISOR_MASK 0x000000ff 699 #define DISPLAY_PLL_IGD_POST1_DIVISOR_MASK 0x00ff8000 700 #define DISPLAY_PLL_POST1_DIVISOR_SHIFT 16 701 #define DISPLAY_PLL_SNB_FP0_POST1_DIVISOR_SHIFT 0 702 #define DISPLAY_PLL_IGD_POST1_DIVISOR_SHIFT 15 703 #define DISPLAY_PLL_DIVISOR_1 (1UL << 8) 704 #define DISPLAY_PLL_N_DIVISOR_MASK 0x001f0000 705 #define DISPLAY_PLL_IGD_N_DIVISOR_MASK 0x00ff0000 706 #define DISPLAY_PLL_M1_DIVISOR_MASK 0x00001f00 707 #define DISPLAY_PLL_M2_DIVISOR_MASK 0x0000001f 708 #define DISPLAY_PLL_IGD_M2_DIVISOR_MASK 0x000000ff 709 #define DISPLAY_PLL_N_DIVISOR_SHIFT 16 710 #define DISPLAY_PLL_M1_DIVISOR_SHIFT 8 711 #define DISPLAY_PLL_M2_DIVISOR_SHIFT 0 712 #define DISPLAY_PLL_PULSE_PHASE_SHIFT 9 713 714 // Skylake PLLs 715 #define SKL_DPLL1_CFGCR1 (0xc040 | REGS_NORTH_PIPE_AND_PORT) 716 #define SKL_DPLL1_CFGCR2 (0xc044 | REGS_NORTH_PIPE_AND_PORT) 717 #define SKL_DPLL2_CFGCR1 (0xc048 | REGS_NORTH_PIPE_AND_PORT) 718 #define SKL_DPLL2_CFGCR2 (0xc04c | REGS_NORTH_PIPE_AND_PORT) 719 #define SKL_DPLL3_CFGCR1 (0xc050 | REGS_NORTH_PIPE_AND_PORT) 720 #define SKL_DPLL3_CFGCR2 (0xc054 | REGS_NORTH_PIPE_AND_PORT) 721 // These exist also still in CoffeeLake (confirmed): 722 #define SKL_DPLL_CTRL1 (0xc058 | REGS_NORTH_PIPE_AND_PORT) 723 #define SKL_DPLL_CTRL2 (0xc05c | REGS_NORTH_PIPE_AND_PORT) 724 #define SKL_DPLL_STATUS (0xc060 | REGS_NORTH_PIPE_AND_PORT) 725 #define SKL_DPLL0_DP_LINKRATE_SHIFT 1 726 #define SKL_DPLL1_DP_LINKRATE_SHIFT 7 727 #define SKL_DPLL2_DP_LINKRATE_SHIFT 13 728 #define SKL_DPLL3_DP_LINKRATE_SHIFT 19 729 #define SKL_DPLL_DP_LINKRATE_MASK 7 730 #define SKL_DPLL_CTRL1_2700 0 731 #define SKL_DPLL_CTRL1_1350 1 732 #define SKL_DPLL_CTRL1_810 2 733 #define SKL_DPLL_CTRL1_1620 3 734 #define SKL_DPLL_CTRL1_1080 4 735 #define SKL_DPLL_CTRL1_2160 5 736 737 // Icelake PLLs 738 #define ICL_DSSM 0x51004 739 #define ICL_DSSM_REF_FREQ_SHIFT 29 740 #define ICL_DSSM_REF_FREQ_MASK (7 << ICL_DSSM_REF_FREQ_SHIFT) 741 #define ICL_DSSM_24000 0 742 #define ICL_DSSM_19200 1 743 #define ICL_DSSM_38400 2 744 745 // display 746 747 #define INTEL_DISPLAY_OFFSET 0x1000 748 749 // Note: on Skylake below registers are part of the transcoder 750 #define INTEL_DISPLAY_A_HTOTAL (0x0000 | REGS_NORTH_PIPE_AND_PORT) 751 #define INTEL_DISPLAY_A_HBLANK (0x0004 | REGS_NORTH_PIPE_AND_PORT) 752 #define INTEL_DISPLAY_A_HSYNC (0x0008 | REGS_NORTH_PIPE_AND_PORT) 753 #define INTEL_DISPLAY_A_VTOTAL (0x000c | REGS_NORTH_PIPE_AND_PORT) 754 #define INTEL_DISPLAY_A_VBLANK (0x0010 | REGS_NORTH_PIPE_AND_PORT) 755 #define INTEL_DISPLAY_A_VSYNC (0x0014 | REGS_NORTH_PIPE_AND_PORT) 756 #define INTEL_DISPLAY_B_HTOTAL (0x1000 | REGS_NORTH_PIPE_AND_PORT) 757 #define INTEL_DISPLAY_B_HBLANK (0x1004 | REGS_NORTH_PIPE_AND_PORT) 758 #define INTEL_DISPLAY_B_HSYNC (0x1008 | REGS_NORTH_PIPE_AND_PORT) 759 #define INTEL_DISPLAY_B_VTOTAL (0x100c | REGS_NORTH_PIPE_AND_PORT) 760 #define INTEL_DISPLAY_B_VBLANK (0x1010 | REGS_NORTH_PIPE_AND_PORT) 761 #define INTEL_DISPLAY_B_VSYNC (0x1014 | REGS_NORTH_PIPE_AND_PORT) 762 763 #define INTEL_DISPLAY_A_PIPE_SIZE (0x001c | REGS_NORTH_PIPE_AND_PORT) 764 #define INTEL_DISPLAY_B_PIPE_SIZE (0x101c | REGS_NORTH_PIPE_AND_PORT) 765 766 //G45 displayport link 767 #define INTEL_PIPE_A_DATA_M (0x0050 | REGS_NORTH_PLANE_CONTROL) 768 #define INTEL_PIPE_B_DATA_M (0x1050 | REGS_NORTH_PLANE_CONTROL) 769 #define INTEL_PIPE_A_DATA_N (0x0054 | REGS_NORTH_PLANE_CONTROL) 770 #define INTEL_PIPE_B_DATA_N (0x1054 | REGS_NORTH_PLANE_CONTROL) 771 #define INTEL_PIPE_A_LINK_M (0x0060 | REGS_NORTH_PLANE_CONTROL) 772 #define INTEL_PIPE_B_LINK_M (0x1060 | REGS_NORTH_PLANE_CONTROL) 773 #define INTEL_PIPE_A_LINK_N (0x0064 | REGS_NORTH_PLANE_CONTROL) 774 #define INTEL_PIPE_B_LINK_N (0x1064 | REGS_NORTH_PLANE_CONTROL) 775 776 //DDI port link 777 #define INTEL_DDI_PIPE_A_DATA_M (0x0030 | REGS_NORTH_PIPE_AND_PORT) 778 #define INTEL_DDI_PIPE_B_DATA_M (0x1030 | REGS_NORTH_PIPE_AND_PORT) 779 #define INTEL_DDI_PIPE_A_DATA_N (0x0034 | REGS_NORTH_PIPE_AND_PORT) 780 #define INTEL_DDI_PIPE_B_DATA_N (0x1034 | REGS_NORTH_PIPE_AND_PORT) 781 #define INTEL_DDI_PIPE_A_LINK_M (0x0040 | REGS_NORTH_PIPE_AND_PORT) 782 #define INTEL_DDI_PIPE_B_LINK_M (0x1040 | REGS_NORTH_PIPE_AND_PORT) 783 #define INTEL_DDI_PIPE_A_LINK_N (0x0044 | REGS_NORTH_PIPE_AND_PORT) 784 #define INTEL_DDI_PIPE_B_LINK_N (0x1044 | REGS_NORTH_PIPE_AND_PORT) 785 786 // on PCH we also have to set the transcoder 787 #define INTEL_TRANSCODER_A_HTOTAL (0x0000 | REGS_SOUTH_TRANSCODER_PORT) 788 #define INTEL_TRANSCODER_A_HBLANK (0x0004 | REGS_SOUTH_TRANSCODER_PORT) 789 #define INTEL_TRANSCODER_A_HSYNC (0x0008 | REGS_SOUTH_TRANSCODER_PORT) 790 #define INTEL_TRANSCODER_A_VTOTAL (0x000c | REGS_SOUTH_TRANSCODER_PORT) 791 #define INTEL_TRANSCODER_A_VBLANK (0x0010 | REGS_SOUTH_TRANSCODER_PORT) 792 #define INTEL_TRANSCODER_A_VSYNC (0x0014 | REGS_SOUTH_TRANSCODER_PORT) 793 #define INTEL_TRANSCODER_B_HTOTAL (0x1000 | REGS_SOUTH_TRANSCODER_PORT) 794 #define INTEL_TRANSCODER_B_HBLANK (0x1004 | REGS_SOUTH_TRANSCODER_PORT) 795 #define INTEL_TRANSCODER_B_HSYNC (0x1008 | REGS_SOUTH_TRANSCODER_PORT) 796 #define INTEL_TRANSCODER_B_VTOTAL (0x100c | REGS_SOUTH_TRANSCODER_PORT) 797 #define INTEL_TRANSCODER_B_VBLANK (0x1010 | REGS_SOUTH_TRANSCODER_PORT) 798 #define INTEL_TRANSCODER_B_VSYNC (0x1014 | REGS_SOUTH_TRANSCODER_PORT) 799 800 // transcoder M/N DATA AND LINK VALUES (refreshrate) 801 #define INTEL_TRANSCODER_A_DATA_M1 (0x0030 | REGS_SOUTH_TRANSCODER_PORT) 802 #define INTEL_TRANSCODER_A_DATA_M2 (0x0038 | REGS_SOUTH_TRANSCODER_PORT) 803 #define INTEL_TRANSCODER_B_DATA_M1 (0x1030 | REGS_SOUTH_TRANSCODER_PORT) 804 #define INTEL_TRANSCODER_B_DATA_M2 (0x1038 | REGS_SOUTH_TRANSCODER_PORT) 805 #define INTEL_TRANSCODER_C_DATA_M1 (0x2030 | REGS_SOUTH_TRANSCODER_PORT) 806 #define INTEL_TRANSCODER_C_DATA_M2 (0x2038 | REGS_SOUTH_TRANSCODER_PORT) 807 #define INTEL_TRANSCODER_A_DATA_N1 (0x0034 | REGS_SOUTH_TRANSCODER_PORT) 808 #define INTEL_TRANSCODER_A_DATA_N2 (0x003c | REGS_SOUTH_TRANSCODER_PORT) 809 #define INTEL_TRANSCODER_B_DATA_N1 (0x1034 | REGS_SOUTH_TRANSCODER_PORT) 810 #define INTEL_TRANSCODER_B_DATA_N2 (0x103c | REGS_SOUTH_TRANSCODER_PORT) 811 #define INTEL_TRANSCODER_C_DATA_N1 (0x2034 | REGS_SOUTH_TRANSCODER_PORT) 812 #define INTEL_TRANSCODER_C_DATA_N2 (0x203c | REGS_SOUTH_TRANSCODER_PORT) 813 #define INTEL_TRANSCODER_A_LINK_M1 (0x0040 | REGS_SOUTH_TRANSCODER_PORT) 814 #define INTEL_TRANSCODER_A_LINK_M2 (0x0048 | REGS_SOUTH_TRANSCODER_PORT) 815 #define INTEL_TRANSCODER_B_LINK_M1 (0x1040 | REGS_SOUTH_TRANSCODER_PORT) 816 #define INTEL_TRANSCODER_B_LINK_M2 (0x1048 | REGS_SOUTH_TRANSCODER_PORT) 817 #define INTEL_TRANSCODER_C_LINK_M1 (0x2040 | REGS_SOUTH_TRANSCODER_PORT) 818 #define INTEL_TRANSCODER_C_LINK_M2 (0x2048 | REGS_SOUTH_TRANSCODER_PORT) 819 #define INTEL_TRANSCODER_A_LINK_N1 (0x0044 | REGS_SOUTH_TRANSCODER_PORT) 820 #define INTEL_TRANSCODER_A_LINK_N2 (0x004c | REGS_SOUTH_TRANSCODER_PORT) 821 #define INTEL_TRANSCODER_B_LINK_N1 (0x1044 | REGS_SOUTH_TRANSCODER_PORT) 822 #define INTEL_TRANSCODER_B_LINK_N2 (0x104c | REGS_SOUTH_TRANSCODER_PORT) 823 #define INTEL_TRANSCODER_C_LINK_N1 (0x2044 | REGS_SOUTH_TRANSCODER_PORT) 824 #define INTEL_TRANSCODER_C_LINK_N2 (0x204c | REGS_SOUTH_TRANSCODER_PORT) 825 #define INTEL_TRANSCODER_MN_TU_SIZE_MASK (0x3f << 25) 826 #define INTEL_TRANSCODER_MN_VALUE_MASK (0xffffff << 0) 827 828 #define INTEL_TRANSCODER_A_IMAGE_SIZE (0x001c | REGS_SOUTH_TRANSCODER_PORT) 829 #define INTEL_TRANSCODER_B_IMAGE_SIZE (0x101c | REGS_SOUTH_TRANSCODER_PORT) 830 831 // TODO: Is there consolidation that could happen here with digital ports? 832 833 #define INTEL_ANALOG_PORT (0x1100 | REGS_SOUTH_TRANSCODER_PORT) 834 #define INTEL_DIGITAL_PORT_A (0x1120 | REGS_SOUTH_TRANSCODER_PORT) 835 #define INTEL_DIGITAL_PORT_B (0x1140 | REGS_SOUTH_TRANSCODER_PORT) 836 #define INTEL_DIGITAL_PORT_C (0x1160 | REGS_SOUTH_TRANSCODER_PORT) 837 #define INTEL_DIGITAL_LVDS_PORT (0x1180 | REGS_SOUTH_TRANSCODER_PORT) 838 839 #define INTEL_HDMI_PORT_B (0x1140 | REGS_SOUTH_TRANSCODER_PORT) 840 #define INTEL_HDMI_PORT_C (0x1160 | REGS_SOUTH_TRANSCODER_PORT) 841 842 #define PCH_HDMI_PORT_B (0x1140 | REGS_SOUTH_TRANSCODER_PORT) 843 #define PCH_HDMI_PORT_C (0x1150 | REGS_SOUTH_TRANSCODER_PORT) 844 #define PCH_HDMI_PORT_D (0x1160 | REGS_SOUTH_TRANSCODER_PORT) 845 846 #define GEN4_HDMI_PORT_B (0x1140 | REGS_SOUTH_TRANSCODER_PORT) 847 #define GEN4_HDMI_PORT_C (0x1160 | REGS_SOUTH_TRANSCODER_PORT) 848 #define CHV_HDMI_PORT_D (0x116C | REGS_SOUTH_TRANSCODER_PORT) 849 850 // DDI Buffer Control (This replaces DP on Haswell+) 851 #define DDI_BUF_CTL_A (0x4000 | REGS_NORTH_PIPE_AND_PORT) 852 #define DDI_BUF_CTL_B (0x4100 | REGS_NORTH_PIPE_AND_PORT) 853 #define DDI_BUF_CTL_C (0x4200 | REGS_NORTH_PIPE_AND_PORT) 854 #define DDI_BUF_CTL_D (0x4300 | REGS_NORTH_PIPE_AND_PORT) 855 #define DDI_BUF_CTL_E (0x4400 | REGS_NORTH_PIPE_AND_PORT) 856 #define DDI_BUF_CTL_F (0x4500 | REGS_NORTH_PIPE_AND_PORT) 857 #define DDI_BUF_CTL_ENABLE (1 << 31) 858 #define DDI_BUF_TRANS_SELECT(n) ((n) << 24) 859 #define DDI_BUF_EMP_MASK (0xf << 24) 860 #define DDI_BUF_PORT_REVERSAL (1 << 16) 861 #define DDI_BUF_IS_IDLE (1 << 7) 862 #define DDI_A_4_LANES (1 << 4) 863 #define DDI_PORT_WIDTH(width) (((width) - 1) << 1) 864 #define DDI_INIT_DISPLAY_DETECTED (1 << 0) 865 866 #define PIPE_DDI_FUNC_CTL_A (0x0400 | REGS_NORTH_PIPE_AND_PORT) 867 #define PIPE_DDI_FUNC_CTL_B (0x1400 | REGS_NORTH_PIPE_AND_PORT) 868 #define PIPE_DDI_FUNC_CTL_C (0x2400 | REGS_NORTH_PIPE_AND_PORT) 869 #define PIPE_DDI_FUNC_CTL_EDP (0xF400 | REGS_NORTH_PIPE_AND_PORT) 870 #define PIPE_DDI_FUNC_CTL_ENABLE (1 << 31) 871 #define PIPE_DDI_SELECT_SHIFT 28 872 #define PIPE_DDI_SELECT_PORT(x) ((x) << PIPE_DDI_SELECT_SHIFT) 873 #define PIPE_DDI_SELECT_MASK (7 << PIPE_DDI_SELECT_SHIFT) 874 #define PIPE_DDI_PORT_NONE 0 875 #define PIPE_DDI_PORT_B 1 876 #define PIPE_DDI_PORT_C 2 877 #define PIPE_DDI_PORT_D 3 878 #define PIPE_DDI_PORT_E 4 879 #define PIPE_DDI_PORT_F 5 880 #define PIPE_DDI_MODESEL_SHIFT 24 881 #define PIPE_DDI_MODESEL_MODE(x) ((x) << PIPE_DDI_MODESEL_SHIFT) 882 #define PIPE_DDI_MODESEL_MASK (7 << PIPE_DDI_MODESEL_SHIFT) 883 #define PIPE_DDI_MODE_HDMI 0 884 #define PIPE_DDI_MODE_DVI 1 885 #define PIPE_DDI_MODE_DP_SST 2 886 #define PIPE_DDI_MODE_DP_MST 3 887 #define PIPE_DDI_COLOR_SHIFT 20 888 #define PIPE_DDI_BPC(x) ((x) << PIPE_DDI_COLOR_SHIFT) 889 #define PIPE_DDI_BPC_MASK (7 << PIPE_DDI_COLOR_SHIFT) 890 #define PIPE_DDI_8BPC 0 891 #define PIPE_DDI_10BPC 1 892 #define PIPE_DDI_6BPC 2 893 #define PIPE_DDI_12BPC 3 894 #define PIPE_DDI_DP_WIDTH_SHIFT 1 895 #define PIPE_DDI_DP_WIDTH_SEL(x) ((x) << PIPE_DDI_DP_WIDTH_SHIFT) 896 #define PIPE_DDI_DP_WIDTH_MASK (7 << PIPE_DDI_DP_WIDTH_SHIFT) 897 #define PIPE_DDI_DP_WIDTH_1 0 898 #define PIPE_DDI_DP_WIDTH_2 1 899 #define PIPE_DDI_DP_WIDTH_4 2 900 901 // DP_A always @ 6xxxx, DP_B-DP_D move with PCH 902 #define INTEL_DISPLAY_PORT_A (0x4000 | REGS_NORTH_PIPE_AND_PORT) 903 #define INTEL_DISPLAY_PORT_B (0x4100 | REGS_SOUTH_TRANSCODER_PORT) 904 #define INTEL_DISPLAY_PORT_C (0x4200 | REGS_SOUTH_TRANSCODER_PORT) 905 #define INTEL_DISPLAY_PORT_D (0x4300 | REGS_SOUTH_TRANSCODER_PORT) 906 907 #define INTEL_DISP_PORTA_SNB_PIPE_SHIFT 30 908 #define INTEL_DISP_PORTA_SNB_PIPE_MASK (1 << INTEL_DISP_PORTA_SNB_PIPE_SHIFT) 909 #define INTEL_DISP_PORTA_SNB_PIPE_A 0 910 #define INTEL_DISP_PORTA_SNB_PIPE_B 1 911 #define INTEL_DISP_PORTA_IVB_PIPE_SHIFT 29 912 #define INTEL_DISP_PORTA_IVB_PIPE_MASK (3 << INTEL_DISP_PORTA_IVB_PIPE_SHIFT) 913 #define INTEL_DISP_PORTA_IVB_PIPE_A 0 914 #define INTEL_DISP_PORTA_IVB_PIPE_B 1 915 #define INTEL_DISP_PORTA_IVB_PIPE_C 2 916 917 #define INTEL_DISP_PORT_WIDTH_SHIFT 19 918 #define INTEL_DISP_PORT_WIDTH_MASK (7 << INTEL_DISP_PORT_WIDTH_SHIFT) 919 #define INTEL_DISP_PORT_WIDTH_1 0 920 #define INTEL_DISP_PORT_WIDTH_2 1 921 #define INTEL_DISP_PORT_WIDTH_4 3 922 #define INTEL_DISP_EDP_PLL_FREQ_SHIFT 16 923 #define INTEL_DISP_EDP_PLL_FREQ_MASK (3 << INTEL_DISP_EDP_PLL_FREQ_SHIFT) 924 #define INTEL_DISP_EDP_PLL_FREQ_270 0 925 #define INTEL_DISP_EDP_PLL_FREQ_162 1 926 927 #define INTEL_TRANSCODER_A_DP_CTL (0x0300 | REGS_SOUTH_TRANSCODER_PORT) 928 #define INTEL_TRANSCODER_B_DP_CTL (0x1300 | REGS_SOUTH_TRANSCODER_PORT) 929 #define INTEL_TRANSCODER_C_DP_CTL (0x2300 | REGS_SOUTH_TRANSCODER_PORT) 930 931 #define INTEL_TRANS_DP_COLOR_SHIFT 9 932 #define INTEL_TRANS_DP_BPC(x) ((x) << INTEL_TRANS_DP_COLOR_SHIFT) 933 #define INTEL_TRANS_DP_BPC_MASK (7 << INTEL_TRANS_DP_COLOR_SHIFT) 934 #define INTEL_TRANS_DP_PORT_SHIFT 29 935 #define INTEL_TRANS_DP_PORT(x) ((x) << INTEL_TRANS_DP_PORT_SHIFT) 936 #define INTEL_TRANS_DP_PORT_MASK (3 << INTEL_TRANS_DP_PORT_SHIFT) 937 #define INTEL_TRANS_DP_PORT_B 0 938 #define INTEL_TRANS_DP_PORT_C 1 939 #define INTEL_TRANS_DP_PORT_D 2 940 #define INTEL_TRANS_DP_PORT_NONE 3 941 942 // Unless you're a damn Valley/CherryView unicorn :-( 943 #define VLV_DISPLAY_PORT_B (VLV_DISPLAY_BASE + 0x64100) 944 #define VLV_DISPLAY_PORT_C (VLV_DISPLAY_BASE + 0x64200) 945 #define CHV_DISPLAY_PORT_D (VLV_DISPLAY_BASE + 0x64300) 946 947 // DP AUX channels 948 #define _DPA_AUX_CH_CTL (0x4010 | REGS_NORTH_PIPE_AND_PORT) 949 #define _DPA_AUX_CH_DATA1 (0x4014 | REGS_NORTH_PIPE_AND_PORT) 950 #define _DPB_AUX_CH_CTL (0x4110 | REGS_NORTH_PIPE_AND_PORT) 951 #define _DPB_AUX_CH_DATA1 (0x4114 | REGS_NORTH_PIPE_AND_PORT) 952 #define DP_AUX_CH_CTL(aux) \ 953 (_DPA_AUX_CH_CTL + (_DPB_AUX_CH_CTL - _DPA_AUX_CH_CTL) * aux) 954 #define DP_AUX_CH_DATA(aux, i) \ 955 (_DPA_AUX_CH_DATA1 + (_DPB_AUX_CH_DATA1 - _DPA_AUX_CH_DATA1) * aux + i * 4) 956 957 #define INTEL_DP_AUX_CTL_BUSY (1 << 31) 958 #define INTEL_DP_AUX_CTL_DONE (1 << 30) 959 #define INTEL_DP_AUX_CTL_INTERRUPT (1 << 29) 960 #define INTEL_DP_AUX_CTL_TIMEOUT_ERROR (1 << 28) 961 #define INTEL_DP_AUX_CTL_TIMEOUT_400us (0 << 26) 962 #define INTEL_DP_AUX_CTL_TIMEOUT_600us (1 << 26) 963 #define INTEL_DP_AUX_CTL_TIMEOUT_800us (2 << 26) 964 #define INTEL_DP_AUX_CTL_TIMEOUT_1600us (3 << 26) 965 #define INTEL_DP_AUX_CTL_TIMEOUT_MASK (3 << 26) 966 #define INTEL_DP_AUX_CTL_RECEIVE_ERROR (1 << 25) 967 #define INTEL_DP_AUX_CTL_MSG_SIZE_MASK (0x1f << 20) 968 #define INTEL_DP_AUX_CTL_MSG_SIZE_SHIFT 20 969 #define INTEL_DP_AUX_CTL_PRECHARGE_2US_MASK (0xf << 16) 970 #define INTEL_DP_AUX_CTL_PRECHARGE_2US_SHIFT 16 971 #define INTEL_DP_AUX_CTL_BIT_CLOCK_2X_MASK (0x7ff) 972 #define INTEL_DP_AUX_CTL_BIT_CLOCK_2X_SHIFT 0 973 #define INTEL_DP_AUX_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5) 974 #define INTEL_DP_AUX_CTL_SYNC_PULSE_SKL(c) ((c) - 1) 975 976 // planes 977 #define INTEL_PIPE_ENABLED (1UL << 31) 978 #define INTEL_PIPE_STATE (1UL << 30) 979 980 #define INTEL_PLANE_OFFSET 0x1000 981 982 #define INTEL_DISPLAY_A_PIPE_CONTROL (0x0008 | REGS_NORTH_PLANE_CONTROL) 983 #define INTEL_DISPLAY_B_PIPE_CONTROL (0x1008 | REGS_NORTH_PLANE_CONTROL) 984 #define INTEL_DISPLAY_C_PIPE_CONTROL (0x2008 | REGS_NORTH_PLANE_CONTROL) 985 #define INTEL_DISPLAY_A_PIPE_STATUS (0x0024 | REGS_NORTH_PLANE_CONTROL) 986 #define INTEL_DISPLAY_B_PIPE_STATUS (0x1024 | REGS_NORTH_PLANE_CONTROL) 987 988 #define INTEL_DISPLAY_A_PIPE_WATERMARK (0x5100 | REGS_NORTH_PLANE_CONTROL) 989 #define INTEL_DISPLAY_B_PIPE_WATERMARK (0x5104 | REGS_NORTH_PLANE_CONTROL) 990 #define INTEL_DISPLAY_C_PIPE_WATERMARK (0x5200 | REGS_NORTH_PLANE_CONTROL) 991 992 #define DISPLAY_PIPE_VBLANK_ENABLED (1UL << 17) 993 #define DISPLAY_PIPE_VBLANK_STATUS (1UL << 1) 994 995 #define INTEL_DISPLAY_A_CONTROL (0x0180 | REGS_NORTH_PLANE_CONTROL) 996 #define INTEL_DISPLAY_A_BASE (0x0184 | REGS_NORTH_PLANE_CONTROL) 997 #define INTEL_DISPLAY_A_BYTES_PER_ROW (0x0188 | REGS_NORTH_PLANE_CONTROL) 998 #define INTEL_DISPLAY_A_POS (0x018c | REGS_NORTH_PLANE_CONTROL) 999 // reserved on A 1000 #define INTEL_DISPLAY_A_IMAGE_SIZE (0x0190 | REGS_NORTH_PLANE_CONTROL) 1001 #define INTEL_DISPLAY_A_SURFACE (0x019c | REGS_NORTH_PLANE_CONTROL) 1002 #define INTEL_DISPLAY_A_OFFSET_HAS (0x01a4 | REGS_NORTH_PLANE_CONTROL) 1003 // i965 and up only 1004 1005 #define INTEL_DISPLAY_B_CONTROL (0x1180 | REGS_NORTH_PLANE_CONTROL) 1006 #define INTEL_DISPLAY_B_BASE (0x1184 | REGS_NORTH_PLANE_CONTROL) 1007 #define INTEL_DISPLAY_B_BYTES_PER_ROW (0x1188 | REGS_NORTH_PLANE_CONTROL) 1008 #define INTEL_DISPLAY_B_POS (0x118c | REGS_NORTH_PLANE_CONTROL) 1009 #define INTEL_DISPLAY_B_IMAGE_SIZE (0x1190 | REGS_NORTH_PLANE_CONTROL) 1010 #define INTEL_DISPLAY_B_SURFACE (0x119c | REGS_NORTH_PLANE_CONTROL) 1011 #define INTEL_DISPLAY_B_OFFSET_HAS (0x11a4 | REGS_NORTH_PLANE_CONTROL) 1012 // i965 and up only 1013 1014 // INTEL_DISPLAY_A_CONTROL source pixel format 1015 #define DISPLAY_CONTROL_ENABLED (1UL << 31) 1016 #define DISPLAY_CONTROL_GAMMA (1UL << 30) 1017 #define DISPLAY_CONTROL_COLOR_MASK (0x0fUL << 26) 1018 #define DISPLAY_CONTROL_CMAP8 (2UL << 26) 1019 #define DISPLAY_CONTROL_RGB15 (4UL << 26) 1020 #define DISPLAY_CONTROL_RGB16 (5UL << 26) 1021 #define DISPLAY_CONTROL_RGB32 (6UL << 26) 1022 #define DISPLAY_CONTROL_RGB64 (0x0cUL << 26) 1023 // Skylake 1024 #define DISPLAY_CONTROL_COLOR_MASK_SKY (0x0fUL << 24) 1025 #define DISPLAY_CONTROL_CMAP8_SKY (0x0cUL << 24) 1026 #define DISPLAY_CONTROL_RGB15_SKY (0x0eUL << 24) 1027 #define DISPLAY_CONTROL_RGB16_SKY (0x0eUL << 24) 1028 #define DISPLAY_CONTROL_RGB32_SKY (0x04UL << 24) 1029 #define DISPLAY_CONTROL_RGB64_SKY (0x06UL << 24) 1030 1031 // INTEL_DISPLAY_A_PIPE_CONTROL ILK+ 1032 #define INTEL_PIPE_DITHER_TYPE_MASK (0x0000000c) 1033 #define INTEL_PIPE_DITHER_TYPE_SP (0 << 2) 1034 #define INTEL_PIPE_DITHER_TYPE_ST1 (1 << 2) 1035 #define INTEL_PIPE_DITHER_TYPE_ST2 (2 << 2) 1036 #define INTEL_PIPE_DITHER_TYPE_TEMP (3 << 2) 1037 #define INTEL_PIPE_DITHER_EN (1 << 4) 1038 #define INTEL_PIPE_COLOR_SHIFT 5 1039 #define INTEL_PIPE_BPC(x) ((x) << INTEL_PIPE_COLOR_SHIFT) 1040 #define INTEL_PIPE_BPC_MASK (7 << INTEL_PIPE_COLOR_SHIFT) 1041 #define INTEL_PIPE_8BPC 0 1042 #define INTEL_PIPE_10BPC 1 1043 #define INTEL_PIPE_6BPC 2 1044 #define INTEL_PIPE_12BPC 3 1045 #define INTEL_PIPE_PROGRESSIVE (0 << 21) 1046 1047 // cursors 1048 #define INTEL_CURSOR_CONTROL (0x0080 | REGS_NORTH_PLANE_CONTROL) 1049 #define INTEL_CURSOR_BASE (0x0084 | REGS_NORTH_PLANE_CONTROL) 1050 #define INTEL_CURSOR_POSITION (0x0088 | REGS_NORTH_PLANE_CONTROL) 1051 #define INTEL_CURSOR_PALETTE (0x0090 | REGS_NORTH_PLANE_CONTROL) 1052 // (- 0x009f) 1053 #define INTEL_CURSOR_SIZE (0x00a0 | REGS_NORTH_PLANE_CONTROL) 1054 #define CURSOR_ENABLED (1UL << 31) 1055 #define CURSOR_FORMAT_2_COLORS (0UL << 24) 1056 #define CURSOR_FORMAT_3_COLORS (1UL << 24) 1057 #define CURSOR_FORMAT_4_COLORS (2UL << 24) 1058 #define CURSOR_FORMAT_ARGB (4UL << 24) 1059 #define CURSOR_FORMAT_XRGB (5UL << 24) 1060 #define CURSOR_POSITION_NEGATIVE 0x8000 1061 #define CURSOR_POSITION_MASK 0x3fff 1062 1063 // palette registers 1064 #define INTEL_DISPLAY_A_PALETTE (0xa000 | REGS_NORTH_SHARED) 1065 #define INTEL_DISPLAY_B_PALETTE (0xa800 | REGS_NORTH_SHARED) 1066 1067 // Ironlake PCH reference clk control 1068 #define PCH_DREF_CONTROL (0x6200 | REGS_SOUTH_SHARED) 1069 #define DREF_CONTROL_MASK 0x7fc3 1070 #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0 << 13) 1071 #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2 << 13) 1072 #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3 << 13) 1073 #define DREF_CPU_SOURCE_OUTPUT_MASK (3 << 13) 1074 #define DREF_SSC_SOURCE_DISABLE (0 << 11) 1075 #define DREF_SSC_SOURCE_ENABLE (2 << 11) 1076 #define DREF_SSC_SOURCE_MASK (3 << 11) 1077 #define DREF_NONSPREAD_SOURCE_DISABLE (0 << 9) 1078 #define DREF_NONSPREAD_CK505_ENABLE (1 << 9) 1079 #define DREF_NONSPREAD_SOURCE_ENABLE (2 << 9) 1080 #define DREF_NONSPREAD_SOURCE_MASK (3 << 9) 1081 #define DREF_SUPERSPREAD_SOURCE_DISABLE (0 << 7) 1082 #define DREF_SUPERSPREAD_SOURCE_ENABLE (2 << 7) 1083 #define DREF_SUPERSPREAD_SOURCE_MASK (3 << 7) 1084 #define DREF_SSC4_DOWNSPREAD (0 << 6) 1085 #define DREF_SSC4_CENTERSPREAD (1 << 6) 1086 #define DREF_SSC1_DISABLE (0 << 1) 1087 #define DREF_SSC1_ENABLE (1 << 1) 1088 #define DREF_SSC4_DISABLE (0 << 0) 1089 #define DREF_SSC4_ENABLE (1 << 0) 1090 1091 // PLL registers 1092 // Multiplier Divisor 1093 #define INTEL_DISPLAY_A_PLL (0x6014 | REGS_SOUTH_SHARED) 1094 #define INTEL_DISPLAY_B_PLL (0x6018 | REGS_SOUTH_SHARED) 1095 #define INTEL_DISPLAY_A_PLL_MD (0x601C | REGS_SOUTH_SHARED) 1096 #define INTEL_DISPLAY_B_PLL_MD (0x6020 | REGS_SOUTH_SHARED) 1097 #define CHV_DISPLAY_C_PLL (0x6030 | REGS_SOUTH_SHARED) 1098 #define CHV_DISPLAY_B_PLL_MD (0x603C | REGS_SOUTH_SHARED) 1099 1100 #define INTEL_DISPLAY_A_PLL_DIVISOR_0 (0x6040 | REGS_SOUTH_SHARED) 1101 #define INTEL_DISPLAY_A_PLL_DIVISOR_1 (0x6044 | REGS_SOUTH_SHARED) 1102 #define INTEL_DISPLAY_B_PLL_DIVISOR_0 (0x6048 | REGS_SOUTH_SHARED) 1103 #define INTEL_DISPLAY_B_PLL_DIVISOR_1 (0x604c | REGS_SOUTH_SHARED) 1104 1105 #define SNB_DPLL_SEL (0x7000 | REGS_SOUTH_SHARED) 1106 1107 // i2c bit banging interface 1108 #define INTEL_I2C_IO_A (0x5010 | REGS_SOUTH_SHARED) 1109 #define INTEL_I2C_IO_B (0x5014 | REGS_SOUTH_SHARED) 1110 #define INTEL_I2C_IO_C (0x5018 | REGS_SOUTH_SHARED) 1111 #define INTEL_I2C_IO_D (0x501c | REGS_SOUTH_SHARED) 1112 #define INTEL_I2C_IO_E (0x5020 | REGS_SOUTH_SHARED) 1113 #define INTEL_I2C_IO_F (0x5024 | REGS_SOUTH_SHARED) 1114 #define INTEL_I2C_IO_G (0x5028 | REGS_SOUTH_SHARED) 1115 #define INTEL_I2C_IO_H (0x502c | REGS_SOUTH_SHARED) 1116 // i2c hardware controller 1117 #define INTEL_GMBUS0 (0x5100 | REGS_SOUTH_SHARED) 1118 #define INTEL_GMBUS4 (0x5110 | REGS_SOUTH_SHARED) 1119 1120 #define I2C_CLOCK_DIRECTION_MASK (1 << 0) 1121 #define I2C_CLOCK_DIRECTION_OUT (1 << 1) 1122 #define I2C_CLOCK_VALUE_MASK (1 << 2) 1123 #define I2C_CLOCK_VALUE_OUT (1 << 3) 1124 #define I2C_CLOCK_VALUE_IN (1 << 4) 1125 #define I2C_DATA_DIRECTION_MASK (1 << 8) 1126 #define I2C_DATA_DIRECTION_OUT (1 << 9) 1127 #define I2C_DATA_VALUE_MASK (1 << 10) 1128 #define I2C_DATA_VALUE_OUT (1 << 11) 1129 #define I2C_DATA_VALUE_IN (1 << 12) 1130 #define I2C_RESERVED ((1 << 13) | (1 << 5)) 1131 1132 // gpu block clock gating disable bits 1133 #define INTEL_DSPCLK_GATE_D (0x2020 | REGS_SOUTH_SHARED) 1134 #define PCH_GMBUSUNIT_CLK_GATE_DIS (1UL << 31) 1135 #define INTEL_GEN9_CLKGATE_DIS_4 (0x653c | REGS_NORTH_SHARED) 1136 #define BXT_GMBUSUNIT_CLK_GATE_DIS (1 << 14) 1137 1138 // gpu power wells (confirmed skylake) 1139 #define INTEL_PWR_WELL_CTL_1_BIOS (0x5400 | REGS_NORTH_SHARED) 1140 #define INTEL_PWR_WELL_CTL_2_DRIVER (0x5404 | REGS_NORTH_SHARED) 1141 1142 #define HSW_PWR_WELL_CTL_REQ(i) (0x2 << ((2 * i))) 1143 #define HSW_PWR_WELL_CTL_STATE(i) (0x1 << ((2 * i))) 1144 1145 #define HSW_PWR_WELL_CTL1 INTEL_PWR_WELL_CTL_1_BIOS 1146 #define HSW_PWR_WELL_CTL2 INTEL_PWR_WELL_CTL_2_DRIVER 1147 #define HSW_PWR_WELL_CTL3 (0x5408 | REGS_NORTH_SHARED) 1148 #define HSW_PWR_WELL_CTL4 (0x540c | REGS_NORTH_SHARED) 1149 1150 #define ICL_PWR_WELL_CTL_AUX1 (0x5440 | REGS_NORTH_SHARED) 1151 #define ICL_PWR_WELL_CTL_AUX2 (0x5444 | REGS_NORTH_SHARED) 1152 #define ICL_PWR_WELL_CTL_AUX4 (0x544c | REGS_NORTH_SHARED) 1153 1154 #define ICL_PWR_WELL_CTL_DDI1 (0x5450 | REGS_NORTH_SHARED) 1155 #define ICL_PWR_WELL_CTL_DDI2 (0x5454 | REGS_NORTH_SHARED) 1156 #define ICL_PWR_WELL_CTL_DDI4 (0x545c | REGS_NORTH_SHARED) 1157 1158 // gpu pll enable registers (confirmed skylake) 1159 #define INTEL_WRPLL_CTL_1_DPLL2 (0x6040 | REGS_NORTH_SHARED) 1160 #define INTEL_WRPLL_CTL_2_DPLL3 (0x6060 | REGS_NORTH_SHARED) 1161 #define WRPLL_PLL_ENABLE (1 << 31) 1162 1163 // TODO: on IronLake this is in the north shared block at 0x41000 1164 #define INTEL_VGA_DISPLAY_CONTROL (0x1400 | REGS_NORTH_PLANE_CONTROL) 1165 #define VGA_DISPLAY_DISABLED (1UL << 31) 1166 1167 // LVDS panel 1168 #define INTEL_PANEL_STATUS (0x1200 | REGS_NORTH_PIPE_AND_PORT) 1169 #define INTEL_PANEL_CONTROL (0x1204 | REGS_NORTH_PIPE_AND_PORT) 1170 #define INTEL_PANEL_FIT_CONTROL (0x1230 | REGS_NORTH_PIPE_AND_PORT) 1171 #define INTEL_PANEL_FIT_RATIOS (0x1234 | REGS_NORTH_PIPE_AND_PORT) 1172 1173 // LVDS on IronLake and up 1174 #define PCH_PANEL_STATUS (0x7200 | REGS_SOUTH_SHARED) 1175 #define PCH_PANEL_CONTROL (0x7204 | REGS_SOUTH_SHARED) 1176 #define PCH_PANEL_ON_DELAYS (0x7208 | REGS_SOUTH_SHARED) 1177 #define PCH_PANEL_OFF_DELAYS (0x720c | REGS_SOUTH_SHARED) 1178 #define PCH_PANEL_DIVISOR (0x7210 | REGS_SOUTH_SHARED) 1179 #define PCH_LVDS_DETECTED (1 << 1) 1180 1181 #define PANEL_STATUS_POWER_ON (1UL << 31) 1182 #define PANEL_CONTROL_POWER_TARGET_OFF (0UL << 0) 1183 #define PANEL_CONTROL_POWER_TARGET_ON (1UL << 0) 1184 #define PANEL_CONTROL_POWER_TARGET_RST (1UL << 1) 1185 #define PANEL_REGISTER_UNLOCK (0xabcd << 16) 1186 1187 // PCH_PANEL_ON_DELAYS 1188 #define PANEL_DELAY_PORT_SELECT_MASK (3 << 30) 1189 #define PANEL_DELAY_PORT_SELECT_LVDS (0 << 30) 1190 #define PANEL_DELAY_PORT_SELECT_DPA (1 << 30) 1191 #define PANEL_DELAY_PORT_SELECT_DPC (2 << 30) 1192 #define PANEL_DELAY_PORT_SELECT_DPD (3 << 30) 1193 1194 // PCH_PANEL_DIVISOR 1195 #define PANEL_DIVISOR_REFERENCE_DIV_MASK 0xffffff00 1196 #define PANEL_DIVISOR_REFERENCE_DIV_SHIFT 8 1197 #define PANEL_DIVISOR_POW_CYCLE_DLY_MASK 0x1f 1198 #define PANEL_DIVISOR_POW_CYCLE_DLY_SHIFT 0x1f 1199 1200 // Backlight control registers 1201 // These have moved around, initially they were per pipe, then they were moved in the "north" part 1202 // of the PCH with a single backlight control (independant of pipes), and then moved again to the 1203 // "south" part of the PCH, with a simplified register layout. 1204 #define PCH_BLC_PWM_CTL2 (0x8250 | REGS_NORTH_SHARED) // Linux BLC_PWM_CPU_CTL2 1205 #define PCH_BLC_PWM_CTL (0x8254 | REGS_NORTH_SHARED) // Linux BLC_PWM_CPU_CTL 1206 1207 // Devices after Cannonlake have a new register layout, with separate registers for the period 1208 // and duty cycle instead of having two 16bit values in a 32bit register 1209 #define PCH_SOUTH_BLC_PWM_CONTROL (0x8250 | REGS_SOUTH_SHARED) // Linux _BXT_BLC_PWM_CTL1 1210 #define PCH_SOUTH_BLC_PWM_PERIOD (0x8254 | REGS_SOUTH_SHARED) // Linux _BXT_BLC_PWM_FREQ1 1211 #define PCH_SOUTH_BLC_PWM_DUTY_CYCLE (0x8258 | REGS_SOUTH_SHARED) // Linux _BXT_BLC_PWM_DUTY1 1212 1213 #define MCH_BLC_PWM_CTL (0x1254 | REGS_NORTH_PIPE_AND_PORT) 1214 // Linux VLV_BLC_PWM_CTL (one register per pipe) or BLC_PWM_CTL (a single register that can be 1215 // programmed for use on either pipe) 1216 1217 // ring buffer commands 1218 1219 #define COMMAND_NOOP 0x00 1220 #define COMMAND_WAIT_FOR_EVENT (0x03 << 23) 1221 #define COMMAND_WAIT_FOR_OVERLAY_FLIP (1 << 16) 1222 1223 #define COMMAND_FLUSH (0x04 << 23) 1224 1225 // overlay flip 1226 #define COMMAND_OVERLAY_FLIP (0x11 << 23) 1227 #define COMMAND_OVERLAY_CONTINUE (0 << 21) 1228 #define COMMAND_OVERLAY_ON (1 << 21) 1229 #define COMMAND_OVERLAY_OFF (2 << 21) 1230 #define OVERLAY_UPDATE_COEFFICIENTS 0x1 1231 1232 // 2D acceleration 1233 #define XY_COMMAND_SOURCE_BLIT 0x54c00006 1234 #define XY_COMMAND_COLOR_BLIT 0x54000004 1235 #define XY_COMMAND_SETUP_MONO_PATTERN 0x44400007 1236 #define XY_COMMAND_SCANLINE_BLIT 0x49400001 1237 #define COMMAND_COLOR_BLIT 0x50000003 1238 #define COMMAND_BLIT_RGBA 0x00300000 1239 1240 #define COMMAND_MODE_SOLID_PATTERN 0x80 1241 #define COMMAND_MODE_CMAP8 0x00 1242 #define COMMAND_MODE_RGB15 0x02 1243 #define COMMAND_MODE_RGB16 0x01 1244 #define COMMAND_MODE_RGB32 0x03 1245 1246 // overlay 1247 #define INTEL_OVERLAY_UPDATE 0x30000 1248 #define INTEL_OVERLAY_TEST 0x30004 1249 #define INTEL_OVERLAY_STATUS 0x30008 1250 #define INTEL_OVERLAY_EXTENDED_STATUS 0x3000c 1251 #define INTEL_OVERLAY_GAMMA_5 0x30010 1252 #define INTEL_OVERLAY_GAMMA_4 0x30014 1253 #define INTEL_OVERLAY_GAMMA_3 0x30018 1254 #define INTEL_OVERLAY_GAMMA_2 0x3001c 1255 #define INTEL_OVERLAY_GAMMA_1 0x30020 1256 #define INTEL_OVERLAY_GAMMA_0 0x30024 1257 1258 // FDI - Flexible Display Interface, the interface between the (CPU-internal) 1259 // GPU and the PCH display outputs. Proprietary interface, based on DisplayPort 1260 // though, so similar link training and all... 1261 // There's an FDI transmitter (TX) on the CPU and an FDI receiver (RX) on the 1262 // PCH for each display pipe. 1263 // FDI receiver A is hooked up to transcoder A, FDI receiver B is hooked up to 1264 // transcoder B, so we have the same mapping as with the display pipes. 1265 #define PCH_FDI_RX_BASE_REGISTER 0xf0000 1266 #define PCH_FDI_RX_PIPE_OFFSET 0x01000 1267 #define PCH_FDI_RX_CONTROL 0x00c 1268 #define PCH_FDI_RX_MISC 0x010 1269 #define PCH_FDI_RX_IIR 0x014 1270 #define PCH_FDI_RX_IMR 0x018 1271 1272 #define FDI_RX_ENABLE (1 << 31) 1273 #define FDI_RX_PLL_ENABLED (1 << 13) 1274 1275 #define FDI_RX_LINK_COLOR_SHIFT 16 1276 #define FDI_RX_LINK_BPC(x) ((x) << FDI_RX_LINK_COLOR_SHIFT) 1277 #define FDI_RX_LINK_BPC_MASK (7 << FDI_RX_LINK_COLOR_SHIFT) 1278 1279 // Transcoder - same base as FDI_RX 1280 #define PCH_TRANS_CONF_A 0x0008 1281 #define PCH_TRANS_CONF_B 0x1008 1282 #define PCH_TRANS_CONF_C 0x2008 1283 1284 // Transcoder - skylake DDI 1285 #define DDI_SKL_TRANS_CONF_A (0x0008 | REGS_NORTH_PLANE_CONTROL) 1286 #define DDI_SKL_TRANS_CONF_B (0x1008 | REGS_NORTH_PLANE_CONTROL) 1287 #define DDI_SKL_TRANS_CONF_C (0x2008 | REGS_NORTH_PLANE_CONTROL) 1288 #define DDI_SKL_TRANS_CONF_EDP (0xf008 | REGS_NORTH_PLANE_CONTROL) 1289 1290 #define TRANS_ENABLE (1 << 31) 1291 #define TRANS_ENABLED (1 << 30) 1292 1293 // FDI_tX interrupt register 1294 #define FDI_RX_INTER_LANE_ALIGN (1 << 10) 1295 #define FDI_RX_SYMBOL_LOCK (1 << 9) 1296 #define FDI_RX_BIT_LOCK (1 << 8) 1297 #define FDI_RX_TRAIN_PATTERN_2_FAIL (1 << 7) 1298 #define FDI_RX_FS_CODE_ERR (1 << 6) 1299 #define FDI_RX_FE_CODE_ERR (1 << 5) 1300 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1 << 4) 1301 #define FDI_RX_HDCP_LINK_FAIL (1 << 3) 1302 #define FDI_RX_PIXEL_FIFO_OVERFLOW (1 << 2) 1303 #define FDI_RX_CROSS_CLOCK_OVERFLOW (1 << 1) 1304 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1 << 0) 1305 1306 #define FDI_FS_ERRC_ENABLE (1 << 27) 1307 #define FDI_FE_ERRC_ENABLE (1 << 26) 1308 1309 #define PCH_FDI_RX_TRANS_UNIT_SIZE_1 0x30 1310 #define PCH_FDI_RX_TRANS_UNIT_SIZE_2 0x38 1311 #define FDI_RX_TRANS_UNIT_SIZE(x) ((x - 1) << 25) 1312 #define FDI_RX_TRANS_UNIT_MASK 0x7e000000 1313 1314 #define FDI_RX_ENHANCE_FRAME_ENABLE (1 << 6) 1315 #define FDI_RX_CLOCK_MASK (1 << 4) 1316 #define FDI_RX_CLOCK_RAW (0 << 4) 1317 #define FDI_RX_CLOCK_PCD (1 << 4) 1318 1319 // FDI RX MISC 1320 #define FDI_RX_PWRDN_LANE1_MASK (3 << 26) 1321 #define FDI_RX_PWRDN_LANE1_VAL(x) ((x) << 26) 1322 #define FDI_RX_PWRDN_LANE0_MASK (3 << 24) 1323 #define FDI_RX_PWRDN_LANE0_VAL(x) ((x) << 24) 1324 #define FDI_RX_TP1_TO_TP2_48 (2 << 20) 1325 #define FDI_RX_TP1_TO_TP2_64 (3 << 20) 1326 #define FDI_RX_FDI_DELAY_90 (0x90 << 0) 1327 1328 #define PCH_FDI_TX_BASE_REGISTER 0x60000 1329 #define PCH_FDI_TX_PIPE_OFFSET 0x01000 1330 #define PCH_FDI_TX_CONTROL 0x100 1331 #define FDI_TX_ENABLE (1 << 31) 1332 #define FDI_LINK_TRAIN_PATTERN_1 (0 << 28) 1333 #define FDI_LINK_TRAIN_PATTERN_2 (1 << 28) 1334 #define FDI_LINK_TRAIN_PATTERN_IDLE (2 << 28) 1335 #define FDI_LINK_TRAIN_NONE (3 << 28) 1336 #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0 << 25) 1337 #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1 << 25) 1338 #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2 << 25) 1339 #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3 << 25) 1340 #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0 << 22) 1341 #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1 << 22) 1342 #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2 << 22) 1343 #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3 << 22) 1344 1345 // FDI/PIPE M/N DATA AND LINK VALUES (refreshrate) 1346 #define PCH_FDI_PIPE_A_DATA_M1 (0x0030 | REGS_NORTH_PIPE_AND_PORT) 1347 #define PCH_FDI_PIPE_A_DATA_M2 (0x0038 | REGS_NORTH_PIPE_AND_PORT) 1348 #define PCH_FDI_PIPE_B_DATA_M1 (0x1030 | REGS_NORTH_PIPE_AND_PORT) 1349 #define PCH_FDI_PIPE_B_DATA_M2 (0x1038 | REGS_NORTH_PIPE_AND_PORT) 1350 #define PCH_FDI_PIPE_C_DATA_M1 (0x2030 | REGS_NORTH_PIPE_AND_PORT) 1351 #define PCH_FDI_PIPE_C_DATA_M2 (0x2038 | REGS_NORTH_PIPE_AND_PORT) 1352 #define PCH_FDI_PIPE_A_DATA_N1 (0x0034 | REGS_NORTH_PIPE_AND_PORT) 1353 #define PCH_FDI_PIPE_A_DATA_N2 (0x003c | REGS_NORTH_PIPE_AND_PORT) 1354 #define PCH_FDI_PIPE_B_DATA_N1 (0x1034 | REGS_NORTH_PIPE_AND_PORT) 1355 #define PCH_FDI_PIPE_B_DATA_N2 (0x103c | REGS_NORTH_PIPE_AND_PORT) 1356 #define PCH_FDI_PIPE_C_DATA_N1 (0x2034 | REGS_NORTH_PIPE_AND_PORT) 1357 #define PCH_FDI_PIPE_C_DATA_N2 (0x203c | REGS_NORTH_PIPE_AND_PORT) 1358 #define PCH_FDI_PIPE_A_LINK_M1 (0x0040 | REGS_NORTH_PIPE_AND_PORT) 1359 #define PCH_FDI_PIPE_A_LINK_M2 (0x0048 | REGS_NORTH_PIPE_AND_PORT) 1360 #define PCH_FDI_PIPE_B_LINK_M1 (0x1040 | REGS_NORTH_PIPE_AND_PORT) 1361 #define PCH_FDI_PIPE_B_LINK_M2 (0x1048 | REGS_NORTH_PIPE_AND_PORT) 1362 #define PCH_FDI_PIPE_C_LINK_M1 (0x2040 | REGS_NORTH_PIPE_AND_PORT) 1363 #define PCH_FDI_PIPE_C_LINK_M2 (0x2048 | REGS_NORTH_PIPE_AND_PORT) 1364 #define PCH_FDI_PIPE_A_LINK_N1 (0x0044 | REGS_NORTH_PIPE_AND_PORT) 1365 #define PCH_FDI_PIPE_A_LINK_N2 (0x004c | REGS_NORTH_PIPE_AND_PORT) 1366 #define PCH_FDI_PIPE_B_LINK_N1 (0x1044 | REGS_NORTH_PIPE_AND_PORT) 1367 #define PCH_FDI_PIPE_B_LINK_N2 (0x104c | REGS_NORTH_PIPE_AND_PORT) 1368 #define PCH_FDI_PIPE_C_LINK_N1 (0x2044 | REGS_NORTH_PIPE_AND_PORT) 1369 #define PCH_FDI_PIPE_C_LINK_N2 (0x204c | REGS_NORTH_PIPE_AND_PORT) 1370 #define FDI_PIPE_MN_TU_SIZE_MASK (0x3f << 25) 1371 #define FDI_PIPE_MN_VALUE_MASK (0xffffff << 0) 1372 1373 // SNB A stepping 1374 #define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22) 1375 #define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22) 1376 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22) 1377 #define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x00 << 22) 1378 1379 // SNB B stepping 1380 #define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x00 << 22) 1381 #define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a << 22) 1382 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39 << 22) 1383 #define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38 << 22) 1384 #define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f << 22) 1385 #define FDI_TX_ENHANCE_FRAME_ENABLE (1 << 18) 1386 #define FDI_TX_PLL_ENABLED (1 << 14) 1387 1388 #define FDI_DP_PORT_WIDTH_SHIFT 19 1389 #define FDI_DP_PORT_WIDTH_MASK (7 << FDI_DP_PORT_WIDTH_SHIFT) 1390 #define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT) 1391 1392 #define FDI_PLL_BIOS_0 0x46000 1393 #define FDI_PLL_FB_CLOCK_MASK 0xff 1394 #define FDI_PLL_BIOS_1 0x46004 1395 #define FDI_PLL_BIOS_2 0x46008 1396 1397 #define FDI_AUTO_TRAINING (1 << 10) 1398 #define FDI_AUTO_TRAIN_DONE (1 << 1) 1399 1400 #define FDI_LINK_TRAIN_PATTERN_1_CPT (0 << 8) 1401 #define FDI_LINK_TRAIN_PATTERN_2_CPT (1 << 8) 1402 #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2 << 8) 1403 #define FDI_LINK_TRAIN_NORMAL_CPT (3 << 8) 1404 #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3 << 8) 1405 1406 // IvyBridge changes it up because... they hate developers? 1407 #define FDI_LINK_TRAIN_PATTERN_1_IVB (0 << 8) 1408 #define FDI_LINK_TRAIN_PATTERN_2_IVB (1 << 8) 1409 #define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2 << 8) 1410 #define FDI_LINK_TRAIN_NONE_IVB (3 << 8) 1411 1412 #define PCH_FDI_RXA_CHICKEN (0x200c | REGS_SOUTH_SHARED) 1413 #define PCH_FDI_RXB_CHICKEN (0x2010 | REGS_SOUTH_SHARED) 1414 #define FDI_RX_PHASE_SYNC_POINTER_EN (1 << 0) 1415 #define FDI_RX_PHASE_SYNC_POINTER_OVR (1 << 1) 1416 1417 // CPU Panel Fitters - These are for IronLake and up and are the CPU internal 1418 // panel fitters. 1419 #define PCH_PANEL_FITTER_BASE_REGISTER 0x68000 1420 #define PCH_PANEL_FITTER_PIPE_OFFSET 0x00800 1421 1422 #define PCH_PANEL_FITTER_WINDOW_POS 0x70 1423 #define PCH_PANEL_FITTER_WINDOW_SIZE 0x74 1424 #define PCH_PANEL_FITTER_CONTROL 0x80 1425 //not on IvyBridge: 1426 #define PCH_PANEL_FITTER_V_SCALE 0x84 1427 #define PCH_PANEL_FITTER_H_SCALE 0x90 1428 1429 #define PANEL_FITTER_ENABLED (1 << 31) 1430 //pipes are hardcoded according to offset on SkyLake and later 1431 #define PANEL_FITTER_PIPE_MASK (3 << 29) 1432 #define PANEL_FITTER_PIPE_A (0 << 29) 1433 #define PANEL_FITTER_PIPE_B (1 << 29) 1434 #define PANEL_FITTER_PIPE_C (2 << 29) 1435 #define PANEL_FITTER_SCALING_MODE_MASK (7 << 26) 1436 #define PANEL_FITTER_FILTER_MASK (3 << 24) 1437 1438 struct overlay_scale { 1439 uint32 _reserved0 : 3; 1440 uint32 horizontal_scale_fraction : 12; 1441 uint32 _reserved1 : 1; 1442 uint32 horizontal_downscale_factor : 3; 1443 uint32 _reserved2 : 1; 1444 uint32 vertical_scale_fraction : 12; 1445 }; 1446 1447 #define OVERLAY_FORMAT_RGB15 0x2 1448 #define OVERLAY_FORMAT_RGB16 0x3 1449 #define OVERLAY_FORMAT_RGB32 0x1 1450 #define OVERLAY_FORMAT_YCbCr422 0x8 1451 #define OVERLAY_FORMAT_YCbCr411 0x9 1452 #define OVERLAY_FORMAT_YCbCr420 0xc 1453 1454 #define OVERLAY_MIRROR_NORMAL 0x0 1455 #define OVERLAY_MIRROR_HORIZONTAL 0x1 1456 #define OVERLAY_MIRROR_VERTICAL 0x2 1457 1458 // The real overlay registers are written to using an update buffer 1459 1460 struct overlay_registers { 1461 uint32 buffer_rgb0; 1462 uint32 buffer_rgb1; 1463 uint32 buffer_u0; 1464 uint32 buffer_v0; 1465 uint32 buffer_u1; 1466 uint32 buffer_v1; 1467 // (0x18) OSTRIDE - overlay stride 1468 uint16 stride_rgb; 1469 uint16 stride_uv; 1470 // (0x1c) YRGB_VPH - Y/RGB vertical phase 1471 uint16 vertical_phase0_rgb; 1472 uint16 vertical_phase1_rgb; 1473 // (0x20) UV_VPH - UV vertical phase 1474 uint16 vertical_phase0_uv; 1475 uint16 vertical_phase1_uv; 1476 // (0x24) HORZ_PH - horizontal phase 1477 uint16 horizontal_phase_rgb; 1478 uint16 horizontal_phase_uv; 1479 // (0x28) INIT_PHS - initial phase shift 1480 uint32 initial_vertical_phase0_shift_rgb0 : 4; 1481 uint32 initial_vertical_phase1_shift_rgb0 : 4; 1482 uint32 initial_horizontal_phase_shift_rgb0 : 4; 1483 uint32 initial_vertical_phase0_shift_uv : 4; 1484 uint32 initial_vertical_phase1_shift_uv : 4; 1485 uint32 initial_horizontal_phase_shift_uv : 4; 1486 uint32 _reserved0 : 8; 1487 // (0x2c) DWINPOS - destination window position 1488 uint16 window_left; 1489 uint16 window_top; 1490 // (0x30) DWINSZ - destination window size 1491 uint16 window_width; 1492 uint16 window_height; 1493 // (0x34) SWIDTH - source width 1494 uint16 source_width_rgb; 1495 uint16 source_width_uv; 1496 // (0x38) SWITDHSW - source width in 8 byte steps 1497 uint16 source_bytes_per_row_rgb; 1498 uint16 source_bytes_per_row_uv; 1499 uint16 source_height_rgb; 1500 uint16 source_height_uv; 1501 overlay_scale scale_rgb; 1502 overlay_scale scale_uv; 1503 // (0x48) OCLRC0 - overlay color correction 0 1504 uint32 brightness_correction : 8; // signed, -128 to 127 1505 uint32 _reserved1 : 10; 1506 uint32 contrast_correction : 9; // fixed point: 3.6 bits 1507 uint32 _reserved2 : 5; 1508 // (0x4c) OCLRC1 - overlay color correction 1 1509 uint32 saturation_cos_correction : 10; // fixed point: 3.7 bits 1510 uint32 _reserved3 : 6; 1511 uint32 saturation_sin_correction : 11; // signed fixed point: 3.7 bits 1512 uint32 _reserved4 : 5; 1513 // (0x50) DCLRKV - destination color key value 1514 uint32 color_key_blue : 8; 1515 uint32 color_key_green : 8; 1516 uint32 color_key_red : 8; 1517 uint32 _reserved5 : 8; 1518 // (0x54) DCLRKM - destination color key mask 1519 uint32 color_key_mask_blue : 8; 1520 uint32 color_key_mask_green : 8; 1521 uint32 color_key_mask_red : 8; 1522 uint32 _reserved6 : 7; 1523 uint32 color_key_enabled : 1; 1524 // (0x58) SCHRKVH - source chroma key high value 1525 uint32 source_chroma_key_high_red : 8; 1526 uint32 source_chroma_key_high_blue : 8; 1527 uint32 source_chroma_key_high_green : 8; 1528 uint32 _reserved7 : 8; 1529 // (0x5c) SCHRKVL - source chroma key low value 1530 uint32 source_chroma_key_low_red : 8; 1531 uint32 source_chroma_key_low_blue : 8; 1532 uint32 source_chroma_key_low_green : 8; 1533 uint32 _reserved8 : 8; 1534 // (0x60) SCHRKEN - source chroma key enable 1535 uint32 _reserved9 : 24; 1536 uint32 source_chroma_key_red_enabled : 1; 1537 uint32 source_chroma_key_blue_enabled : 1; 1538 uint32 source_chroma_key_green_enabled : 1; 1539 uint32 _reserved10 : 5; 1540 // (0x64) OCONFIG - overlay configuration 1541 uint32 _reserved11 : 3; 1542 uint32 color_control_output_mode : 1; 1543 uint32 yuv_to_rgb_bypass : 1; 1544 uint32 _reserved12 : 11; 1545 uint32 gamma2_enabled : 1; 1546 uint32 _reserved13 : 1; 1547 uint32 select_pipe : 1; 1548 uint32 slot_time : 8; 1549 uint32 _reserved14 : 5; 1550 // (0x68) OCOMD - overlay command 1551 uint32 overlay_enabled : 1; 1552 uint32 active_field : 1; 1553 uint32 active_buffer : 2; 1554 uint32 test_mode : 1; 1555 uint32 buffer_field_mode : 1; 1556 uint32 _reserved15 : 1; 1557 uint32 tv_flip_field_enabled : 1; 1558 uint32 _reserved16 : 1; 1559 uint32 tv_flip_field_parity : 1; 1560 uint32 source_format : 4; 1561 uint32 ycbcr422_order : 2; 1562 uint32 _reserved18 : 1; 1563 uint32 mirroring_mode : 2; 1564 uint32 _reserved19 : 13; 1565 1566 uint32 _reserved20; 1567 1568 uint32 start_0y; 1569 uint32 start_1y; 1570 uint32 start_0u; 1571 uint32 start_0v; 1572 uint32 start_1u; 1573 uint32 start_1v; 1574 uint32 _reserved21[6]; 1575 #if 0 1576 // (0x70) AWINPOS - alpha blend window position 1577 uint32 awinpos; 1578 // (0x74) AWINSZ - alpha blend window size 1579 uint32 awinsz; 1580 1581 uint32 _reserved21[10]; 1582 #endif 1583 1584 // (0xa0) FASTHSCALE - fast horizontal downscale (strangely enough, 1585 // the next two registers switch the usual Y/RGB vs. UV order) 1586 uint16 horizontal_scale_uv; 1587 uint16 horizontal_scale_rgb; 1588 // (0xa4) UVSCALEV - vertical downscale 1589 uint16 vertical_scale_uv; 1590 uint16 vertical_scale_rgb; 1591 1592 uint32 _reserved22[86]; 1593 1594 // (0x200) polyphase filter coefficients 1595 uint16 vertical_coefficients_rgb[128]; 1596 uint16 horizontal_coefficients_rgb[128]; 1597 1598 uint32 _reserved23[64]; 1599 1600 // (0x500) 1601 uint16 vertical_coefficients_uv[128]; 1602 uint16 horizontal_coefficients_uv[128]; 1603 }; 1604 1605 // i965 overlay support is currently realized using its 3D hardware 1606 #define INTEL_i965_OVERLAY_STATE_SIZE 36864 1607 #define INTEL_i965_3D_CONTEXT_SIZE 32768 1608 1609 inline bool 1610 intel_uses_physical_overlay(intel_shared_info &info) 1611 { 1612 return !info.device_type.InGroup(INTEL_GROUP_Gxx); 1613 } 1614 1615 1616 struct hardware_status { 1617 uint32 interrupt_status_register; 1618 uint32 _reserved0[3]; 1619 void* primary_ring_head_storage; 1620 uint32 _reserved1[3]; 1621 void* secondary_ring_0_head_storage; 1622 void* secondary_ring_1_head_storage; 1623 uint32 _reserved2[2]; 1624 void* binning_head_storage; 1625 uint32 _reserved3[3]; 1626 uint32 store[1008]; 1627 }; 1628 1629 #endif /* INTEL_EXTREME_H */ 1630