1 /* 2 * Copyright 2006-2009, Haiku, Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Axel Dörfler, axeld@pinc-software.de 7 */ 8 #ifndef INTEL_EXTREME_H 9 #define INTEL_EXTREME_H 10 11 12 #include "lock.h" 13 14 #include <Accelerant.h> 15 #include <Drivers.h> 16 #include <PCI.h> 17 18 19 #define VENDOR_ID_INTEL 0x8086 20 21 #define INTEL_TYPE_FAMILY_MASK 0xf000 22 #define INTEL_TYPE_GROUP_MASK 0xfff0 23 #define INTEL_TYPE_MODEL_MASK 0xffff 24 // families 25 #define INTEL_TYPE_7xx 0x1000 26 #define INTEL_TYPE_8xx 0x2000 27 #define INTEL_TYPE_9xx 0x4000 28 // groups 29 #define INTEL_TYPE_83x (INTEL_TYPE_8xx | 0x0010) 30 #define INTEL_TYPE_85x (INTEL_TYPE_8xx | 0x0020) 31 #define INTEL_TYPE_91x (INTEL_TYPE_9xx | 0x0040) 32 #define INTEL_TYPE_94x (INTEL_TYPE_9xx | 0x0080) 33 #define INTEL_TYPE_96x (INTEL_TYPE_9xx | 0x0100) 34 #define INTEL_TYPE_Gxx (INTEL_TYPE_9xx | 0x0200) 35 #define INTEL_TYPE_G4x (INTEL_TYPE_9xx | 0x0400) 36 // models 37 #define INTEL_TYPE_MOBILE 0x0008 38 #define INTEL_TYPE_915 (INTEL_TYPE_91x) 39 #define INTEL_TYPE_945 (INTEL_TYPE_94x) 40 #define INTEL_TYPE_945M (INTEL_TYPE_94x | INTEL_TYPE_MOBILE) 41 #define INTEL_TYPE_965 (INTEL_TYPE_96x) 42 #define INTEL_TYPE_965M (INTEL_TYPE_96x | INTEL_TYPE_MOBILE) 43 #define INTEL_TYPE_G33 (INTEL_TYPE_Gxx) 44 #define INTEL_TYPE_G45 (INTEL_TYPE_G4x) 45 #define INTEL_TYPE_GM45 (INTEL_TYPE_G4x | INTEL_TYPE_MOBILE) 46 47 #define DEVICE_NAME "intel_extreme" 48 #define INTEL_ACCELERANT_NAME "intel_extreme.accelerant" 49 50 struct DeviceType { 51 uint32 type; 52 53 DeviceType(int t) 54 { 55 type = t; 56 } 57 58 DeviceType& operator=(int t) 59 { 60 type = t; 61 return *this; 62 } 63 64 bool InFamily(uint32 family) const 65 { 66 return (type & INTEL_TYPE_FAMILY_MASK) == family; 67 } 68 69 bool InGroup(uint32 group) const 70 { 71 return (type & INTEL_TYPE_GROUP_MASK) == group; 72 } 73 74 bool IsModel(uint32 model) const 75 { 76 return (type & INTEL_TYPE_MODEL_MASK) == model; 77 } 78 }; 79 80 // info about PLL on graphics card 81 struct pll_info { 82 uint32 reference_frequency; 83 uint32 max_frequency; 84 uint32 min_frequency; 85 uint32 divisor_register; 86 }; 87 88 struct ring_buffer { 89 struct lock lock; 90 uint32 register_base; 91 uint32 offset; 92 uint32 size; 93 uint32 position; 94 uint32 space_left; 95 uint8* base; 96 }; 97 98 struct overlay_registers; 99 100 struct intel_shared_info { 101 area_id mode_list_area; // area containing display mode list 102 uint32 mode_count; 103 104 display_mode current_mode; 105 uint32 bytes_per_row; 106 uint32 bits_per_pixel; 107 uint32 dpms_mode; 108 109 area_id registers_area; // area of memory mapped registers 110 uint8* status_page; 111 phys_addr_t physical_status_page; 112 uint8* graphics_memory; 113 phys_addr_t physical_graphics_memory; 114 uint32 graphics_memory_size; 115 116 addr_t frame_buffer; 117 uint32 frame_buffer_offset; 118 119 struct lock accelerant_lock; 120 struct lock engine_lock; 121 122 ring_buffer primary_ring_buffer; 123 124 int32 overlay_channel_used; 125 bool overlay_active; 126 uint32 overlay_token; 127 phys_addr_t physical_overlay_registers; 128 uint32 overlay_offset; 129 130 bool hardware_cursor_enabled; 131 sem_id vblank_sem; 132 133 uint8* cursor_memory; 134 phys_addr_t physical_cursor_memory; 135 uint32 cursor_buffer_offset; 136 uint32 cursor_format; 137 bool cursor_visible; 138 uint16 cursor_hot_x; 139 uint16 cursor_hot_y; 140 141 DeviceType device_type; 142 char device_identifier[32]; 143 struct pll_info pll_info; 144 }; 145 146 //----------------- ioctl() interface ---------------- 147 148 // magic code for ioctls 149 #define INTEL_PRIVATE_DATA_MAGIC 'itic' 150 151 // list ioctls 152 enum { 153 INTEL_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1, 154 155 INTEL_GET_DEVICE_NAME, 156 INTEL_ALLOCATE_GRAPHICS_MEMORY, 157 INTEL_FREE_GRAPHICS_MEMORY 158 }; 159 160 // retrieve the area_id of the kernel/accelerant shared info 161 struct intel_get_private_data { 162 uint32 magic; // magic number 163 area_id shared_info_area; 164 }; 165 166 // allocate graphics memory 167 struct intel_allocate_graphics_memory { 168 uint32 magic; 169 uint32 size; 170 uint32 alignment; 171 uint32 flags; 172 uint32 buffer_base; 173 }; 174 175 // free graphics memory 176 struct intel_free_graphics_memory { 177 uint32 magic; 178 uint32 buffer_base; 179 }; 180 181 //---------------------------------------------------------- 182 // Register definitions, taken from X driver 183 184 // PCI bridge memory management 185 #define INTEL_GRAPHICS_MEMORY_CONTROL 0x52 // GGC - (G)MCH Graphics Control Register 186 #define MEMORY_CONTROL_ENABLED 0x0004 187 #define MEMORY_MASK 0x0001 188 #define STOLEN_MEMORY_MASK 0x00f0 189 #define i965_GTT_MASK 0x000e 190 #define G33_GTT_MASK 0x0300 191 #define G4X_GTT_MASK 0x0f00 // GGMS (GSM Memory Size) mask 192 193 // models i830 and up 194 #define i830_LOCAL_MEMORY_ONLY 0x10 195 #define i830_STOLEN_512K 0x20 196 #define i830_STOLEN_1M 0x30 197 #define i830_STOLEN_8M 0x40 198 #define i830_FRAME_BUFFER_64M 0x01 199 #define i830_FRAME_BUFFER_128M 0x00 200 201 // models i855 and up 202 #define i855_STOLEN_MEMORY_1M 0x10 203 #define i855_STOLEN_MEMORY_4M 0x20 204 #define i855_STOLEN_MEMORY_8M 0x30 205 #define i855_STOLEN_MEMORY_16M 0x40 206 #define i855_STOLEN_MEMORY_32M 0x50 207 #define i855_STOLEN_MEMORY_48M 0x60 208 #define i855_STOLEN_MEMORY_64M 0x70 209 #define i855_STOLEN_MEMORY_128M 0x80 210 #define i855_STOLEN_MEMORY_256M 0x90 211 212 #define G4X_STOLEN_MEMORY_96MB 0xa0 // GMS - Graphics Mode Select 213 #define G4X_STOLEN_MEMORY_160MB 0xb0 214 #define G4X_STOLEN_MEMORY_224MB 0xc0 215 #define G4X_STOLEN_MEMORY_352MB 0xd0 216 217 218 // graphics page translation table 219 #define INTEL_PAGE_TABLE_CONTROL 0x02020 220 #define PAGE_TABLE_ENABLED 0x00000001 221 #define INTEL_PAGE_TABLE_ERROR 0x02024 222 #define INTEL_HARDWARE_STATUS_PAGE 0x02080 223 #define i915_GTT_BASE 0x1c 224 #define i830_GTT_BASE 0x10000 // (- 0x2ffff) 225 #define i830_GTT_SIZE 0x20000 226 #define i965_GTT_BASE 0x80000 // (- 0xfffff) 227 #define i965_GTT_SIZE 0x80000 228 #define i965_GTT_128K (2 << 1) 229 #define i965_GTT_256K (1 << 1) 230 #define i965_GTT_512K (0 << 1) 231 #define G33_GTT_1M (1 << 8) 232 #define G33_GTT_2M (2 << 8) 233 #define G4X_GTT_NONE 0x000 // GGMS - GSM Memory Size 234 #define G4X_GTT_1M_NO_IVT 0x100 // no Intel Virtualization Tech. 235 #define G4X_GTT_2M_NO_IVT 0x300 236 #define G4X_GTT_2M_IVT 0x900 // with Intel Virt. Tech. 237 #define G4X_GTT_3M_IVT 0xa00 238 #define G4X_GTT_4M_IVT 0xb00 239 240 241 #define GTT_ENTRY_VALID 0x01 242 #define GTT_ENTRY_LOCAL_MEMORY 0x02 243 #define GTT_PAGE_SHIFT 12 244 245 // interrupts 246 #define INTEL_INTERRUPT_ENABLED 0x020a0 247 #define INTEL_INTERRUPT_IDENTITY 0x020a4 248 #define INTEL_INTERRUPT_MASK 0x020a8 249 #define INTEL_INTERRUPT_STATUS 0x020ac 250 #define INTERRUPT_VBLANK (1 << 7) 251 252 // ring buffer 253 #define INTEL_PRIMARY_RING_BUFFER 0x02030 254 #define INTEL_SECONDARY_RING_BUFFER_0 0x02100 255 #define INTEL_SECONDARY_RING_BUFFER_1 0x02110 256 // offsets for the ring buffer base registers above 257 #define RING_BUFFER_TAIL 0x0 258 #define RING_BUFFER_HEAD 0x4 259 #define RING_BUFFER_START 0x8 260 #define RING_BUFFER_CONTROL 0xc 261 #define INTEL_RING_BUFFER_SIZE_MASK 0x001ff000 262 #define INTEL_RING_BUFFER_HEAD_MASK 0x001ffffc 263 #define INTEL_RING_BUFFER_ENABLED 1 264 265 // display ports 266 #define INTEL_DISPLAY_A_ANALOG_PORT 0x61100 267 #define DISPLAY_MONITOR_PORT_ENABLED (1UL << 31) 268 #define DISPLAY_MONITOR_PIPE_B (1UL << 30) 269 #define DISPLAY_MONITOR_VGA_POLARITY (1UL << 15) 270 #define DISPLAY_MONITOR_MODE_MASK (3UL << 10) 271 #define DISPLAY_MONITOR_ON 0 272 #define DISPLAY_MONITOR_SUSPEND (1UL << 10) 273 #define DISPLAY_MONITOR_STAND_BY (2UL << 10) 274 #define DISPLAY_MONITOR_OFF (3UL << 10) 275 #define DISPLAY_MONITOR_POLARITY_MASK (3UL << 3) 276 #define DISPLAY_MONITOR_POSITIVE_HSYNC (1UL << 3) 277 #define DISPLAY_MONITOR_POSITIVE_VSYNC (2UL << 3) 278 #define INTEL_DISPLAY_A_DIGITAL_PORT 0x61120 279 #define INTEL_DISPLAY_C_DIGITAL 0x61160 280 #define INTEL_DISPLAY_LVDS_PORT 0x61180 281 #define LVDS_POST2_RATE_SLOW 14 // PLL Divisors 282 #define LVDS_POST2_RATE_FAST 7 283 #define LVDS_CLKB_POWER_MASK (3 << 4) 284 #define LVDS_CLKB_POWER_UP (3 << 4) 285 #define LVDS_PORT_EN (1 << 31) 286 #define LVDS_A0A2_CLKA_POWER_UP (3 << 8) 287 #define LVDS_PIPEB_SELECT (1 << 30) 288 #define LVDS_B0B3PAIRS_POWER_UP (3 << 2) 289 #define LVDS_PLL_MODE_LVDS (2 << 26) 290 291 // PLL flags 292 #define DISPLAY_PLL_ENABLED (1UL << 31) 293 #define DISPLAY_PLL_2X_CLOCK (1UL << 30) 294 #define DISPLAY_PLL_SYNC_LOCK_ENABLED (1UL << 29) 295 #define DISPLAY_PLL_NO_VGA_CONTROL (1UL << 28) 296 #define DISPLAY_PLL_MODE_ANALOG (1UL << 26) 297 #define DISPLAY_PLL_DIVIDE_HIGH (1UL << 24) 298 #define DISPLAY_PLL_DIVIDE_4X (1UL << 23) 299 #define DISPLAY_PLL_POST1_DIVIDE_2 (1UL << 21) 300 #define DISPLAY_PLL_POST1_DIVISOR_MASK 0x001f0000 301 #define DISPLAY_PLL_9xx_POST1_DIVISOR_MASK 0x00ff0000 302 #define DISPLAY_PLL_POST1_DIVISOR_SHIFT 16 303 #define DISPLAY_PLL_DIVISOR_1 (1UL << 8) 304 #define DISPLAY_PLL_N_DIVISOR_MASK 0x001f0000 305 #define DISPLAY_PLL_M1_DIVISOR_MASK 0x00001f00 306 #define DISPLAY_PLL_M2_DIVISOR_MASK 0x0000001f 307 #define DISPLAY_PLL_N_DIVISOR_SHIFT 16 308 #define DISPLAY_PLL_M1_DIVISOR_SHIFT 8 309 #define DISPLAY_PLL_M2_DIVISOR_SHIFT 0 310 #define DISPLAY_PLL_PULSE_PHASE_SHIFT 9 311 312 // display A 313 #define INTEL_DISPLAY_A_HTOTAL 0x60000 314 #define INTEL_DISPLAY_A_HBLANK 0x60004 315 #define INTEL_DISPLAY_A_HSYNC 0x60008 316 #define INTEL_DISPLAY_A_VTOTAL 0x6000c 317 #define INTEL_DISPLAY_A_VBLANK 0x60010 318 #define INTEL_DISPLAY_A_VSYNC 0x60014 319 #define INTEL_DISPLAY_A_IMAGE_SIZE 0x6001c 320 321 #define INTEL_DISPLAY_A_CONTROL 0x70180 322 #define INTEL_DISPLAY_A_BASE 0x70184 323 #define INTEL_DISPLAY_A_BYTES_PER_ROW 0x70188 324 #define INTEL_DISPLAY_A_SURFACE 0x7019c // i965 and up only 325 #define DISPLAY_CONTROL_ENABLED (1UL << 31) 326 #define DISPLAY_CONTROL_GAMMA (1UL << 30) 327 #define DISPLAY_CONTROL_COLOR_MASK (0x0fUL << 26) 328 #define DISPLAY_CONTROL_CMAP8 (2UL << 26) 329 #define DISPLAY_CONTROL_RGB15 (4UL << 26) 330 #define DISPLAY_CONTROL_RGB16 (5UL << 26) 331 #define DISPLAY_CONTROL_RGB32 (6UL << 26) 332 333 #define INTEL_VGA_DISPLAY_CONTROL 0x71400 334 #define VGA_DISPLAY_DISABLED (1UL << 31) 335 336 #define INTEL_DISPLAY_A_PALETTE 0x0a000 337 338 #define INTEL_DISPLAY_A_PIPE_CONTROL 0x70008 339 #define DISPLAY_PIPE_ENABLED (1UL << 31) 340 #define INTEL_DISPLAY_A_PIPE_STATUS 0x70024 341 #define DISPLAY_PIPE_VBLANK_ENABLED (1UL << 17) 342 #define DISPLAY_PIPE_VBLANK_STATUS (1UL << 1) 343 344 #define INTEL_DISPLAY_A_PLL 0x06014 345 #define INTEL_DISPLAY_A_PLL_DIVISOR_0 0x06040 346 #define INTEL_DISPLAY_A_PLL_DIVISOR_1 0x06044 347 348 // display B 349 #define INTEL_DISPLAY_B_HTOTAL 0x61000 350 #define INTEL_DISPLAY_B_HBLANK 0x61004 351 #define INTEL_DISPLAY_B_HSYNC 0x61008 352 #define INTEL_DISPLAY_B_VTOTAL 0x6100c 353 #define INTEL_DISPLAY_B_VBLANK 0x61010 354 #define INTEL_DISPLAY_B_VSYNC 0x61014 355 356 #define INTEL_DISPLAY_B_DIGITAL_PORT 0x61140 357 #define INTEL_DISPLAY_B_PIPE_SIZE 0x71190 358 359 #define INTEL_DISPLAY_B_PIPE_CONTROL 0x71008 360 361 #define INTEL_DISPLAY_B_CONTROL 0x71180 362 #define INTEL_DISPLAY_B_BASE 0x71184 363 #define INTEL_DISPLAY_B_BYTES_PER_ROW 0x71188 364 #define INTEL_DISPLAY_B_POS 0x7118C 365 366 #define INTEL_DISPLAY_B_IMAGE_SIZE 0x6101c 367 #define INTEL_DISPLAY_B_SURFACE 0x7119c // i965 and up only 368 369 #define INTEL_DISPLAY_B_PALETTE 0x0a800 370 371 #define INTEL_DISPLAY_B_PLL 0x06018 372 #define INTEL_DISPLAY_B_PLL_MULTIPLIER_DIVISOR 0x06020 373 #define INTEL_DISPLAY_B_PLL_DIVISOR_0 0x06048 374 #define INTEL_DISPLAY_B_PLL_DIVISOR_1 0x0604c 375 376 // LVDS panel 377 #define INTEL_PANEL_STATUS 0x61200 378 #define PANEL_STATUS_POWER_ON (1UL << 31) 379 #define INTEL_PANEL_CONTROL 0x61204 380 #define PANEL_CONTROL_POWER_TARGET_ON (1UL << 0) 381 #define INTEL_PANEL_FIT_CONTROL 0x61230 382 #define INTEL_PANEL_FIT_RATIOS 0x61234 383 384 // cursor 385 #define INTEL_CURSOR_CONTROL 0x70080 386 #define INTEL_CURSOR_BASE 0x70084 387 #define INTEL_CURSOR_POSITION 0x70088 388 #define INTEL_CURSOR_PALETTE 0x70090 // (- 0x7009f) 389 #define INTEL_CURSOR_SIZE 0x700a0 390 #define CURSOR_ENABLED (1UL << 31) 391 #define CURSOR_FORMAT_2_COLORS (0UL << 24) 392 #define CURSOR_FORMAT_3_COLORS (1UL << 24) 393 #define CURSOR_FORMAT_4_COLORS (2UL << 24) 394 #define CURSOR_FORMAT_ARGB (4UL << 24) 395 #define CURSOR_FORMAT_XRGB (5UL << 24) 396 #define CURSOR_POSITION_NEGATIVE 0x8000 397 #define CURSOR_POSITION_MASK 0x3fff 398 399 // ring buffer commands 400 401 #define COMMAND_NOOP 0x00 402 #define COMMAND_WAIT_FOR_EVENT (0x03 << 23) 403 #define COMMAND_WAIT_FOR_OVERLAY_FLIP (1 << 16) 404 405 #define COMMAND_FLUSH (0x04 << 23) 406 407 // overlay flip 408 #define COMMAND_OVERLAY_FLIP (0x11 << 23) 409 #define COMMAND_OVERLAY_CONTINUE (0 << 21) 410 #define COMMAND_OVERLAY_ON (1 << 21) 411 #define COMMAND_OVERLAY_OFF (2 << 21) 412 #define OVERLAY_UPDATE_COEFFICIENTS 0x1 413 414 // 2D acceleration 415 #define XY_COMMAND_SOURCE_BLIT 0x54c00006 416 #define XY_COMMAND_COLOR_BLIT 0x54000004 417 #define XY_COMMAND_SETUP_MONO_PATTERN 0x44400007 418 #define XY_COMMAND_SCANLINE_BLIT 0x49400001 419 #define COMMAND_COLOR_BLIT 0x50000003 420 #define COMMAND_BLIT_RGBA 0x00300000 421 422 #define COMMAND_MODE_SOLID_PATTERN 0x80 423 #define COMMAND_MODE_CMAP8 0x00 424 #define COMMAND_MODE_RGB15 0x02 425 #define COMMAND_MODE_RGB16 0x01 426 #define COMMAND_MODE_RGB32 0x03 427 428 // i2c 429 430 #define INTEL_I2C_IO_A 0x5010 431 #define INTEL_I2C_IO_B 0x5014 432 #define INTEL_I2C_IO_C 0x5018 433 #define INTEL_I2C_IO_D 0x501c 434 #define INTEL_I2C_IO_E 0x5020 435 #define INTEL_I2C_IO_F 0x5024 436 #define INTEL_I2C_IO_G 0x5028 437 #define INTEL_I2C_IO_H 0x502c 438 439 #define I2C_CLOCK_DIRECTION_MASK (1 << 0) 440 #define I2C_CLOCK_DIRECTION_OUT (1 << 1) 441 #define I2C_CLOCK_VALUE_MASK (1 << 2) 442 #define I2C_CLOCK_VALUE_OUT (1 << 3) 443 #define I2C_CLOCK_VALUE_IN (1 << 4) 444 #define I2C_DATA_DIRECTION_MASK (1 << 8) 445 #define I2C_DATA_DIRECTION_OUT (1 << 9) 446 #define I2C_DATA_VALUE_MASK (1 << 10) 447 #define I2C_DATA_VALUE_OUT (1 << 11) 448 #define I2C_DATA_VALUE_IN (1 << 12) 449 #define I2C_RESERVED ((1 << 13) | (1 << 5)) 450 451 // overlay 452 453 #define INTEL_OVERLAY_UPDATE 0x30000 454 #define INTEL_OVERLAY_TEST 0x30004 455 #define INTEL_OVERLAY_STATUS 0x30008 456 #define INTEL_OVERLAY_EXTENDED_STATUS 0x3000c 457 #define INTEL_OVERLAY_GAMMA_5 0x30010 458 #define INTEL_OVERLAY_GAMMA_4 0x30014 459 #define INTEL_OVERLAY_GAMMA_3 0x30018 460 #define INTEL_OVERLAY_GAMMA_2 0x3001c 461 #define INTEL_OVERLAY_GAMMA_1 0x30020 462 #define INTEL_OVERLAY_GAMMA_0 0x30024 463 464 struct overlay_scale { 465 uint32 _reserved0 : 3; 466 uint32 horizontal_scale_fraction : 12; 467 uint32 _reserved1 : 1; 468 uint32 horizontal_downscale_factor : 3; 469 uint32 _reserved2 : 1; 470 uint32 vertical_scale_fraction : 12; 471 }; 472 473 #define OVERLAY_FORMAT_RGB15 0x2 474 #define OVERLAY_FORMAT_RGB16 0x3 475 #define OVERLAY_FORMAT_RGB32 0x1 476 #define OVERLAY_FORMAT_YCbCr422 0x8 477 #define OVERLAY_FORMAT_YCbCr411 0x9 478 #define OVERLAY_FORMAT_YCbCr420 0xc 479 480 #define OVERLAY_MIRROR_NORMAL 0x0 481 #define OVERLAY_MIRROR_HORIZONTAL 0x1 482 #define OVERLAY_MIRROR_VERTICAL 0x2 483 484 // The real overlay registers are written to using an update buffer 485 486 struct overlay_registers { 487 uint32 buffer_rgb0; 488 uint32 buffer_rgb1; 489 uint32 buffer_u0; 490 uint32 buffer_v0; 491 uint32 buffer_u1; 492 uint32 buffer_v1; 493 // (0x18) OSTRIDE - overlay stride 494 uint16 stride_rgb; 495 uint16 stride_uv; 496 // (0x1c) YRGB_VPH - Y/RGB vertical phase 497 uint16 vertical_phase0_rgb; 498 uint16 vertical_phase1_rgb; 499 // (0x20) UV_VPH - UV vertical phase 500 uint16 vertical_phase0_uv; 501 uint16 vertical_phase1_uv; 502 // (0x24) HORZ_PH - horizontal phase 503 uint16 horizontal_phase_rgb; 504 uint16 horizontal_phase_uv; 505 // (0x28) INIT_PHS - initial phase shift 506 uint32 initial_vertical_phase0_shift_rgb0 : 4; 507 uint32 initial_vertical_phase1_shift_rgb0 : 4; 508 uint32 initial_horizontal_phase_shift_rgb0 : 4; 509 uint32 initial_vertical_phase0_shift_uv : 4; 510 uint32 initial_vertical_phase1_shift_uv : 4; 511 uint32 initial_horizontal_phase_shift_uv : 4; 512 uint32 _reserved0 : 8; 513 // (0x2c) DWINPOS - destination window position 514 uint16 window_left; 515 uint16 window_top; 516 // (0x30) DWINSZ - destination window size 517 uint16 window_width; 518 uint16 window_height; 519 // (0x34) SWIDTH - source width 520 uint16 source_width_rgb; 521 uint16 source_width_uv; 522 // (0x38) SWITDHSW - source width in 8 byte steps 523 uint16 source_bytes_per_row_rgb; 524 uint16 source_bytes_per_row_uv; 525 uint16 source_height_rgb; 526 uint16 source_height_uv; 527 overlay_scale scale_rgb; 528 overlay_scale scale_uv; 529 // (0x48) OCLRC0 - overlay color correction 0 530 uint32 brightness_correction : 8; // signed, -128 to 127 531 uint32 _reserved1 : 10; 532 uint32 contrast_correction : 9; // fixed point: 3.6 bits 533 uint32 _reserved2 : 5; 534 // (0x4c) OCLRC1 - overlay color correction 1 535 uint32 saturation_cos_correction : 10; // fixed point: 3.7 bits 536 uint32 _reserved3 : 6; 537 uint32 saturation_sin_correction : 11; // signed fixed point: 3.7 bits 538 uint32 _reserved4 : 5; 539 // (0x50) DCLRKV - destination color key value 540 uint32 color_key_blue : 8; 541 uint32 color_key_green : 8; 542 uint32 color_key_red : 8; 543 uint32 _reserved5 : 8; 544 // (0x54) DCLRKM - destination color key mask 545 uint32 color_key_mask_blue : 8; 546 uint32 color_key_mask_green : 8; 547 uint32 color_key_mask_red : 8; 548 uint32 _reserved6 : 7; 549 uint32 color_key_enabled : 1; 550 // (0x58) SCHRKVH - source chroma key high value 551 uint32 source_chroma_key_high_red : 8; 552 uint32 source_chroma_key_high_blue : 8; 553 uint32 source_chroma_key_high_green : 8; 554 uint32 _reserved7 : 8; 555 // (0x5c) SCHRKVL - source chroma key low value 556 uint32 source_chroma_key_low_red : 8; 557 uint32 source_chroma_key_low_blue : 8; 558 uint32 source_chroma_key_low_green : 8; 559 uint32 _reserved8 : 8; 560 // (0x60) SCHRKEN - source chroma key enable 561 uint32 _reserved9 : 24; 562 uint32 source_chroma_key_red_enabled : 1; 563 uint32 source_chroma_key_blue_enabled : 1; 564 uint32 source_chroma_key_green_enabled : 1; 565 uint32 _reserved10 : 5; 566 // (0x64) OCONFIG - overlay configuration 567 uint32 _reserved11 : 3; 568 uint32 color_control_output_mode : 1; 569 uint32 yuv_to_rgb_bypass : 1; 570 uint32 _reserved12 : 11; 571 uint32 gamma2_enabled : 1; 572 uint32 _reserved13 : 1; 573 uint32 select_pipe : 1; 574 uint32 slot_time : 8; 575 uint32 _reserved14 : 5; 576 // (0x68) OCOMD - overlay command 577 uint32 overlay_enabled : 1; 578 uint32 active_field : 1; 579 uint32 active_buffer : 2; 580 uint32 test_mode : 1; 581 uint32 buffer_field_mode : 1; 582 uint32 _reserved15 : 1; 583 uint32 tv_flip_field_enabled : 1; 584 uint32 _reserved16 : 1; 585 uint32 tv_flip_field_parity : 1; 586 uint32 source_format : 4; 587 uint32 ycbcr422_order : 2; 588 uint32 _reserved18 : 1; 589 uint32 mirroring_mode : 2; 590 uint32 _reserved19 : 13; 591 592 uint32 _reserved20; 593 594 uint32 start_0y; 595 uint32 start_1y; 596 uint32 start_0u; 597 uint32 start_0v; 598 uint32 start_1u; 599 uint32 start_1v; 600 uint32 _reserved21[6]; 601 #if 0 602 // (0x70) AWINPOS - alpha blend window position 603 uint32 awinpos; 604 // (0x74) AWINSZ - alpha blend window size 605 uint32 awinsz; 606 607 uint32 _reserved21[10]; 608 #endif 609 610 // (0xa0) FASTHSCALE - fast horizontal downscale (strangely enough, 611 // the next two registers switch the usual Y/RGB vs. UV order) 612 uint16 horizontal_scale_uv; 613 uint16 horizontal_scale_rgb; 614 // (0xa4) UVSCALEV - vertical downscale 615 uint16 vertical_scale_uv; 616 uint16 vertical_scale_rgb; 617 618 uint32 _reserved22[86]; 619 620 // (0x200) polyphase filter coefficients 621 uint16 vertical_coefficients_rgb[128]; 622 uint16 horizontal_coefficients_rgb[128]; 623 624 uint32 _reserved23[64]; 625 626 // (0x500) 627 uint16 vertical_coefficients_uv[128]; 628 uint16 horizontal_coefficients_uv[128]; 629 }; 630 631 // i965 overlay support is currently realized using its 3D hardware 632 #define INTEL_i965_OVERLAY_STATE_SIZE 36864 633 #define INTEL_i965_3D_CONTEXT_SIZE 32768 634 635 inline bool 636 intel_uses_physical_overlay(intel_shared_info &info) 637 { 638 return !info.device_type.InGroup(INTEL_TYPE_Gxx); 639 } 640 641 642 struct hardware_status { 643 uint32 interrupt_status_register; 644 uint32 _reserved0[3]; 645 void* primary_ring_head_storage; 646 uint32 _reserved1[3]; 647 void* secondary_ring_0_head_storage; 648 void* secondary_ring_1_head_storage; 649 uint32 _reserved2[2]; 650 void* binning_head_storage; 651 uint32 _reserved3[3]; 652 uint32 store[1008]; 653 }; 654 655 #endif /* INTEL_EXTREME_H */ 656