1 /* 2 * Copyright 2006-2016, Haiku, Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Axel Dörfler, axeld@pinc-software.de 7 * Alexander von Gluck, kallisti5@unixzen.com 8 */ 9 #ifndef INTEL_EXTREME_H 10 #define INTEL_EXTREME_H 11 12 13 #include "lock.h" 14 15 #include <Accelerant.h> 16 #include <Drivers.h> 17 #include <PCI.h> 18 19 #include <edid.h> 20 21 22 #define VENDOR_ID_INTEL 0x8086 23 24 #define INTEL_FAMILY_MASK 0x00ff0000 25 #define INTEL_GROUP_MASK 0x00fffff0 26 #define INTEL_MODEL_MASK 0x00ffffff 27 #define INTEL_TYPE_MASK 0x0000000f 28 29 // families 30 #define INTEL_FAMILY_8xx 0x00020000 // Second Gen 31 #define INTEL_FAMILY_9xx 0x00040000 // Third Gen + 32 #define INTEL_FAMILY_SER5 0x00080000 // Intel5 Series 33 #define INTEL_FAMILY_SOC0 0x00200000 // Atom SOC 34 #define INTEL_FAMILY_LAKE 0x00400000 // Intel Lakes 35 36 // groups 37 #define INTEL_GROUP_83x (INTEL_FAMILY_8xx | 0x0010) 38 #define INTEL_GROUP_85x (INTEL_FAMILY_8xx | 0x0020) 39 #define INTEL_GROUP_91x (INTEL_FAMILY_9xx | 0x0010) 40 #define INTEL_GROUP_94x (INTEL_FAMILY_9xx | 0x0020) 41 #define INTEL_GROUP_96x (INTEL_FAMILY_9xx | 0x0040) 42 #define INTEL_GROUP_Gxx (INTEL_FAMILY_9xx | 0x0080) 43 #define INTEL_GROUP_G4x (INTEL_FAMILY_9xx | 0x0100) 44 #define INTEL_GROUP_PIN (INTEL_FAMILY_9xx | 0x0200) // PineView 45 #define INTEL_GROUP_ILK (INTEL_FAMILY_SER5 | 0x0010) // IronLake 46 #define INTEL_GROUP_SNB (INTEL_FAMILY_SER5 | 0x0020) // SandyBridge 47 #define INTEL_GROUP_IVB (INTEL_FAMILY_SER5 | 0x0040) // IvyBridge 48 #define INTEL_GROUP_HAS (INTEL_FAMILY_SER5 | 0x0080) // Haswell 49 #define INTEL_GROUP_VLV (INTEL_FAMILY_SOC0 | 0x0010) // ValleyView 50 #define INTEL_GROUP_CHV (INTEL_FAMILY_SOC0 | 0x0020) // CherryView 51 #define INTEL_GROUP_BDW (INTEL_FAMILY_SOC0 | 0x0040) // Broadwell 52 #define INTEL_GROUP_SKY (INTEL_FAMILY_LAKE | 0x0010) // SkyLake 53 #define INTEL_GROUP_KBY (INTEL_FAMILY_LAKE | 0x0020) // KabyLake 54 #define INTEL_GROUP_CFL (INTEL_FAMILY_LAKE | 0x0040) // CoffeeLake 55 #define INTEL_GROUP_CML (INTEL_FAMILY_LAKE | 0x0080) // CometLake 56 // models 57 #define INTEL_TYPE_SERVER 0x0004 58 #define INTEL_TYPE_MOBILE 0x0008 59 #define INTEL_MODEL_915 (INTEL_GROUP_91x) 60 #define INTEL_MODEL_915M (INTEL_GROUP_91x | INTEL_TYPE_MOBILE) 61 #define INTEL_MODEL_945 (INTEL_GROUP_94x) 62 #define INTEL_MODEL_945M (INTEL_GROUP_94x | INTEL_TYPE_MOBILE) 63 #define INTEL_MODEL_965 (INTEL_GROUP_96x) 64 #define INTEL_MODEL_965M (INTEL_GROUP_96x | INTEL_TYPE_MOBILE) 65 #define INTEL_MODEL_G33 (INTEL_GROUP_Gxx) 66 #define INTEL_MODEL_G45 (INTEL_GROUP_G4x) 67 #define INTEL_MODEL_GM45 (INTEL_GROUP_G4x | INTEL_TYPE_MOBILE) 68 #define INTEL_MODEL_PINE (INTEL_GROUP_PIN) 69 #define INTEL_MODEL_PINEM (INTEL_GROUP_PIN | INTEL_TYPE_MOBILE) 70 #define INTEL_MODEL_ILKG (INTEL_GROUP_ILK) 71 #define INTEL_MODEL_ILKGM (INTEL_GROUP_ILK | INTEL_TYPE_MOBILE) 72 #define INTEL_MODEL_SNBG (INTEL_GROUP_SNB) 73 #define INTEL_MODEL_SNBGM (INTEL_GROUP_SNB | INTEL_TYPE_MOBILE) 74 #define INTEL_MODEL_SNBGS (INTEL_GROUP_SNB | INTEL_TYPE_SERVER) 75 #define INTEL_MODEL_IVBG (INTEL_GROUP_IVB) 76 #define INTEL_MODEL_IVBGM (INTEL_GROUP_IVB | INTEL_TYPE_MOBILE) 77 #define INTEL_MODEL_IVBGS (INTEL_GROUP_IVB | INTEL_TYPE_SERVER) 78 #define INTEL_MODEL_HAS (INTEL_GROUP_HAS) 79 #define INTEL_MODEL_HASM (INTEL_GROUP_HAS | INTEL_TYPE_MOBILE) 80 #define INTEL_MODEL_VLV (INTEL_GROUP_VLV) 81 #define INTEL_MODEL_VLVM (INTEL_GROUP_VLV | INTEL_TYPE_MOBILE) 82 #define INTEL_MODEL_BDW (INTEL_GROUP_BDW) 83 #define INTEL_MODEL_BDWM (INTEL_GROUP_BDW | INTEL_TYPE_MOBILE) 84 #define INTEL_MODEL_SKY (INTEL_GROUP_SKY) 85 #define INTEL_MODEL_SKYM (INTEL_GROUP_SKY | INTEL_TYPE_MOBILE) 86 #define INTEL_MODEL_SKYS (INTEL_GROUP_SKY | INTEL_TYPE_SERVER) 87 #define INTEL_MODEL_KBY (INTEL_GROUP_KBY) 88 #define INTEL_MODEL_KBYM (INTEL_GROUP_KBY | INTEL_TYPE_MOBILE) 89 #define INTEL_MODEL_CFL (INTEL_GROUP_CFL) 90 #define INTEL_MODEL_CFLM (INTEL_GROUP_CFL | INTEL_TYPE_MOBILE) 91 #define INTEL_MODEL_CML (INTEL_GROUP_CML) 92 93 #define INTEL_PCH_DEVICE_ID_MASK 0xff80 94 #define INTEL_PCH_IBX_DEVICE_ID 0x3b00 95 #define INTEL_PCH_CPT_DEVICE_ID 0x1c00 96 #define INTEL_PCH_PPT_DEVICE_ID 0x1e00 97 #define INTEL_PCH_LPT_DEVICE_ID 0x8c00 98 #define INTEL_PCH_LPT_LP_DEVICE_ID 0x9c00 99 #define INTEL_PCH_WPT_DEVICE_ID 0x8c80 100 #define INTEL_PCH_WPT_LP_DEVICE_ID 0x9c80 101 #define INTEL_PCH_SPT_DEVICE_ID 0xa100 102 #define INTEL_PCH_SPT_LP_DEVICE_ID 0x9d00 103 #define INTEL_PCH_KBP_DEVICE_ID 0xa280 104 #define INTEL_PCH_CNP_DEVICE_ID 0xa300 105 #define INTEL_PCH_CNP_LP_DEVICE_ID 0x9d80 106 #define INTEL_PCH_CMP_DEVICE_ID 0x0280 107 #define INTEL_PCH_CMP2_DEVICE_ID 0x0680 108 #define INTEL_PCH_CMP_V_DEVICE_ID 0xa380 109 #define INTEL_PCH_ICP_DEVICE_ID 0x3480 110 #define INTEL_PCH_MCC_DEVICE_ID 0x4b00 111 #define INTEL_PCH_TGP_DEVICE_ID 0xa080 112 #define INTEL_PCH_TGP2_DEVICE_ID 0x4380 113 #define INTEL_PCH_JSP_DEVICE_ID 0x4d80 114 #define INTEL_PCH_JSP2_DEVICE_ID 0x3880 115 #define INTEL_PCH_ADP_DEVICE_ID 0x7a80 116 #define INTEL_PCH_ADP2_DEVICE_ID 0x5180 117 #define INTEL_PCH_P2X_DEVICE_ID 0x7100 118 #define INTEL_PCH_P3X_DEVICE_ID 0x7000 119 120 // ValleyView MMIO offset 121 #define VLV_DISPLAY_BASE 0x180000 122 123 #define DEVICE_NAME "intel_extreme" 124 #define INTEL_ACCELERANT_NAME "intel_extreme.accelerant" 125 126 // We encode the register block into the value and extract/translate it when 127 // actually accessing. 128 #define REGISTER_BLOCK_COUNT 6 129 #define REGISTER_BLOCK_SHIFT 24 130 #define REGISTER_BLOCK_MASK 0xff000000 131 #define REGISTER_REGISTER_MASK 0x00ffffff 132 #define REGISTER_BLOCK(x) ((x & REGISTER_BLOCK_MASK) >> REGISTER_BLOCK_SHIFT) 133 #define REGISTER_REGISTER(x) (x & REGISTER_REGISTER_MASK) 134 135 #define REGS_FLAT (0 << REGISTER_BLOCK_SHIFT) 136 #define REGS_NORTH_SHARED (1 << REGISTER_BLOCK_SHIFT) 137 #define REGS_NORTH_PIPE_AND_PORT (2 << REGISTER_BLOCK_SHIFT) 138 #define REGS_NORTH_PLANE_CONTROL (3 << REGISTER_BLOCK_SHIFT) 139 #define REGS_SOUTH_SHARED (4 << REGISTER_BLOCK_SHIFT) 140 #define REGS_SOUTH_TRANSCODER_PORT (5 << REGISTER_BLOCK_SHIFT) 141 142 // register blocks for (G)MCH/ICH based platforms 143 #define MCH_SHARED_REGISTER_BASE 0x00000 144 #define MCH_PIPE_AND_PORT_REGISTER_BASE 0x60000 145 #define MCH_PLANE_CONTROL_REGISTER_BASE 0x70000 146 147 #define ICH_SHARED_REGISTER_BASE 0x00000 148 #define ICH_PORT_REGISTER_BASE 0x60000 149 150 // PCH - Platform Control Hub - Some hardware moves from a MCH/ICH based 151 // setup to a PCH based one, that means anything that used to communicate via 152 // (G)MCH registers needs to use different ones on PCH based platforms 153 // (Ironlake, SandyBridge, IvyBridge, Some Haswell). 154 #define PCH_NORTH_SHARED_REGISTER_BASE 0x40000 155 #define PCH_NORTH_PIPE_AND_PORT_REGISTER_BASE 0x60000 156 #define PCH_NORTH_PLANE_CONTROL_REGISTER_BASE 0x70000 157 #define PCH_SOUTH_SHARED_REGISTER_BASE 0xc0000 158 #define PCH_SOUTH_TRANSCODER_AND_PORT_REGISTER_BASE 0xe0000 159 160 161 struct DeviceType { 162 uint32 type; 163 164 DeviceType(int t) 165 { 166 type = t; 167 } 168 169 DeviceType& operator=(int t) 170 { 171 type = t; 172 return *this; 173 } 174 175 bool InFamily(uint32 family) const 176 { 177 return (type & INTEL_FAMILY_MASK) == family; 178 } 179 180 bool InGroup(uint32 group) const 181 { 182 return (type & INTEL_GROUP_MASK) == group; 183 } 184 185 bool IsModel(uint32 model) const 186 { 187 return (type & INTEL_MODEL_MASK) == model; 188 } 189 190 bool IsMobile() const 191 { 192 return (type & INTEL_TYPE_MASK) == INTEL_TYPE_MOBILE; 193 } 194 195 bool SupportsHDMI() const 196 { 197 return InGroup(INTEL_GROUP_G4x) || InFamily(INTEL_FAMILY_SER5) 198 || InFamily(INTEL_FAMILY_SOC0); 199 } 200 201 bool HasDDI() const 202 { 203 // Intel Digital Display Interface 204 return InGroup(INTEL_GROUP_HAS) || (Generation() >= 8); 205 } 206 207 int Generation() const 208 { 209 if (InFamily(INTEL_FAMILY_8xx)) 210 return 2; 211 if (InGroup(INTEL_GROUP_91x) || InGroup(INTEL_GROUP_94x) 212 || IsModel(INTEL_MODEL_G33) || InGroup(INTEL_GROUP_PIN)) 213 return 3; 214 if (InFamily(INTEL_FAMILY_9xx)) 215 return 4; 216 if (InGroup(INTEL_GROUP_ILK)) 217 return 5; 218 if (InGroup(INTEL_GROUP_SNB)) 219 return 6; 220 if (InFamily(INTEL_FAMILY_SER5) || InGroup(INTEL_GROUP_VLV)) 221 return 7; 222 if (InGroup(INTEL_GROUP_CHV) || InGroup(INTEL_GROUP_BDW)) 223 return 8; 224 if (InFamily(INTEL_FAMILY_LAKE)) 225 return 9; 226 227 // Generation 0 means something is wrong :-) 228 return 0; 229 } 230 }; 231 232 enum port_index { 233 INTEL_PORT_ANY, // wildcard for lookup functions 234 INTEL_PORT_A, 235 INTEL_PORT_B, 236 INTEL_PORT_C, 237 INTEL_PORT_D, 238 INTEL_PORT_E, 239 INTEL_PORT_F 240 }; 241 242 enum pch_info { 243 INTEL_PCH_NONE = 0, // No PCH present 244 INTEL_PCH_IBX, // Ibexpeak 245 INTEL_PCH_CPT, // Cougarpoint 246 INTEL_PCH_LPT, // Lynxpoint 247 INTEL_PCH_SPT, // SunrisePoint 248 INTEL_PCH_CNP, // CannonLake 249 INTEL_PCH_ICP, // IceLake 250 INTEL_PCH_JSP, // JasperLake 251 INTEL_PCH_MCC, // Mule Creek Canyon 252 INTEL_PCH_TGP, // TigerLake 253 INTEL_PCH_ADP, // AlderLake 254 INTEL_PCH_NOP 255 }; 256 257 // info about PLL on graphics card 258 struct pll_info { 259 uint32 reference_frequency; 260 uint32 max_frequency; 261 uint32 min_frequency; 262 uint32 divisor_register; 263 }; 264 265 struct ring_buffer { 266 struct lock lock; 267 uint32 register_base; 268 uint32 offset; 269 uint32 size; 270 uint32 position; 271 uint32 space_left; 272 uint8* base; 273 }; 274 275 struct overlay_registers; 276 277 struct intel_shared_info { 278 area_id mode_list_area; // area containing display mode list 279 uint32 mode_count; 280 281 display_mode current_mode; // pretty much a hack until per-display modes 282 display_timing panel_timing; // Hardware timings of the LVDS panel, extracted from BIOS 283 uint32 bytes_per_row; 284 uint32 bits_per_pixel; 285 uint32 dpms_mode; 286 287 area_id registers_area; // area of memory mapped registers 288 uint32 register_blocks[REGISTER_BLOCK_COUNT]; 289 290 uint8* status_page; 291 phys_addr_t physical_status_page; 292 uint8* graphics_memory; 293 phys_addr_t physical_graphics_memory; 294 uint32 graphics_memory_size; 295 296 addr_t frame_buffer; 297 uint32 frame_buffer_offset; 298 299 uint32 fdi_link_frequency; // In Mhz 300 301 bool got_vbt; 302 bool single_head_locked; 303 304 struct lock accelerant_lock; 305 struct lock engine_lock; 306 307 ring_buffer primary_ring_buffer; 308 309 int32 overlay_channel_used; 310 bool overlay_active; 311 uintptr_t overlay_token; 312 phys_addr_t physical_overlay_registers; 313 uint32 overlay_offset; 314 315 bool hardware_cursor_enabled; 316 sem_id vblank_sem; 317 318 uint8* cursor_memory; 319 phys_addr_t physical_cursor_memory; 320 uint32 cursor_buffer_offset; 321 uint32 cursor_format; 322 bool cursor_visible; 323 uint16 cursor_hot_x; 324 uint16 cursor_hot_y; 325 326 DeviceType device_type; 327 char device_identifier[32]; 328 struct pll_info pll_info; 329 330 enum pch_info pch_info; 331 332 edid1_info vesa_edid_info; 333 bool has_vesa_edid_info; 334 }; 335 336 enum pipe_index { 337 INTEL_PIPE_ANY, 338 INTEL_PIPE_A, 339 INTEL_PIPE_B, 340 INTEL_PIPE_C, 341 INTEL_PIPE_D 342 }; 343 344 class pipes { 345 public: 346 pipes() : bitmask(0) {} 347 348 bool HasPipe(pipe_index pipe) 349 { 350 if (pipe == INTEL_PIPE_ANY) 351 return bitmask != 0; 352 353 return (bitmask & (1 << pipe)) != 0; 354 } 355 356 void SetPipe(pipe_index pipe) 357 { 358 if (pipe == INTEL_PIPE_ANY) { 359 bitmask = ~1; 360 // first bit corresponds to INTEL_PIPE_ANY but it's never used, 361 // so it should be 0 362 } 363 bitmask |= (1 << pipe); 364 } 365 366 void ClearPipe(pipe_index pipe) 367 { 368 if (pipe == INTEL_PIPE_ANY) 369 bitmask = 0; 370 371 bitmask &= ~(1 << pipe); 372 } 373 374 private: 375 uint8 bitmask; 376 }; 377 378 //----------------- ioctl() interface ---------------- 379 380 // magic code for ioctls 381 #define INTEL_PRIVATE_DATA_MAGIC 'itic' 382 383 // list ioctls 384 enum { 385 INTEL_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1, 386 387 INTEL_GET_DEVICE_NAME, 388 INTEL_ALLOCATE_GRAPHICS_MEMORY, 389 INTEL_FREE_GRAPHICS_MEMORY 390 }; 391 392 // retrieve the area_id of the kernel/accelerant shared info 393 struct intel_get_private_data { 394 uint32 magic; // magic number 395 area_id shared_info_area; 396 }; 397 398 // allocate graphics memory 399 struct intel_allocate_graphics_memory { 400 uint32 magic; 401 uint32 size; 402 uint32 alignment; 403 uint32 flags; 404 addr_t buffer_base; 405 }; 406 407 // free graphics memory 408 struct intel_free_graphics_memory { 409 uint32 magic; 410 addr_t buffer_base; 411 }; 412 413 //---------------------------------------------------------- 414 // Register definitions, taken from X driver 415 416 // PCI bridge memory management 417 #define INTEL_GRAPHICS_MEMORY_CONTROL 0x52 // i830+ 418 419 // GGC - (G)MCH Graphics Control Register 420 #define MEMORY_CONTROL_ENABLED 0x0004 421 #define MEMORY_MASK 0x0001 422 #define STOLEN_MEMORY_MASK 0x00f0 423 #define i965_GTT_MASK 0x000e 424 #define G33_GTT_MASK 0x0300 425 #define G4X_GTT_MASK 0x0f00 // GGMS (GSM Memory Size) mask 426 427 // models i830 and up 428 #define i830_LOCAL_MEMORY_ONLY 0x10 429 #define i830_STOLEN_512K 0x20 430 #define i830_STOLEN_1M 0x30 431 #define i830_STOLEN_8M 0x40 432 #define i830_FRAME_BUFFER_64M 0x01 433 #define i830_FRAME_BUFFER_128M 0x00 434 435 // models i855 and up 436 #define i855_STOLEN_MEMORY_1M 0x10 437 #define i855_STOLEN_MEMORY_4M 0x20 438 #define i855_STOLEN_MEMORY_8M 0x30 439 #define i855_STOLEN_MEMORY_16M 0x40 440 #define i855_STOLEN_MEMORY_32M 0x50 441 #define i855_STOLEN_MEMORY_48M 0x60 442 #define i855_STOLEN_MEMORY_64M 0x70 443 #define i855_STOLEN_MEMORY_128M 0x80 444 #define i855_STOLEN_MEMORY_256M 0x90 445 446 #define G4X_STOLEN_MEMORY_96MB 0xa0 // GMS - Graphics Mode Select 447 #define G4X_STOLEN_MEMORY_160MB 0xb0 448 #define G4X_STOLEN_MEMORY_224MB 0xc0 449 #define G4X_STOLEN_MEMORY_352MB 0xd0 450 451 // SandyBridge (SNB) 452 453 #define SNB_GRAPHICS_MEMORY_CONTROL 0x50 454 455 #define SNB_STOLEN_MEMORY_MASK 0xf8 456 #define SNB_STOLEN_MEMORY_32MB (1 << 3) 457 #define SNB_STOLEN_MEMORY_64MB (2 << 3) 458 #define SNB_STOLEN_MEMORY_96MB (3 << 3) 459 #define SNB_STOLEN_MEMORY_128MB (4 << 3) 460 #define SNB_STOLEN_MEMORY_160MB (5 << 3) 461 #define SNB_STOLEN_MEMORY_192MB (6 << 3) 462 #define SNB_STOLEN_MEMORY_224MB (7 << 3) 463 #define SNB_STOLEN_MEMORY_256MB (8 << 3) 464 #define SNB_STOLEN_MEMORY_288MB (9 << 3) 465 #define SNB_STOLEN_MEMORY_320MB (10 << 3) 466 #define SNB_STOLEN_MEMORY_352MB (11 << 3) 467 #define SNB_STOLEN_MEMORY_384MB (12 << 3) 468 #define SNB_STOLEN_MEMORY_416MB (13 << 3) 469 #define SNB_STOLEN_MEMORY_448MB (14 << 3) 470 #define SNB_STOLEN_MEMORY_480MB (15 << 3) 471 #define SNB_STOLEN_MEMORY_512MB (16 << 3) 472 473 #define SNB_GTT_SIZE_MASK (3 << 8) 474 #define SNB_GTT_SIZE_NONE (0 << 8) 475 #define SNB_GTT_SIZE_1MB (1 << 8) 476 #define SNB_GTT_SIZE_2MB (2 << 8) 477 478 // BDW+ (GGC_0_0_0_PCI) 479 480 #define BDW_GRAPHICS_MEMORY_CONTROL 0x50 481 482 #define BDW_STOLEN_MEMORY_MASK 0xff00 483 #define BDW_STOLEN_MEMORY_32MB (1 << 8) 484 #define BDW_STOLEN_MEMORY_64MB (2 << 8) 485 #define BDW_STOLEN_MEMORY_96MB (3 << 8) 486 #define BDW_STOLEN_MEMORY_128MB (4 << 8) 487 #define BDW_STOLEN_MEMORY_160MB (5 << 8) 488 #define BDW_STOLEN_MEMORY_192MB (6 << 8) 489 #define BDW_STOLEN_MEMORY_224MB (7 << 8) 490 #define BDW_STOLEN_MEMORY_256MB (8 << 8) 491 #define BDW_STOLEN_MEMORY_288MB (9 << 8) 492 #define BDW_STOLEN_MEMORY_320MB (10 << 8) 493 #define BDW_STOLEN_MEMORY_352MB (11 << 8) 494 #define BDW_STOLEN_MEMORY_384MB (12 << 8) 495 #define BDW_STOLEN_MEMORY_416MB (13 << 8) 496 #define BDW_STOLEN_MEMORY_448MB (14 << 8) 497 #define BDW_STOLEN_MEMORY_480MB (15 << 8) 498 #define BDW_STOLEN_MEMORY_512MB (16 << 8) 499 #define BDW_STOLEN_MEMORY_1024MB (32 << 8) 500 #define BDW_STOLEN_MEMORY_1536MB (48 << 8) 501 #define BDW_STOLEN_MEMORY_2016MB (63 << 8) 502 #define SKL_STOLEN_MEMORY_2048MB (64 << 8) 503 #define SKL_STOLEN_MEMORY_4MB (240 << 8) 504 #define SKL_STOLEN_MEMORY_8MB (241 << 8) 505 #define SKL_STOLEN_MEMORY_12MB (242 << 8) 506 #define SKL_STOLEN_MEMORY_16MB (243 << 8) 507 #define SKL_STOLEN_MEMORY_20MB (244 << 8) 508 #define SKL_STOLEN_MEMORY_24MB (245 << 8) 509 #define SKL_STOLEN_MEMORY_28MB (246 << 8) 510 #define SKL_STOLEN_MEMORY_32MB (247 << 8) 511 #define SKL_STOLEN_MEMORY_36MB (248 << 8) 512 #define SKL_STOLEN_MEMORY_40MB (249 << 8) 513 #define SKL_STOLEN_MEMORY_44MB (250 << 8) 514 #define SKL_STOLEN_MEMORY_48MB (251 << 8) 515 #define SKL_STOLEN_MEMORY_52MB (252 << 8) 516 #define SKL_STOLEN_MEMORY_56MB (253 << 8) 517 #define SKL_STOLEN_MEMORY_60MB (254 << 8) 518 519 520 #define BDW_GTT_SIZE_MASK (3 << 6) 521 #define BDW_GTT_SIZE_NONE (0 << 6) 522 #define BDW_GTT_SIZE_2MB (1 << 6) 523 #define BDW_GTT_SIZE_4MB (2 << 6) 524 #define BDW_GTT_SIZE_8MB (3 << 6) 525 526 // graphics page translation table 527 #define INTEL_PAGE_TABLE_CONTROL 0x02020 528 #define PAGE_TABLE_ENABLED 0x00000001 529 #define INTEL_PAGE_TABLE_ERROR 0x02024 530 #define INTEL_HARDWARE_STATUS_PAGE 0x02080 531 #define i915_GTT_BASE 0x1c 532 #define i830_GTT_BASE 0x10000 // (- 0x2ffff) 533 #define i830_GTT_SIZE 0x20000 534 #define i965_GTT_BASE 0x80000 // (- 0xfffff) 535 #define i965_GTT_SIZE 0x80000 536 #define i965_GTT_128K (2 << 1) 537 #define i965_GTT_256K (1 << 1) 538 #define i965_GTT_512K (0 << 1) 539 #define G33_GTT_1M (1 << 8) 540 #define G33_GTT_2M (2 << 8) 541 #define G4X_GTT_NONE 0x000 // GGMS - GSM Memory Size 542 #define G4X_GTT_1M_NO_IVT 0x100 // no Intel Virtualization Tech. 543 #define G4X_GTT_2M_NO_IVT 0x300 544 #define G4X_GTT_2M_IVT 0x900 // with Intel Virt. Tech. 545 #define G4X_GTT_3M_IVT 0xa00 546 #define G4X_GTT_4M_IVT 0xb00 547 548 549 #define GTT_ENTRY_VALID 0x01 550 #define GTT_ENTRY_LOCAL_MEMORY 0x02 551 #define GTT_PAGE_SHIFT 12 552 553 554 // ring buffer 555 #define INTEL_PRIMARY_RING_BUFFER 0x02030 556 #define INTEL_SECONDARY_RING_BUFFER_0 0x02100 557 #define INTEL_SECONDARY_RING_BUFFER_1 0x02110 558 // offsets for the ring buffer base registers above 559 #define RING_BUFFER_TAIL 0x0 560 #define RING_BUFFER_HEAD 0x4 561 #define RING_BUFFER_START 0x8 562 #define RING_BUFFER_CONTROL 0xc 563 #define INTEL_RING_BUFFER_SIZE_MASK 0x001ff000 564 #define INTEL_RING_BUFFER_HEAD_MASK 0x001ffffc 565 #define INTEL_RING_BUFFER_ENABLED 1 566 567 // interrupts 568 #define INTEL_INTERRUPT_ENABLED 0x020a0 569 #define INTEL_INTERRUPT_IDENTITY 0x020a4 570 #define INTEL_INTERRUPT_MASK 0x020a8 571 #define INTEL_INTERRUPT_STATUS 0x020ac 572 #define INTERRUPT_VBLANK_PIPEA (1 << 7) 573 #define INTERRUPT_VBLANK_PIPEB (1 << 5) 574 575 // PCH interrupts 576 #define PCH_INTERRUPT_STATUS 0x44000 577 #define PCH_INTERRUPT_MASK 0x44004 578 #define PCH_INTERRUPT_IDENTITY 0x44008 579 #define PCH_INTERRUPT_ENABLED 0x4400c 580 581 #define PCH_INTERRUPT_VBLANK_PIPEA (1 << 0) 582 #define PCH_INTERRUPT_VBLANK_PIPEB (1 << 5) 583 #define PCH_INTERRUPT_VBLANK_PIPEC (1 << 10) 584 585 // SandyBridge had only two pipes, and things were shuffled aroud again with 586 // the introduction of pipe C. 587 #define PCH_INTERRUPT_VBLANK_PIPEA_SNB (1 << 7) 588 #define PCH_INTERRUPT_VBLANK_PIPEB_SNB (1 << 15) 589 #define PCH_INTERRUPT_GLOBAL_SNB (1 << 31) 590 591 #define PCH_MASTER_INT_CTL_BDW 0x44200 592 593 #define PCH_MASTER_INT_CTL_PIPE_PENDING_BDW(pipe) (1 << (15 + pipe)) 594 #define PCH_MASTER_INT_CTL_GLOBAL_BDW (1 << 31) 595 596 #define PCH_INTERRUPT_PIPE_STATUS_BDW(pipe) (0x44400 + (pipe - 1) * 0x10) 597 #define PCH_INTERRUPT_PIPE_MASK_BDW(pipe) (0x44404 + (pipe - 1) * 0x10) 598 #define PCH_INTERRUPT_PIPE_IDENTITY_BDW(pipe) (0x44408 + (pipe - 1) * 0x10) 599 #define PCH_INTERRUPT_PIPE_ENABLED_BDW(pipe) (0x4440c + (pipe - 1) * 0x10) 600 601 #define PCH_INTERRUPT_VBLANK_BDW (1 << 0) 602 603 // graphics port control (i.e. G45) 604 #define DISPLAY_MONITOR_PORT_ENABLED (1UL << 31) 605 #define DISPLAY_MONITOR_PIPE_B (1UL << 30) 606 #define DISPLAY_MONITOR_VGA_POLARITY (1UL << 15) 607 #define DISPLAY_MONITOR_MODE_MASK (3UL << 10) 608 #define DISPLAY_MONITOR_ON 0 609 #define DISPLAY_MONITOR_SUSPEND (1UL << 10) 610 #define DISPLAY_MONITOR_STAND_BY (2UL << 10) 611 #define DISPLAY_MONITOR_OFF (3UL << 10) 612 #define DISPLAY_MONITOR_POLARITY_MASK (3UL << 3) 613 #define DISPLAY_MONITOR_POSITIVE_HSYNC (1UL << 3) 614 #define DISPLAY_MONITOR_POSITIVE_VSYNC (2UL << 3) 615 #define DISPLAY_MONITOR_PORT_DETECTED (1UL << 2) // TMDS/DisplayPort only 616 617 // Cougar Point transcoder pipe selection 618 // (replaces DISPLAY_MONITOR_PIPE_B) 619 #define PORT_TRANS_A_SEL_CPT 0 620 #define PORT_TRANS_B_SEL_CPT (1<<29) 621 #define PORT_TRANS_C_SEL_CPT (2<<29) 622 #define PORT_TRANS_SEL_MASK (3<<29) 623 624 #define LVDS_POST2_RATE_SLOW 14 // PLL Divisors 625 #define LVDS_POST2_RATE_FAST 7 626 #define LVDS_B0B3_POWER_MASK (3UL << 2) 627 #define LVDS_B0B3_POWER_UP (3UL << 2) 628 #define LVDS_CLKB_POWER_MASK (3UL << 4) 629 #define LVDS_CLKB_POWER_UP (3UL << 4) 630 #define LVDS_A3_POWER_MASK (3UL << 6) 631 #define LVDS_A3_POWER_UP (3UL << 6) 632 #define LVDS_A0A2_CLKA_POWER_UP (3UL << 8) 633 #define LVDS_BORDER_ENABLE (1UL << 15) 634 #define LVDS_HSYNC_POLARITY (1UL << 20) 635 #define LVDS_VSYNC_POLARITY (1UL << 21) 636 #define LVDS_18BIT_DITHER (1UL << 25) 637 #define LVDS_PORT_EN (1UL << 31) 638 639 // PLL flags (pre-DDI) 640 #define DISPLAY_PLL_ENABLED (1UL << 31) 641 #define DISPLAY_PLL_2X_CLOCK (1UL << 30) 642 #define DISPLAY_PLL_SYNC_LOCK_ENABLED (1UL << 29) 643 #define DISPLAY_PLL_NO_VGA_CONTROL (1UL << 28) 644 #define DISPLAY_PLL_MODE_NORMAL (1UL << 26) 645 #define DISPLAY_PLL_MODE_LVDS (2UL << 26) 646 #define DISPLAY_PLL_DIVIDE_HIGH (1UL << 24) 647 #define DISPLAY_PLL_DIVIDE_4X (1UL << 23) 648 #define DISPLAY_PLL_POST1_DIVIDE_2 (1UL << 21) 649 #define DISPLAY_PLL_POST1_DIVISOR_MASK 0x001f0000 650 #define DISPLAY_PLL_9xx_POST1_DIVISOR_MASK 0x00ff0000 651 #define DISPLAY_PLL_SNB_FP0_POST1_DIVISOR_MASK 0x000000ff 652 #define DISPLAY_PLL_IGD_POST1_DIVISOR_MASK 0x00ff8000 653 #define DISPLAY_PLL_POST1_DIVISOR_SHIFT 16 654 #define DISPLAY_PLL_SNB_FP0_POST1_DIVISOR_SHIFT 0 655 #define DISPLAY_PLL_IGD_POST1_DIVISOR_SHIFT 15 656 #define DISPLAY_PLL_DIVISOR_1 (1UL << 8) 657 #define DISPLAY_PLL_N_DIVISOR_MASK 0x001f0000 658 #define DISPLAY_PLL_IGD_N_DIVISOR_MASK 0x00ff0000 659 #define DISPLAY_PLL_M1_DIVISOR_MASK 0x00001f00 660 #define DISPLAY_PLL_M2_DIVISOR_MASK 0x0000001f 661 #define DISPLAY_PLL_IGD_M2_DIVISOR_MASK 0x000000ff 662 #define DISPLAY_PLL_N_DIVISOR_SHIFT 16 663 #define DISPLAY_PLL_M1_DIVISOR_SHIFT 8 664 #define DISPLAY_PLL_M2_DIVISOR_SHIFT 0 665 #define DISPLAY_PLL_PULSE_PHASE_SHIFT 9 666 667 // Skylake PLLs 668 #define SKL_DPLL1_CFGCR1 (0xc040 | REGS_NORTH_PIPE_AND_PORT) 669 #define SKL_DPLL1_CFGCR2 (0xc044 | REGS_NORTH_PIPE_AND_PORT) 670 #define SKL_DPLL2_CFGCR1 (0xc048 | REGS_NORTH_PIPE_AND_PORT) 671 #define SKL_DPLL2_CFGCR2 (0xc04c | REGS_NORTH_PIPE_AND_PORT) 672 #define SKL_DPLL3_CFGCR1 (0xc050 | REGS_NORTH_PIPE_AND_PORT) 673 #define SKL_DPLL3_CFGCR2 (0xc054 | REGS_NORTH_PIPE_AND_PORT) 674 // These exist also still in CoffeeLake (confirmed): 675 #define SKL_DPLL_CTRL1 (0xc058 | REGS_NORTH_PIPE_AND_PORT) 676 #define SKL_DPLL_CTRL2 (0xc05c | REGS_NORTH_PIPE_AND_PORT) 677 #define SKL_DPLL_STATUS (0xc060 | REGS_NORTH_PIPE_AND_PORT) 678 #define SKL_DPLL0_DP_LINKRATE_SHIFT 1 679 #define SKL_DPLL1_DP_LINKRATE_SHIFT 7 680 #define SKL_DPLL2_DP_LINKRATE_SHIFT 13 681 #define SKL_DPLL3_DP_LINKRATE_SHIFT 19 682 #define SKL_DPLL_DP_LINKRATE_MASK 7 683 #define SKL_DPLL_CTRL1_2700 0 684 #define SKL_DPLL_CTRL1_1350 1 685 #define SKL_DPLL_CTRL1_810 2 686 #define SKL_DPLL_CTRL1_1620 3 687 #define SKL_DPLL_CTRL1_1080 4 688 #define SKL_DPLL_CTRL1_2160 5 689 690 // Icelake PLLs 691 #define ICL_DSSM 0x51004 692 #define ICL_DSSM_REF_FREQ_SHIFT 29 693 #define ICL_DSSM_REF_FREQ_MASK (7 << ICL_DSSM_REF_FREQ_SHIFT) 694 #define ICL_DSSM_24000 0 695 #define ICL_DSSM_19200 1 696 #define ICL_DSSM_38400 2 697 698 // display 699 700 #define INTEL_DISPLAY_OFFSET 0x1000 701 702 // Note: on Skylake below registers are part of the transcoder 703 #define INTEL_DISPLAY_A_HTOTAL (0x0000 | REGS_NORTH_PIPE_AND_PORT) 704 #define INTEL_DISPLAY_A_HBLANK (0x0004 | REGS_NORTH_PIPE_AND_PORT) 705 #define INTEL_DISPLAY_A_HSYNC (0x0008 | REGS_NORTH_PIPE_AND_PORT) 706 #define INTEL_DISPLAY_A_VTOTAL (0x000c | REGS_NORTH_PIPE_AND_PORT) 707 #define INTEL_DISPLAY_A_VBLANK (0x0010 | REGS_NORTH_PIPE_AND_PORT) 708 #define INTEL_DISPLAY_A_VSYNC (0x0014 | REGS_NORTH_PIPE_AND_PORT) 709 #define INTEL_DISPLAY_B_HTOTAL (0x1000 | REGS_NORTH_PIPE_AND_PORT) 710 #define INTEL_DISPLAY_B_HBLANK (0x1004 | REGS_NORTH_PIPE_AND_PORT) 711 #define INTEL_DISPLAY_B_HSYNC (0x1008 | REGS_NORTH_PIPE_AND_PORT) 712 #define INTEL_DISPLAY_B_VTOTAL (0x100c | REGS_NORTH_PIPE_AND_PORT) 713 #define INTEL_DISPLAY_B_VBLANK (0x1010 | REGS_NORTH_PIPE_AND_PORT) 714 #define INTEL_DISPLAY_B_VSYNC (0x1014 | REGS_NORTH_PIPE_AND_PORT) 715 716 #define INTEL_DISPLAY_A_PIPE_SIZE (0x001c | REGS_NORTH_PIPE_AND_PORT) 717 #define INTEL_DISPLAY_B_PIPE_SIZE (0x101c | REGS_NORTH_PIPE_AND_PORT) 718 719 //G45 displayport link 720 #define INTEL_PIPE_A_DATA_M (0x0050 | REGS_NORTH_PLANE_CONTROL) 721 #define INTEL_PIPE_B_DATA_M (0x1050 | REGS_NORTH_PLANE_CONTROL) 722 #define INTEL_PIPE_A_DATA_N (0x0054 | REGS_NORTH_PLANE_CONTROL) 723 #define INTEL_PIPE_B_DATA_N (0x1054 | REGS_NORTH_PLANE_CONTROL) 724 #define INTEL_PIPE_A_LINK_M (0x0060 | REGS_NORTH_PLANE_CONTROL) 725 #define INTEL_PIPE_B_LINK_M (0x1060 | REGS_NORTH_PLANE_CONTROL) 726 #define INTEL_PIPE_A_LINK_N (0x0064 | REGS_NORTH_PLANE_CONTROL) 727 #define INTEL_PIPE_B_LINK_N (0x1064 | REGS_NORTH_PLANE_CONTROL) 728 729 //DDI port link 730 #define INTEL_DDI_PIPE_A_DATA_M (0x0030 | REGS_NORTH_PIPE_AND_PORT) 731 #define INTEL_DDI_PIPE_B_DATA_M (0x1030 | REGS_NORTH_PIPE_AND_PORT) 732 #define INTEL_DDI_PIPE_A_DATA_N (0x0034 | REGS_NORTH_PIPE_AND_PORT) 733 #define INTEL_DDI_PIPE_B_DATA_N (0x1034 | REGS_NORTH_PIPE_AND_PORT) 734 #define INTEL_DDI_PIPE_A_LINK_M (0x0040 | REGS_NORTH_PIPE_AND_PORT) 735 #define INTEL_DDI_PIPE_B_LINK_M (0x1040 | REGS_NORTH_PIPE_AND_PORT) 736 #define INTEL_DDI_PIPE_A_LINK_N (0x0044 | REGS_NORTH_PIPE_AND_PORT) 737 #define INTEL_DDI_PIPE_B_LINK_N (0x1044 | REGS_NORTH_PIPE_AND_PORT) 738 739 // on PCH we also have to set the transcoder 740 #define INTEL_TRANSCODER_A_HTOTAL (0x0000 | REGS_SOUTH_TRANSCODER_PORT) 741 #define INTEL_TRANSCODER_A_HBLANK (0x0004 | REGS_SOUTH_TRANSCODER_PORT) 742 #define INTEL_TRANSCODER_A_HSYNC (0x0008 | REGS_SOUTH_TRANSCODER_PORT) 743 #define INTEL_TRANSCODER_A_VTOTAL (0x000c | REGS_SOUTH_TRANSCODER_PORT) 744 #define INTEL_TRANSCODER_A_VBLANK (0x0010 | REGS_SOUTH_TRANSCODER_PORT) 745 #define INTEL_TRANSCODER_A_VSYNC (0x0014 | REGS_SOUTH_TRANSCODER_PORT) 746 #define INTEL_TRANSCODER_B_HTOTAL (0x1000 | REGS_SOUTH_TRANSCODER_PORT) 747 #define INTEL_TRANSCODER_B_HBLANK (0x1004 | REGS_SOUTH_TRANSCODER_PORT) 748 #define INTEL_TRANSCODER_B_HSYNC (0x1008 | REGS_SOUTH_TRANSCODER_PORT) 749 #define INTEL_TRANSCODER_B_VTOTAL (0x100c | REGS_SOUTH_TRANSCODER_PORT) 750 #define INTEL_TRANSCODER_B_VBLANK (0x1010 | REGS_SOUTH_TRANSCODER_PORT) 751 #define INTEL_TRANSCODER_B_VSYNC (0x1014 | REGS_SOUTH_TRANSCODER_PORT) 752 753 // transcoder M/N DATA AND LINK VALUES (refreshrate) 754 #define INTEL_TRANSCODER_A_DATA_M1 (0x0030 | REGS_SOUTH_TRANSCODER_PORT) 755 #define INTEL_TRANSCODER_A_DATA_M2 (0x0038 | REGS_SOUTH_TRANSCODER_PORT) 756 #define INTEL_TRANSCODER_B_DATA_M1 (0x1030 | REGS_SOUTH_TRANSCODER_PORT) 757 #define INTEL_TRANSCODER_B_DATA_M2 (0x1038 | REGS_SOUTH_TRANSCODER_PORT) 758 #define INTEL_TRANSCODER_C_DATA_M1 (0x2030 | REGS_SOUTH_TRANSCODER_PORT) 759 #define INTEL_TRANSCODER_C_DATA_M2 (0x2038 | REGS_SOUTH_TRANSCODER_PORT) 760 #define INTEL_TRANSCODER_A_DATA_N1 (0x0034 | REGS_SOUTH_TRANSCODER_PORT) 761 #define INTEL_TRANSCODER_A_DATA_N2 (0x003c | REGS_SOUTH_TRANSCODER_PORT) 762 #define INTEL_TRANSCODER_B_DATA_N1 (0x1034 | REGS_SOUTH_TRANSCODER_PORT) 763 #define INTEL_TRANSCODER_B_DATA_N2 (0x103c | REGS_SOUTH_TRANSCODER_PORT) 764 #define INTEL_TRANSCODER_C_DATA_N1 (0x2034 | REGS_SOUTH_TRANSCODER_PORT) 765 #define INTEL_TRANSCODER_C_DATA_N2 (0x203c | REGS_SOUTH_TRANSCODER_PORT) 766 #define INTEL_TRANSCODER_A_LINK_M1 (0x0040 | REGS_SOUTH_TRANSCODER_PORT) 767 #define INTEL_TRANSCODER_A_LINK_M2 (0x0048 | REGS_SOUTH_TRANSCODER_PORT) 768 #define INTEL_TRANSCODER_B_LINK_M1 (0x1040 | REGS_SOUTH_TRANSCODER_PORT) 769 #define INTEL_TRANSCODER_B_LINK_M2 (0x1048 | REGS_SOUTH_TRANSCODER_PORT) 770 #define INTEL_TRANSCODER_C_LINK_M1 (0x2040 | REGS_SOUTH_TRANSCODER_PORT) 771 #define INTEL_TRANSCODER_C_LINK_M2 (0x2048 | REGS_SOUTH_TRANSCODER_PORT) 772 #define INTEL_TRANSCODER_A_LINK_N1 (0x0044 | REGS_SOUTH_TRANSCODER_PORT) 773 #define INTEL_TRANSCODER_A_LINK_N2 (0x004c | REGS_SOUTH_TRANSCODER_PORT) 774 #define INTEL_TRANSCODER_B_LINK_N1 (0x1044 | REGS_SOUTH_TRANSCODER_PORT) 775 #define INTEL_TRANSCODER_B_LINK_N2 (0x104c | REGS_SOUTH_TRANSCODER_PORT) 776 #define INTEL_TRANSCODER_C_LINK_N1 (0x2044 | REGS_SOUTH_TRANSCODER_PORT) 777 #define INTEL_TRANSCODER_C_LINK_N2 (0x204c | REGS_SOUTH_TRANSCODER_PORT) 778 #define INTEL_TRANSCODER_MN_TU_SIZE_MASK (0x3f << 25) 779 #define INTEL_TRANSCODER_MN_VALUE_MASK (0xffffff << 0) 780 781 #define INTEL_TRANSCODER_A_IMAGE_SIZE (0x001c | REGS_SOUTH_TRANSCODER_PORT) 782 #define INTEL_TRANSCODER_B_IMAGE_SIZE (0x101c | REGS_SOUTH_TRANSCODER_PORT) 783 784 // TODO: Is there consolidation that could happen here with digital ports? 785 786 #define INTEL_ANALOG_PORT (0x1100 | REGS_SOUTH_TRANSCODER_PORT) 787 #define INTEL_DIGITAL_PORT_A (0x1120 | REGS_SOUTH_TRANSCODER_PORT) 788 #define INTEL_DIGITAL_PORT_B (0x1140 | REGS_SOUTH_TRANSCODER_PORT) 789 #define INTEL_DIGITAL_PORT_C (0x1160 | REGS_SOUTH_TRANSCODER_PORT) 790 #define INTEL_DIGITAL_LVDS_PORT (0x1180 | REGS_SOUTH_TRANSCODER_PORT) 791 792 #define INTEL_HDMI_PORT_B (0x1140 | REGS_SOUTH_TRANSCODER_PORT) 793 #define INTEL_HDMI_PORT_C (0x1160 | REGS_SOUTH_TRANSCODER_PORT) 794 795 #define PCH_HDMI_PORT_B (0x1140 | REGS_SOUTH_TRANSCODER_PORT) 796 #define PCH_HDMI_PORT_C (0x1150 | REGS_SOUTH_TRANSCODER_PORT) 797 #define PCH_HDMI_PORT_D (0x1160 | REGS_SOUTH_TRANSCODER_PORT) 798 799 #define GEN4_HDMI_PORT_B (0x1140 | REGS_SOUTH_TRANSCODER_PORT) 800 #define GEN4_HDMI_PORT_C (0x1160 | REGS_SOUTH_TRANSCODER_PORT) 801 #define CHV_HDMI_PORT_D (0x116C | REGS_SOUTH_TRANSCODER_PORT) 802 803 // DDI Buffer Control (This replaces DP on Haswell+) 804 #define DDI_BUF_CTL_A (0x4000 | REGS_NORTH_PIPE_AND_PORT) 805 #define DDI_BUF_CTL_B (0x4100 | REGS_NORTH_PIPE_AND_PORT) 806 #define DDI_BUF_CTL_C (0x4200 | REGS_NORTH_PIPE_AND_PORT) 807 #define DDI_BUF_CTL_D (0x4300 | REGS_NORTH_PIPE_AND_PORT) 808 #define DDI_BUF_CTL_E (0x4400 | REGS_NORTH_PIPE_AND_PORT) 809 #define DDI_BUF_CTL_F (0x4500 | REGS_NORTH_PIPE_AND_PORT) 810 #define DDI_BUF_CTL_ENABLE (1 << 31) 811 #define DDI_BUF_TRANS_SELECT(n) ((n) << 24) 812 #define DDI_BUF_EMP_MASK (0xf << 24) 813 #define DDI_BUF_PORT_REVERSAL (1 << 16) 814 #define DDI_BUF_IS_IDLE (1 << 7) 815 #define DDI_A_4_LANES (1 << 4) 816 #define DDI_PORT_WIDTH(width) (((width) - 1) << 1) 817 #define DDI_INIT_DISPLAY_DETECTED (1 << 0) 818 819 #define PIPE_DDI_FUNC_CTL_A (0x0400 | REGS_NORTH_PIPE_AND_PORT) 820 #define PIPE_DDI_FUNC_CTL_B (0x1400 | REGS_NORTH_PIPE_AND_PORT) 821 #define PIPE_DDI_FUNC_CTL_C (0x2400 | REGS_NORTH_PIPE_AND_PORT) 822 #define PIPE_DDI_FUNC_CTL_EDP (0xF400 | REGS_NORTH_PIPE_AND_PORT) 823 #define PIPE_DDI_FUNC_CTL_ENABLE (1 << 31) 824 #define PIPE_DDI_SELECT_SHIFT 28 825 #define PIPE_DDI_SELECT_PORT(x) ((x) << PIPE_DDI_SELECT_SHIFT) 826 #define PIPE_DDI_SELECT_MASK (7 << PIPE_DDI_SELECT_SHIFT) 827 #define PIPE_DDI_PORT_NONE 0 828 #define PIPE_DDI_PORT_B 1 829 #define PIPE_DDI_PORT_C 2 830 #define PIPE_DDI_PORT_D 3 831 #define PIPE_DDI_PORT_E 4 832 #define PIPE_DDI_PORT_F 5 833 #define PIPE_DDI_MODESEL_SHIFT 24 834 #define PIPE_DDI_MODESEL_MODE(x) ((x) << PIPE_DDI_MODESEL_SHIFT) 835 #define PIPE_DDI_MODESEL_MASK (7 << PIPE_DDI_MODESEL_SHIFT) 836 #define PIPE_DDI_MODE_HDMI 0 837 #define PIPE_DDI_MODE_DVI 1 838 #define PIPE_DDI_MODE_DP_SST 2 839 #define PIPE_DDI_MODE_DP_MST 3 840 #define PIPE_DDI_COLOR_SHIFT 20 841 #define PIPE_DDI_BPC(x) ((x) << PIPE_DDI_COLOR_SHIFT) 842 #define PIPE_DDI_BPC_MASK (7 << PIPE_DDI_COLOR_SHIFT) 843 #define PIPE_DDI_8BPC 0 844 #define PIPE_DDI_10BPC 1 845 #define PIPE_DDI_6BPC 2 846 #define PIPE_DDI_12BPC 3 847 #define PIPE_DDI_DP_WIDTH_SHIFT 1 848 #define PIPE_DDI_DP_WIDTH_SEL(x) ((x) << PIPE_DDI_DP_WIDTH_SHIFT) 849 #define PIPE_DDI_DP_WIDTH_MASK (7 << PIPE_DDI_DP_WIDTH_SHIFT) 850 #define PIPE_DDI_DP_WIDTH_1 0 851 #define PIPE_DDI_DP_WIDTH_2 1 852 #define PIPE_DDI_DP_WIDTH_4 2 853 854 // DP_A always @ 6xxxx, DP_B-DP_D move with PCH 855 #define INTEL_DISPLAY_PORT_A (0x4000 | REGS_NORTH_PIPE_AND_PORT) 856 #define INTEL_DISPLAY_PORT_B (0x4100 | REGS_SOUTH_TRANSCODER_PORT) 857 #define INTEL_DISPLAY_PORT_C (0x4200 | REGS_SOUTH_TRANSCODER_PORT) 858 #define INTEL_DISPLAY_PORT_D (0x4300 | REGS_SOUTH_TRANSCODER_PORT) 859 860 #define INTEL_DISP_PORTA_SNB_PIPE_SHIFT 30 861 #define INTEL_DISP_PORTA_SNB_PIPE_MASK (1 << INTEL_DISP_PORTA_SNB_PIPE_SHIFT) 862 #define INTEL_DISP_PORTA_SNB_PIPE_A 0 863 #define INTEL_DISP_PORTA_SNB_PIPE_B 1 864 #define INTEL_DISP_PORTA_IVB_PIPE_SHIFT 29 865 #define INTEL_DISP_PORTA_IVB_PIPE_MASK (3 << INTEL_DISP_PORTA_IVB_PIPE_SHIFT) 866 #define INTEL_DISP_PORTA_IVB_PIPE_A 0 867 #define INTEL_DISP_PORTA_IVB_PIPE_B 1 868 #define INTEL_DISP_PORTA_IVB_PIPE_C 2 869 870 #define INTEL_DISP_PORT_WIDTH_SHIFT 19 871 #define INTEL_DISP_PORT_WIDTH_MASK (7 << INTEL_DISP_PORT_WIDTH_SHIFT) 872 #define INTEL_DISP_PORT_WIDTH_1 0 873 #define INTEL_DISP_PORT_WIDTH_2 1 874 #define INTEL_DISP_PORT_WIDTH_4 3 875 #define INTEL_DISP_EDP_PLL_FREQ_SHIFT 16 876 #define INTEL_DISP_EDP_PLL_FREQ_MASK (3 << INTEL_DISP_EDP_PLL_FREQ_SHIFT) 877 #define INTEL_DISP_EDP_PLL_FREQ_270 0 878 #define INTEL_DISP_EDP_PLL_FREQ_162 1 879 880 #define INTEL_TRANSCODER_A_DP_CTL (0x0300 | REGS_SOUTH_TRANSCODER_PORT) 881 #define INTEL_TRANSCODER_B_DP_CTL (0x1300 | REGS_SOUTH_TRANSCODER_PORT) 882 #define INTEL_TRANSCODER_C_DP_CTL (0x2300 | REGS_SOUTH_TRANSCODER_PORT) 883 884 #define INTEL_TRANS_DP_COLOR_SHIFT 9 885 #define INTEL_TRANS_DP_BPC(x) ((x) << INTEL_TRANS_DP_COLOR_SHIFT) 886 #define INTEL_TRANS_DP_BPC_MASK (7 << INTEL_TRANS_DP_COLOR_SHIFT) 887 #define INTEL_TRANS_DP_PORT_SHIFT 29 888 #define INTEL_TRANS_DP_PORT(x) ((x) << INTEL_TRANS_DP_PORT_SHIFT) 889 #define INTEL_TRANS_DP_PORT_MASK (3 << INTEL_TRANS_DP_PORT_SHIFT) 890 #define INTEL_TRANS_DP_PORT_B 0 891 #define INTEL_TRANS_DP_PORT_C 1 892 #define INTEL_TRANS_DP_PORT_D 2 893 #define INTEL_TRANS_DP_PORT_NONE 3 894 895 // Unless you're a damn Valley/CherryView unicorn :-( 896 #define VLV_DISPLAY_PORT_B (VLV_DISPLAY_BASE + 0x64100) 897 #define VLV_DISPLAY_PORT_C (VLV_DISPLAY_BASE + 0x64200) 898 #define CHV_DISPLAY_PORT_D (VLV_DISPLAY_BASE + 0x64300) 899 900 // DP AUX channels 901 #define INTEL_DP_AUX_CTL_A (0x4010 | REGS_NORTH_PIPE_AND_PORT) 902 #define INTEL_DP_AUX_CTL_B (0x4110 | REGS_SOUTH_TRANSCODER_PORT) 903 #define INTEL_DP_AUX_CTL_C (0x4210 | REGS_SOUTH_TRANSCODER_PORT) 904 #define INTEL_DP_AUX_CTL_D (0x4310 | REGS_SOUTH_TRANSCODER_PORT) 905 906 #define VLV_DP_AUX_CTL_B (VLV_DISPLAY_BASE + 0x64110) 907 #define VLV_DP_AUX_CTL_C (VLV_DISPLAY_BASE + 0x64210) 908 #define CHV_DP_AUX_CTL_D (VLV_DISPLAY_BASE + 0x64310) 909 910 #define INTEL_DP_AUX_CTL_BUSY (1 << 31) 911 #define INTEL_DP_AUX_CTL_DONE (1 << 30) 912 #define INTEL_DP_AUX_CTL_INTERRUPT (1 << 29) 913 #define INTEL_DP_AUX_CTL_TIMEOUT_ERROR (1 << 28) 914 #define INTEL_DP_AUX_CTL_TIMEOUT_400us (0 << 26) 915 #define INTEL_DP_AUX_CTL_TIMEOUT_600us (1 << 26) 916 #define INTEL_DP_AUX_CTL_TIMEOUT_800us (2 << 26) 917 #define INTEL_DP_AUX_CTL_TIMEOUT_1600us (3 << 26) 918 #define INTEL_DP_AUX_CTL_TIMEOUT_MASK (3 << 26) 919 #define INTEL_DP_AUX_CTL_RECEIVE_ERROR (1 << 25) 920 #define INTEL_DP_AUX_CTL_MSG_SIZE_MASK (0x1f << 20) 921 #define INTEL_DP_AUX_CTL_MSG_SIZE_SHIFT 20 922 #define INTEL_DP_AUX_CTL_PRECHARGE_2US_MASK (0xf << 16) 923 #define INTEL_DP_AUX_CTL_PRECHARGE_2US_SHIFT 16 924 #define INTEL_DP_AUX_CTL_BIT_CLOCK_2X_MASK (0x7ff) 925 #define INTEL_DP_AUX_CTL_BIT_CLOCK_2X_SHIFT 0 926 #define INTEL_DP_AUX_CTL_SYNC_PULSE_SKL(c) ((c) - 1) 927 928 // planes 929 #define INTEL_PIPE_ENABLED (1UL << 31) 930 #define INTEL_PIPE_STATE (1UL << 30) 931 932 #define INTEL_PLANE_OFFSET 0x1000 933 934 #define INTEL_DISPLAY_A_PIPE_CONTROL (0x0008 | REGS_NORTH_PLANE_CONTROL) 935 #define INTEL_DISPLAY_B_PIPE_CONTROL (0x1008 | REGS_NORTH_PLANE_CONTROL) 936 #define INTEL_DISPLAY_C_PIPE_CONTROL (0x2008 | REGS_NORTH_PLANE_CONTROL) 937 #define INTEL_DISPLAY_A_PIPE_STATUS (0x0024 | REGS_NORTH_PLANE_CONTROL) 938 #define INTEL_DISPLAY_B_PIPE_STATUS (0x1024 | REGS_NORTH_PLANE_CONTROL) 939 940 #define INTEL_DISPLAY_A_PIPE_WATERMARK (0x5100 | REGS_NORTH_PLANE_CONTROL) 941 #define INTEL_DISPLAY_B_PIPE_WATERMARK (0x5104 | REGS_NORTH_PLANE_CONTROL) 942 #define INTEL_DISPLAY_C_PIPE_WATERMARK (0x5200 | REGS_NORTH_PLANE_CONTROL) 943 944 #define DISPLAY_PIPE_VBLANK_ENABLED (1UL << 17) 945 #define DISPLAY_PIPE_VBLANK_STATUS (1UL << 1) 946 947 #define INTEL_DISPLAY_A_CONTROL (0x0180 | REGS_NORTH_PLANE_CONTROL) 948 #define INTEL_DISPLAY_A_BASE (0x0184 | REGS_NORTH_PLANE_CONTROL) 949 #define INTEL_DISPLAY_A_BYTES_PER_ROW (0x0188 | REGS_NORTH_PLANE_CONTROL) 950 #define INTEL_DISPLAY_A_POS (0x018c | REGS_NORTH_PLANE_CONTROL) 951 // reserved on A 952 #define INTEL_DISPLAY_A_IMAGE_SIZE (0x0190 | REGS_NORTH_PLANE_CONTROL) 953 #define INTEL_DISPLAY_A_SURFACE (0x019c | REGS_NORTH_PLANE_CONTROL) 954 #define INTEL_DISPLAY_A_OFFSET_HAS (0x01a4 | REGS_NORTH_PLANE_CONTROL) 955 // i965 and up only 956 957 #define INTEL_DISPLAY_B_CONTROL (0x1180 | REGS_NORTH_PLANE_CONTROL) 958 #define INTEL_DISPLAY_B_BASE (0x1184 | REGS_NORTH_PLANE_CONTROL) 959 #define INTEL_DISPLAY_B_BYTES_PER_ROW (0x1188 | REGS_NORTH_PLANE_CONTROL) 960 #define INTEL_DISPLAY_B_POS (0x118c | REGS_NORTH_PLANE_CONTROL) 961 #define INTEL_DISPLAY_B_IMAGE_SIZE (0x1190 | REGS_NORTH_PLANE_CONTROL) 962 #define INTEL_DISPLAY_B_SURFACE (0x119c | REGS_NORTH_PLANE_CONTROL) 963 #define INTEL_DISPLAY_B_OFFSET_HAS (0x11a4 | REGS_NORTH_PLANE_CONTROL) 964 // i965 and up only 965 966 // INTEL_DISPLAY_A_CONTROL source pixel format 967 #define DISPLAY_CONTROL_ENABLED (1UL << 31) 968 #define DISPLAY_CONTROL_GAMMA (1UL << 30) 969 #define DISPLAY_CONTROL_COLOR_MASK (0x0fUL << 26) 970 #define DISPLAY_CONTROL_CMAP8 (2UL << 26) 971 #define DISPLAY_CONTROL_RGB15 (4UL << 26) 972 #define DISPLAY_CONTROL_RGB16 (5UL << 26) 973 #define DISPLAY_CONTROL_RGB32 (6UL << 26) 974 #define DISPLAY_CONTROL_RGB64 (0x0cUL << 26) 975 // Skylake 976 #define DISPLAY_CONTROL_COLOR_MASK_SKY (0x0fUL << 24) 977 #define DISPLAY_CONTROL_CMAP8_SKY (0x0cUL << 24) 978 #define DISPLAY_CONTROL_RGB15_SKY (0x0eUL << 24) 979 #define DISPLAY_CONTROL_RGB16_SKY (0x0eUL << 24) 980 #define DISPLAY_CONTROL_RGB32_SKY (0x04UL << 24) 981 #define DISPLAY_CONTROL_RGB64_SKY (0x06UL << 24) 982 983 // INTEL_DISPLAY_A_PIPE_CONTROL ILK+ 984 #define INTEL_PIPE_DITHER_TYPE_MASK (0x0000000c) 985 #define INTEL_PIPE_DITHER_TYPE_SP (0 << 2) 986 #define INTEL_PIPE_DITHER_TYPE_ST1 (1 << 2) 987 #define INTEL_PIPE_DITHER_TYPE_ST2 (2 << 2) 988 #define INTEL_PIPE_DITHER_TYPE_TEMP (3 << 2) 989 #define INTEL_PIPE_DITHER_EN (1 << 4) 990 #define INTEL_PIPE_COLOR_SHIFT 5 991 #define INTEL_PIPE_BPC(x) ((x) << INTEL_PIPE_COLOR_SHIFT) 992 #define INTEL_PIPE_BPC_MASK (7 << INTEL_PIPE_COLOR_SHIFT) 993 #define INTEL_PIPE_8BPC 0 994 #define INTEL_PIPE_10BPC 1 995 #define INTEL_PIPE_6BPC 2 996 #define INTEL_PIPE_12BPC 3 997 #define INTEL_PIPE_PROGRESSIVE (0 << 21) 998 999 // cursors 1000 #define INTEL_CURSOR_CONTROL (0x0080 | REGS_NORTH_PLANE_CONTROL) 1001 #define INTEL_CURSOR_BASE (0x0084 | REGS_NORTH_PLANE_CONTROL) 1002 #define INTEL_CURSOR_POSITION (0x0088 | REGS_NORTH_PLANE_CONTROL) 1003 #define INTEL_CURSOR_PALETTE (0x0090 | REGS_NORTH_PLANE_CONTROL) 1004 // (- 0x009f) 1005 #define INTEL_CURSOR_SIZE (0x00a0 | REGS_NORTH_PLANE_CONTROL) 1006 #define CURSOR_ENABLED (1UL << 31) 1007 #define CURSOR_FORMAT_2_COLORS (0UL << 24) 1008 #define CURSOR_FORMAT_3_COLORS (1UL << 24) 1009 #define CURSOR_FORMAT_4_COLORS (2UL << 24) 1010 #define CURSOR_FORMAT_ARGB (4UL << 24) 1011 #define CURSOR_FORMAT_XRGB (5UL << 24) 1012 #define CURSOR_POSITION_NEGATIVE 0x8000 1013 #define CURSOR_POSITION_MASK 0x3fff 1014 1015 // palette registers 1016 #define INTEL_DISPLAY_A_PALETTE (0xa000 | REGS_NORTH_SHARED) 1017 #define INTEL_DISPLAY_B_PALETTE (0xa800 | REGS_NORTH_SHARED) 1018 1019 // Ironlake PCH reference clk control 1020 #define PCH_DREF_CONTROL (0x6200 | REGS_SOUTH_SHARED) 1021 #define DREF_CONTROL_MASK 0x7fc3 1022 #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0 << 13) 1023 #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2 << 13) 1024 #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3 << 13) 1025 #define DREF_CPU_SOURCE_OUTPUT_MASK (3 << 13) 1026 #define DREF_SSC_SOURCE_DISABLE (0 << 11) 1027 #define DREF_SSC_SOURCE_ENABLE (2 << 11) 1028 #define DREF_SSC_SOURCE_MASK (3 << 11) 1029 #define DREF_NONSPREAD_SOURCE_DISABLE (0 << 9) 1030 #define DREF_NONSPREAD_CK505_ENABLE (1 << 9) 1031 #define DREF_NONSPREAD_SOURCE_ENABLE (2 << 9) 1032 #define DREF_NONSPREAD_SOURCE_MASK (3 << 9) 1033 #define DREF_SUPERSPREAD_SOURCE_DISABLE (0 << 7) 1034 #define DREF_SUPERSPREAD_SOURCE_ENABLE (2 << 7) 1035 #define DREF_SUPERSPREAD_SOURCE_MASK (3 << 7) 1036 #define DREF_SSC4_DOWNSPREAD (0 << 6) 1037 #define DREF_SSC4_CENTERSPREAD (1 << 6) 1038 #define DREF_SSC1_DISABLE (0 << 1) 1039 #define DREF_SSC1_ENABLE (1 << 1) 1040 #define DREF_SSC4_DISABLE (0 << 0) 1041 #define DREF_SSC4_ENABLE (1 << 0) 1042 1043 // PLL registers 1044 // Multiplier Divisor 1045 #define INTEL_DISPLAY_A_PLL (0x6014 | REGS_SOUTH_SHARED) 1046 #define INTEL_DISPLAY_B_PLL (0x6018 | REGS_SOUTH_SHARED) 1047 #define INTEL_DISPLAY_A_PLL_MD (0x601C | REGS_SOUTH_SHARED) 1048 #define INTEL_DISPLAY_B_PLL_MD (0x6020 | REGS_SOUTH_SHARED) 1049 #define CHV_DISPLAY_C_PLL (0x6030 | REGS_SOUTH_SHARED) 1050 #define CHV_DISPLAY_B_PLL_MD (0x603C | REGS_SOUTH_SHARED) 1051 1052 #define INTEL_DISPLAY_A_PLL_DIVISOR_0 (0x6040 | REGS_SOUTH_SHARED) 1053 #define INTEL_DISPLAY_A_PLL_DIVISOR_1 (0x6044 | REGS_SOUTH_SHARED) 1054 #define INTEL_DISPLAY_B_PLL_DIVISOR_0 (0x6048 | REGS_SOUTH_SHARED) 1055 #define INTEL_DISPLAY_B_PLL_DIVISOR_1 (0x604c | REGS_SOUTH_SHARED) 1056 1057 #define SNB_DPLL_SEL (0x7000 | REGS_SOUTH_SHARED) 1058 1059 // i2c bit banging interface 1060 #define INTEL_I2C_IO_A (0x5010 | REGS_SOUTH_SHARED) 1061 #define INTEL_I2C_IO_B (0x5014 | REGS_SOUTH_SHARED) 1062 #define INTEL_I2C_IO_C (0x5018 | REGS_SOUTH_SHARED) 1063 #define INTEL_I2C_IO_D (0x501c | REGS_SOUTH_SHARED) 1064 #define INTEL_I2C_IO_E (0x5020 | REGS_SOUTH_SHARED) 1065 #define INTEL_I2C_IO_F (0x5024 | REGS_SOUTH_SHARED) 1066 #define INTEL_I2C_IO_G (0x5028 | REGS_SOUTH_SHARED) 1067 #define INTEL_I2C_IO_H (0x502c | REGS_SOUTH_SHARED) 1068 // i2c hardware controller 1069 #define INTEL_GMBUS0 (0x5100 | REGS_SOUTH_SHARED) 1070 #define INTEL_GMBUS4 (0x5110 | REGS_SOUTH_SHARED) 1071 1072 #define I2C_CLOCK_DIRECTION_MASK (1 << 0) 1073 #define I2C_CLOCK_DIRECTION_OUT (1 << 1) 1074 #define I2C_CLOCK_VALUE_MASK (1 << 2) 1075 #define I2C_CLOCK_VALUE_OUT (1 << 3) 1076 #define I2C_CLOCK_VALUE_IN (1 << 4) 1077 #define I2C_DATA_DIRECTION_MASK (1 << 8) 1078 #define I2C_DATA_DIRECTION_OUT (1 << 9) 1079 #define I2C_DATA_VALUE_MASK (1 << 10) 1080 #define I2C_DATA_VALUE_OUT (1 << 11) 1081 #define I2C_DATA_VALUE_IN (1 << 12) 1082 #define I2C_RESERVED ((1 << 13) | (1 << 5)) 1083 1084 // gpu block clock gating disable bits 1085 #define INTEL_DSPCLK_GATE_D (0x2020 | REGS_SOUTH_SHARED) 1086 #define PCH_GMBUSUNIT_CLK_GATE_DIS (1UL << 31) 1087 #define INTEL_GEN9_CLKGATE_DIS_4 (0x653c | REGS_NORTH_SHARED) 1088 #define BXT_GMBUSUNIT_CLK_GATE_DIS (1 << 14) 1089 1090 // gpu power wells 1091 #define INTEL_PWR_WELL_CTL_2 (0x5404 | REGS_NORTH_SHARED) 1092 1093 // TODO: on IronLake this is in the north shared block at 0x41000 1094 #define INTEL_VGA_DISPLAY_CONTROL (0x1400 | REGS_NORTH_PLANE_CONTROL) 1095 #define VGA_DISPLAY_DISABLED (1UL << 31) 1096 1097 // LVDS panel 1098 #define INTEL_PANEL_STATUS (0x1200 | REGS_NORTH_PIPE_AND_PORT) 1099 #define INTEL_PANEL_CONTROL (0x1204 | REGS_NORTH_PIPE_AND_PORT) 1100 #define INTEL_PANEL_FIT_CONTROL (0x1230 | REGS_NORTH_PIPE_AND_PORT) 1101 #define INTEL_PANEL_FIT_RATIOS (0x1234 | REGS_NORTH_PIPE_AND_PORT) 1102 1103 // LVDS on IronLake and up 1104 #define PCH_PANEL_STATUS (0x7200 | REGS_SOUTH_SHARED) 1105 #define PCH_PANEL_CONTROL (0x7204 | REGS_SOUTH_SHARED) 1106 #define PCH_PANEL_ON_DELAYS (0x7208 | REGS_SOUTH_SHARED) 1107 #define PCH_PANEL_OFF_DELAYS (0x720c | REGS_SOUTH_SHARED) 1108 #define PCH_PANEL_DIVISOR (0x7210 | REGS_SOUTH_SHARED) 1109 #define PCH_LVDS_DETECTED (1 << 1) 1110 1111 #define PANEL_STATUS_POWER_ON (1UL << 31) 1112 #define PANEL_CONTROL_POWER_TARGET_OFF (0UL << 0) 1113 #define PANEL_CONTROL_POWER_TARGET_ON (1UL << 0) 1114 #define PANEL_CONTROL_POWER_TARGET_RST (1UL << 1) 1115 #define PANEL_REGISTER_UNLOCK (0xabcd << 16) 1116 1117 // PCH_PANEL_ON_DELAYS 1118 #define PANEL_DELAY_PORT_SELECT_MASK (3 << 30) 1119 #define PANEL_DELAY_PORT_SELECT_LVDS (0 << 30) 1120 #define PANEL_DELAY_PORT_SELECT_DPA (1 << 30) 1121 #define PANEL_DELAY_PORT_SELECT_DPC (2 << 30) 1122 #define PANEL_DELAY_PORT_SELECT_DPD (3 << 30) 1123 1124 // PCH_PANEL_DIVISOR 1125 #define PANEL_DIVISOR_REFERENCE_DIV_MASK 0xffffff00 1126 #define PANEL_DIVISOR_REFERENCE_DIV_SHIFT 8 1127 #define PANEL_DIVISOR_POW_CYCLE_DLY_MASK 0x1f 1128 #define PANEL_DIVISOR_POW_CYCLE_DLY_SHIFT 0x1f 1129 1130 // Backlight control registers 1131 #define PCH_BLC_PWM_CTL2 (0x8250 | REGS_NORTH_SHARED) 1132 #define PCH_BLC_PWM_CTL (0x8254 | REGS_NORTH_SHARED) 1133 #define PCH_SBLC_PWM_CTL2 (0x8254 | REGS_SOUTH_SHARED) 1134 1135 #define MCH_BLC_PWM_CTL (0x1254 | REGS_NORTH_PIPE_AND_PORT) 1136 1137 // ring buffer commands 1138 1139 #define COMMAND_NOOP 0x00 1140 #define COMMAND_WAIT_FOR_EVENT (0x03 << 23) 1141 #define COMMAND_WAIT_FOR_OVERLAY_FLIP (1 << 16) 1142 1143 #define COMMAND_FLUSH (0x04 << 23) 1144 1145 // overlay flip 1146 #define COMMAND_OVERLAY_FLIP (0x11 << 23) 1147 #define COMMAND_OVERLAY_CONTINUE (0 << 21) 1148 #define COMMAND_OVERLAY_ON (1 << 21) 1149 #define COMMAND_OVERLAY_OFF (2 << 21) 1150 #define OVERLAY_UPDATE_COEFFICIENTS 0x1 1151 1152 // 2D acceleration 1153 #define XY_COMMAND_SOURCE_BLIT 0x54c00006 1154 #define XY_COMMAND_COLOR_BLIT 0x54000004 1155 #define XY_COMMAND_SETUP_MONO_PATTERN 0x44400007 1156 #define XY_COMMAND_SCANLINE_BLIT 0x49400001 1157 #define COMMAND_COLOR_BLIT 0x50000003 1158 #define COMMAND_BLIT_RGBA 0x00300000 1159 1160 #define COMMAND_MODE_SOLID_PATTERN 0x80 1161 #define COMMAND_MODE_CMAP8 0x00 1162 #define COMMAND_MODE_RGB15 0x02 1163 #define COMMAND_MODE_RGB16 0x01 1164 #define COMMAND_MODE_RGB32 0x03 1165 1166 // overlay 1167 #define INTEL_OVERLAY_UPDATE 0x30000 1168 #define INTEL_OVERLAY_TEST 0x30004 1169 #define INTEL_OVERLAY_STATUS 0x30008 1170 #define INTEL_OVERLAY_EXTENDED_STATUS 0x3000c 1171 #define INTEL_OVERLAY_GAMMA_5 0x30010 1172 #define INTEL_OVERLAY_GAMMA_4 0x30014 1173 #define INTEL_OVERLAY_GAMMA_3 0x30018 1174 #define INTEL_OVERLAY_GAMMA_2 0x3001c 1175 #define INTEL_OVERLAY_GAMMA_1 0x30020 1176 #define INTEL_OVERLAY_GAMMA_0 0x30024 1177 1178 // FDI - Flexible Display Interface, the interface between the (CPU-internal) 1179 // GPU and the PCH display outputs. Proprietary interface, based on DisplayPort 1180 // though, so similar link training and all... 1181 // There's an FDI transmitter (TX) on the CPU and an FDI receiver (RX) on the 1182 // PCH for each display pipe. 1183 // FDI receiver A is hooked up to transcoder A, FDI receiver B is hooked up to 1184 // transcoder B, so we have the same mapping as with the display pipes. 1185 #define PCH_FDI_RX_BASE_REGISTER 0xf0000 1186 #define PCH_FDI_RX_PIPE_OFFSET 0x01000 1187 #define PCH_FDI_RX_CONTROL 0x00c 1188 #define PCH_FDI_RX_MISC 0x010 1189 #define PCH_FDI_RX_IIR 0x014 1190 #define PCH_FDI_RX_IMR 0x018 1191 1192 #define FDI_RX_ENABLE (1 << 31) 1193 #define FDI_RX_PLL_ENABLED (1 << 13) 1194 1195 #define FDI_RX_LINK_COLOR_SHIFT 16 1196 #define FDI_RX_LINK_BPC(x) ((x) << FDI_RX_LINK_COLOR_SHIFT) 1197 #define FDI_RX_LINK_BPC_MASK (7 << FDI_RX_LINK_COLOR_SHIFT) 1198 1199 // Transcoder - same base as FDI_RX 1200 #define PCH_TRANS_CONF_A 0x0008 1201 #define PCH_TRANS_CONF_B 0x1008 1202 #define PCH_TRANS_CONF_C 0x2008 1203 1204 // Transcoder - skylake DDI 1205 #define DDI_SKL_TRANS_CONF_A (0x0008 | REGS_NORTH_PLANE_CONTROL) 1206 #define DDI_SKL_TRANS_CONF_B (0x1008 | REGS_NORTH_PLANE_CONTROL) 1207 #define DDI_SKL_TRANS_CONF_C (0x2008 | REGS_NORTH_PLANE_CONTROL) 1208 #define DDI_SKL_TRANS_CONF_EDP (0xf008 | REGS_NORTH_PLANE_CONTROL) 1209 1210 #define TRANS_ENABLE (1 << 31) 1211 #define TRANS_ENABLED (1 << 30) 1212 1213 // FDI_tX interrupt register 1214 #define FDI_RX_INTER_LANE_ALIGN (1 << 10) 1215 #define FDI_RX_SYMBOL_LOCK (1 << 9) 1216 #define FDI_RX_BIT_LOCK (1 << 8) 1217 #define FDI_RX_TRAIN_PATTERN_2_FAIL (1 << 7) 1218 #define FDI_RX_FS_CODE_ERR (1 << 6) 1219 #define FDI_RX_FE_CODE_ERR (1 << 5) 1220 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1 << 4) 1221 #define FDI_RX_HDCP_LINK_FAIL (1 << 3) 1222 #define FDI_RX_PIXEL_FIFO_OVERFLOW (1 << 2) 1223 #define FDI_RX_CROSS_CLOCK_OVERFLOW (1 << 1) 1224 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1 << 0) 1225 1226 #define FDI_FS_ERRC_ENABLE (1 << 27) 1227 #define FDI_FE_ERRC_ENABLE (1 << 26) 1228 1229 #define PCH_FDI_RX_TRANS_UNIT_SIZE_1 0x30 1230 #define PCH_FDI_RX_TRANS_UNIT_SIZE_2 0x38 1231 #define FDI_RX_TRANS_UNIT_SIZE(x) ((x - 1) << 25) 1232 #define FDI_RX_TRANS_UNIT_MASK 0x7e000000 1233 1234 #define FDI_RX_ENHANCE_FRAME_ENABLE (1 << 6) 1235 #define FDI_RX_CLOCK_MASK (1 << 4) 1236 #define FDI_RX_CLOCK_RAW (0 << 4) 1237 #define FDI_RX_CLOCK_PCD (1 << 4) 1238 1239 // FDI RX MISC 1240 #define FDI_RX_PWRDN_LANE1_MASK (3 << 26) 1241 #define FDI_RX_PWRDN_LANE1_VAL(x) ((x) << 26) 1242 #define FDI_RX_PWRDN_LANE0_MASK (3 << 24) 1243 #define FDI_RX_PWRDN_LANE0_VAL(x) ((x) << 24) 1244 #define FDI_RX_TP1_TO_TP2_48 (2 << 20) 1245 #define FDI_RX_TP1_TO_TP2_64 (3 << 20) 1246 #define FDI_RX_FDI_DELAY_90 (0x90 << 0) 1247 1248 #define PCH_FDI_TX_BASE_REGISTER 0x60000 1249 #define PCH_FDI_TX_PIPE_OFFSET 0x01000 1250 #define PCH_FDI_TX_CONTROL 0x100 1251 #define FDI_TX_ENABLE (1 << 31) 1252 #define FDI_LINK_TRAIN_PATTERN_1 (0 << 28) 1253 #define FDI_LINK_TRAIN_PATTERN_2 (1 << 28) 1254 #define FDI_LINK_TRAIN_PATTERN_IDLE (2 << 28) 1255 #define FDI_LINK_TRAIN_NONE (3 << 28) 1256 #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0 << 25) 1257 #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1 << 25) 1258 #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2 << 25) 1259 #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3 << 25) 1260 #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0 << 22) 1261 #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1 << 22) 1262 #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2 << 22) 1263 #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3 << 22) 1264 1265 // FDI/PIPE M/N DATA AND LINK VALUES (refreshrate) 1266 #define PCH_FDI_PIPE_A_DATA_M1 (0x0030 | REGS_NORTH_PIPE_AND_PORT) 1267 #define PCH_FDI_PIPE_A_DATA_M2 (0x0038 | REGS_NORTH_PIPE_AND_PORT) 1268 #define PCH_FDI_PIPE_B_DATA_M1 (0x1030 | REGS_NORTH_PIPE_AND_PORT) 1269 #define PCH_FDI_PIPE_B_DATA_M2 (0x1038 | REGS_NORTH_PIPE_AND_PORT) 1270 #define PCH_FDI_PIPE_C_DATA_M1 (0x2030 | REGS_NORTH_PIPE_AND_PORT) 1271 #define PCH_FDI_PIPE_C_DATA_M2 (0x2038 | REGS_NORTH_PIPE_AND_PORT) 1272 #define PCH_FDI_PIPE_A_DATA_N1 (0x0034 | REGS_NORTH_PIPE_AND_PORT) 1273 #define PCH_FDI_PIPE_A_DATA_N2 (0x003c | REGS_NORTH_PIPE_AND_PORT) 1274 #define PCH_FDI_PIPE_B_DATA_N1 (0x1034 | REGS_NORTH_PIPE_AND_PORT) 1275 #define PCH_FDI_PIPE_B_DATA_N2 (0x103c | REGS_NORTH_PIPE_AND_PORT) 1276 #define PCH_FDI_PIPE_C_DATA_N1 (0x2034 | REGS_NORTH_PIPE_AND_PORT) 1277 #define PCH_FDI_PIPE_C_DATA_N2 (0x203c | REGS_NORTH_PIPE_AND_PORT) 1278 #define PCH_FDI_PIPE_A_LINK_M1 (0x0040 | REGS_NORTH_PIPE_AND_PORT) 1279 #define PCH_FDI_PIPE_A_LINK_M2 (0x0048 | REGS_NORTH_PIPE_AND_PORT) 1280 #define PCH_FDI_PIPE_B_LINK_M1 (0x1040 | REGS_NORTH_PIPE_AND_PORT) 1281 #define PCH_FDI_PIPE_B_LINK_M2 (0x1048 | REGS_NORTH_PIPE_AND_PORT) 1282 #define PCH_FDI_PIPE_C_LINK_M1 (0x2040 | REGS_NORTH_PIPE_AND_PORT) 1283 #define PCH_FDI_PIPE_C_LINK_M2 (0x2048 | REGS_NORTH_PIPE_AND_PORT) 1284 #define PCH_FDI_PIPE_A_LINK_N1 (0x0044 | REGS_NORTH_PIPE_AND_PORT) 1285 #define PCH_FDI_PIPE_A_LINK_N2 (0x004c | REGS_NORTH_PIPE_AND_PORT) 1286 #define PCH_FDI_PIPE_B_LINK_N1 (0x1044 | REGS_NORTH_PIPE_AND_PORT) 1287 #define PCH_FDI_PIPE_B_LINK_N2 (0x104c | REGS_NORTH_PIPE_AND_PORT) 1288 #define PCH_FDI_PIPE_C_LINK_N1 (0x2044 | REGS_NORTH_PIPE_AND_PORT) 1289 #define PCH_FDI_PIPE_C_LINK_N2 (0x204c | REGS_NORTH_PIPE_AND_PORT) 1290 #define FDI_PIPE_MN_TU_SIZE_MASK (0x3f << 25) 1291 #define FDI_PIPE_MN_VALUE_MASK (0xffffff << 0) 1292 1293 // SNB A stepping 1294 #define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22) 1295 #define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22) 1296 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22) 1297 #define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x00 << 22) 1298 1299 // SNB B stepping 1300 #define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x00 << 22) 1301 #define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a << 22) 1302 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39 << 22) 1303 #define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38 << 22) 1304 #define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f << 22) 1305 #define FDI_TX_ENHANCE_FRAME_ENABLE (1 << 18) 1306 #define FDI_TX_PLL_ENABLED (1 << 14) 1307 1308 #define FDI_DP_PORT_WIDTH_SHIFT 19 1309 #define FDI_DP_PORT_WIDTH_MASK (7 << FDI_DP_PORT_WIDTH_SHIFT) 1310 #define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT) 1311 1312 #define FDI_PLL_BIOS_0 0x46000 1313 #define FDI_PLL_FB_CLOCK_MASK 0xff 1314 #define FDI_PLL_BIOS_1 0x46004 1315 #define FDI_PLL_BIOS_2 0x46008 1316 1317 #define FDI_AUTO_TRAINING (1 << 10) 1318 #define FDI_AUTO_TRAIN_DONE (1 << 1) 1319 1320 #define FDI_LINK_TRAIN_PATTERN_1_CPT (0 << 8) 1321 #define FDI_LINK_TRAIN_PATTERN_2_CPT (1 << 8) 1322 #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2 << 8) 1323 #define FDI_LINK_TRAIN_NORMAL_CPT (3 << 8) 1324 #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3 << 8) 1325 1326 // IvyBridge changes it up because... they hate developers? 1327 #define FDI_LINK_TRAIN_PATTERN_1_IVB (0 << 8) 1328 #define FDI_LINK_TRAIN_PATTERN_2_IVB (1 << 8) 1329 #define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2 << 8) 1330 #define FDI_LINK_TRAIN_NONE_IVB (3 << 8) 1331 1332 #define PCH_FDI_RXA_CHICKEN (0x200c | REGS_SOUTH_SHARED) 1333 #define PCH_FDI_RXB_CHICKEN (0x2010 | REGS_SOUTH_SHARED) 1334 #define FDI_RX_PHASE_SYNC_POINTER_EN (1 << 0) 1335 #define FDI_RX_PHASE_SYNC_POINTER_OVR (1 << 1) 1336 1337 // CPU Panel Fitters - These are for IronLake and up and are the CPU internal 1338 // panel fitters. 1339 #define PCH_PANEL_FITTER_BASE_REGISTER 0x68000 1340 #define PCH_PANEL_FITTER_PIPE_OFFSET 0x00800 1341 1342 #define PCH_PANEL_FITTER_WINDOW_POS 0x70 1343 #define PCH_PANEL_FITTER_WINDOW_SIZE 0x74 1344 #define PCH_PANEL_FITTER_CONTROL 0x80 1345 //not on IvyBridge: 1346 #define PCH_PANEL_FITTER_V_SCALE 0x84 1347 #define PCH_PANEL_FITTER_H_SCALE 0x90 1348 1349 #define PANEL_FITTER_ENABLED (1 << 31) 1350 //pipes are hardcoded according to offset on SkyLake and later 1351 #define PANEL_FITTER_PIPE_MASK (3 << 29) 1352 #define PANEL_FITTER_PIPE_A (0 << 29) 1353 #define PANEL_FITTER_PIPE_B (1 << 29) 1354 #define PANEL_FITTER_PIPE_C (2 << 29) 1355 #define PANEL_FITTER_SCALING_MODE_MASK (7 << 26) 1356 #define PANEL_FITTER_FILTER_MASK (3 << 24) 1357 1358 struct overlay_scale { 1359 uint32 _reserved0 : 3; 1360 uint32 horizontal_scale_fraction : 12; 1361 uint32 _reserved1 : 1; 1362 uint32 horizontal_downscale_factor : 3; 1363 uint32 _reserved2 : 1; 1364 uint32 vertical_scale_fraction : 12; 1365 }; 1366 1367 #define OVERLAY_FORMAT_RGB15 0x2 1368 #define OVERLAY_FORMAT_RGB16 0x3 1369 #define OVERLAY_FORMAT_RGB32 0x1 1370 #define OVERLAY_FORMAT_YCbCr422 0x8 1371 #define OVERLAY_FORMAT_YCbCr411 0x9 1372 #define OVERLAY_FORMAT_YCbCr420 0xc 1373 1374 #define OVERLAY_MIRROR_NORMAL 0x0 1375 #define OVERLAY_MIRROR_HORIZONTAL 0x1 1376 #define OVERLAY_MIRROR_VERTICAL 0x2 1377 1378 // The real overlay registers are written to using an update buffer 1379 1380 struct overlay_registers { 1381 uint32 buffer_rgb0; 1382 uint32 buffer_rgb1; 1383 uint32 buffer_u0; 1384 uint32 buffer_v0; 1385 uint32 buffer_u1; 1386 uint32 buffer_v1; 1387 // (0x18) OSTRIDE - overlay stride 1388 uint16 stride_rgb; 1389 uint16 stride_uv; 1390 // (0x1c) YRGB_VPH - Y/RGB vertical phase 1391 uint16 vertical_phase0_rgb; 1392 uint16 vertical_phase1_rgb; 1393 // (0x20) UV_VPH - UV vertical phase 1394 uint16 vertical_phase0_uv; 1395 uint16 vertical_phase1_uv; 1396 // (0x24) HORZ_PH - horizontal phase 1397 uint16 horizontal_phase_rgb; 1398 uint16 horizontal_phase_uv; 1399 // (0x28) INIT_PHS - initial phase shift 1400 uint32 initial_vertical_phase0_shift_rgb0 : 4; 1401 uint32 initial_vertical_phase1_shift_rgb0 : 4; 1402 uint32 initial_horizontal_phase_shift_rgb0 : 4; 1403 uint32 initial_vertical_phase0_shift_uv : 4; 1404 uint32 initial_vertical_phase1_shift_uv : 4; 1405 uint32 initial_horizontal_phase_shift_uv : 4; 1406 uint32 _reserved0 : 8; 1407 // (0x2c) DWINPOS - destination window position 1408 uint16 window_left; 1409 uint16 window_top; 1410 // (0x30) DWINSZ - destination window size 1411 uint16 window_width; 1412 uint16 window_height; 1413 // (0x34) SWIDTH - source width 1414 uint16 source_width_rgb; 1415 uint16 source_width_uv; 1416 // (0x38) SWITDHSW - source width in 8 byte steps 1417 uint16 source_bytes_per_row_rgb; 1418 uint16 source_bytes_per_row_uv; 1419 uint16 source_height_rgb; 1420 uint16 source_height_uv; 1421 overlay_scale scale_rgb; 1422 overlay_scale scale_uv; 1423 // (0x48) OCLRC0 - overlay color correction 0 1424 uint32 brightness_correction : 8; // signed, -128 to 127 1425 uint32 _reserved1 : 10; 1426 uint32 contrast_correction : 9; // fixed point: 3.6 bits 1427 uint32 _reserved2 : 5; 1428 // (0x4c) OCLRC1 - overlay color correction 1 1429 uint32 saturation_cos_correction : 10; // fixed point: 3.7 bits 1430 uint32 _reserved3 : 6; 1431 uint32 saturation_sin_correction : 11; // signed fixed point: 3.7 bits 1432 uint32 _reserved4 : 5; 1433 // (0x50) DCLRKV - destination color key value 1434 uint32 color_key_blue : 8; 1435 uint32 color_key_green : 8; 1436 uint32 color_key_red : 8; 1437 uint32 _reserved5 : 8; 1438 // (0x54) DCLRKM - destination color key mask 1439 uint32 color_key_mask_blue : 8; 1440 uint32 color_key_mask_green : 8; 1441 uint32 color_key_mask_red : 8; 1442 uint32 _reserved6 : 7; 1443 uint32 color_key_enabled : 1; 1444 // (0x58) SCHRKVH - source chroma key high value 1445 uint32 source_chroma_key_high_red : 8; 1446 uint32 source_chroma_key_high_blue : 8; 1447 uint32 source_chroma_key_high_green : 8; 1448 uint32 _reserved7 : 8; 1449 // (0x5c) SCHRKVL - source chroma key low value 1450 uint32 source_chroma_key_low_red : 8; 1451 uint32 source_chroma_key_low_blue : 8; 1452 uint32 source_chroma_key_low_green : 8; 1453 uint32 _reserved8 : 8; 1454 // (0x60) SCHRKEN - source chroma key enable 1455 uint32 _reserved9 : 24; 1456 uint32 source_chroma_key_red_enabled : 1; 1457 uint32 source_chroma_key_blue_enabled : 1; 1458 uint32 source_chroma_key_green_enabled : 1; 1459 uint32 _reserved10 : 5; 1460 // (0x64) OCONFIG - overlay configuration 1461 uint32 _reserved11 : 3; 1462 uint32 color_control_output_mode : 1; 1463 uint32 yuv_to_rgb_bypass : 1; 1464 uint32 _reserved12 : 11; 1465 uint32 gamma2_enabled : 1; 1466 uint32 _reserved13 : 1; 1467 uint32 select_pipe : 1; 1468 uint32 slot_time : 8; 1469 uint32 _reserved14 : 5; 1470 // (0x68) OCOMD - overlay command 1471 uint32 overlay_enabled : 1; 1472 uint32 active_field : 1; 1473 uint32 active_buffer : 2; 1474 uint32 test_mode : 1; 1475 uint32 buffer_field_mode : 1; 1476 uint32 _reserved15 : 1; 1477 uint32 tv_flip_field_enabled : 1; 1478 uint32 _reserved16 : 1; 1479 uint32 tv_flip_field_parity : 1; 1480 uint32 source_format : 4; 1481 uint32 ycbcr422_order : 2; 1482 uint32 _reserved18 : 1; 1483 uint32 mirroring_mode : 2; 1484 uint32 _reserved19 : 13; 1485 1486 uint32 _reserved20; 1487 1488 uint32 start_0y; 1489 uint32 start_1y; 1490 uint32 start_0u; 1491 uint32 start_0v; 1492 uint32 start_1u; 1493 uint32 start_1v; 1494 uint32 _reserved21[6]; 1495 #if 0 1496 // (0x70) AWINPOS - alpha blend window position 1497 uint32 awinpos; 1498 // (0x74) AWINSZ - alpha blend window size 1499 uint32 awinsz; 1500 1501 uint32 _reserved21[10]; 1502 #endif 1503 1504 // (0xa0) FASTHSCALE - fast horizontal downscale (strangely enough, 1505 // the next two registers switch the usual Y/RGB vs. UV order) 1506 uint16 horizontal_scale_uv; 1507 uint16 horizontal_scale_rgb; 1508 // (0xa4) UVSCALEV - vertical downscale 1509 uint16 vertical_scale_uv; 1510 uint16 vertical_scale_rgb; 1511 1512 uint32 _reserved22[86]; 1513 1514 // (0x200) polyphase filter coefficients 1515 uint16 vertical_coefficients_rgb[128]; 1516 uint16 horizontal_coefficients_rgb[128]; 1517 1518 uint32 _reserved23[64]; 1519 1520 // (0x500) 1521 uint16 vertical_coefficients_uv[128]; 1522 uint16 horizontal_coefficients_uv[128]; 1523 }; 1524 1525 // i965 overlay support is currently realized using its 3D hardware 1526 #define INTEL_i965_OVERLAY_STATE_SIZE 36864 1527 #define INTEL_i965_3D_CONTEXT_SIZE 32768 1528 1529 inline bool 1530 intel_uses_physical_overlay(intel_shared_info &info) 1531 { 1532 return !info.device_type.InGroup(INTEL_GROUP_Gxx); 1533 } 1534 1535 1536 struct hardware_status { 1537 uint32 interrupt_status_register; 1538 uint32 _reserved0[3]; 1539 void* primary_ring_head_storage; 1540 uint32 _reserved1[3]; 1541 void* secondary_ring_0_head_storage; 1542 void* secondary_ring_1_head_storage; 1543 uint32 _reserved2[2]; 1544 void* binning_head_storage; 1545 uint32 _reserved3[3]; 1546 uint32 store[1008]; 1547 }; 1548 1549 #endif /* INTEL_EXTREME_H */ 1550