1 /* 2 * Copyright 2006-2016, Haiku, Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Axel Dörfler, axeld@pinc-software.de 7 * Alexander von Gluck, kallisti5@unixzen.com 8 */ 9 #ifndef INTEL_EXTREME_H 10 #define INTEL_EXTREME_H 11 12 13 #include "lock.h" 14 15 #include <Accelerant.h> 16 #include <Drivers.h> 17 #include <PCI.h> 18 19 #include <edid.h> 20 21 22 #define VENDOR_ID_INTEL 0x8086 23 24 #define INTEL_FAMILY_MASK 0x00ff0000 25 #define INTEL_GROUP_MASK 0x00fffff0 26 #define INTEL_MODEL_MASK 0x00ffffff 27 #define INTEL_TYPE_MASK 0x0000000f 28 29 // families 30 #define INTEL_FAMILY_8xx 0x00020000 // Second Gen 31 #define INTEL_FAMILY_9xx 0x00040000 // Third Gen + 32 #define INTEL_FAMILY_SER5 0x00080000 // Intel5 Series 33 #define INTEL_FAMILY_SOC0 0x00200000 // Atom SOC 34 #define INTEL_FAMILY_LAKE 0x00400000 // Intel Lakes 35 36 // groups 37 #define INTEL_GROUP_83x (INTEL_FAMILY_8xx | 0x0010) 38 #define INTEL_GROUP_85x (INTEL_FAMILY_8xx | 0x0020) 39 #define INTEL_GROUP_91x (INTEL_FAMILY_9xx | 0x0010) 40 #define INTEL_GROUP_94x (INTEL_FAMILY_9xx | 0x0020) 41 #define INTEL_GROUP_96x (INTEL_FAMILY_9xx | 0x0040) 42 #define INTEL_GROUP_Gxx (INTEL_FAMILY_9xx | 0x0080) 43 #define INTEL_GROUP_G4x (INTEL_FAMILY_9xx | 0x0100) 44 #define INTEL_GROUP_PIN (INTEL_FAMILY_9xx | 0x0200) // PineView 45 #define INTEL_GROUP_ILK (INTEL_FAMILY_SER5 | 0x0010) // IronLake 46 #define INTEL_GROUP_SNB (INTEL_FAMILY_SER5 | 0x0020) // SandyBridge 47 #define INTEL_GROUP_IVB (INTEL_FAMILY_SER5 | 0x0040) // IvyBridge 48 #define INTEL_GROUP_HAS (INTEL_FAMILY_SER5 | 0x0080) // Haswell 49 #define INTEL_GROUP_VLV (INTEL_FAMILY_SOC0 | 0x0010) // ValleyView 50 #define INTEL_GROUP_CHV (INTEL_FAMILY_SOC0 | 0x0020) // CherryView 51 #define INTEL_GROUP_BDW (INTEL_FAMILY_SOC0 | 0x0040) // Broadwell 52 #define INTEL_GROUP_SKY (INTEL_FAMILY_LAKE | 0x0010) // SkyLake 53 #define INTEL_GROUP_KBY (INTEL_FAMILY_LAKE | 0x0020) // KabyLake 54 // models 55 #define INTEL_TYPE_SERVER 0x0004 56 #define INTEL_TYPE_MOBILE 0x0008 57 #define INTEL_MODEL_915 (INTEL_GROUP_91x) 58 #define INTEL_MODEL_915M (INTEL_GROUP_91x | INTEL_TYPE_MOBILE) 59 #define INTEL_MODEL_945 (INTEL_GROUP_94x) 60 #define INTEL_MODEL_945M (INTEL_GROUP_94x | INTEL_TYPE_MOBILE) 61 #define INTEL_MODEL_965 (INTEL_GROUP_96x) 62 #define INTEL_MODEL_965M (INTEL_GROUP_96x | INTEL_TYPE_MOBILE) 63 #define INTEL_MODEL_G33 (INTEL_GROUP_Gxx) 64 #define INTEL_MODEL_G45 (INTEL_GROUP_G4x) 65 #define INTEL_MODEL_GM45 (INTEL_GROUP_G4x | INTEL_TYPE_MOBILE) 66 #define INTEL_MODEL_PINE (INTEL_GROUP_PIN) 67 #define INTEL_MODEL_PINEM (INTEL_GROUP_PIN | INTEL_TYPE_MOBILE) 68 #define INTEL_MODEL_ILKG (INTEL_GROUP_ILK) 69 #define INTEL_MODEL_ILKGM (INTEL_GROUP_ILK | INTEL_TYPE_MOBILE) 70 #define INTEL_MODEL_SNBG (INTEL_GROUP_SNB) 71 #define INTEL_MODEL_SNBGM (INTEL_GROUP_SNB | INTEL_TYPE_MOBILE) 72 #define INTEL_MODEL_SNBGS (INTEL_GROUP_SNB | INTEL_TYPE_SERVER) 73 #define INTEL_MODEL_IVBG (INTEL_GROUP_IVB) 74 #define INTEL_MODEL_IVBGM (INTEL_GROUP_IVB | INTEL_TYPE_MOBILE) 75 #define INTEL_MODEL_IVBGS (INTEL_GROUP_IVB | INTEL_TYPE_SERVER) 76 #define INTEL_MODEL_HAS (INTEL_GROUP_HAS) 77 #define INTEL_MODEL_HASM (INTEL_GROUP_HAS | INTEL_TYPE_MOBILE) 78 #define INTEL_MODEL_VLV (INTEL_GROUP_VLV) 79 #define INTEL_MODEL_VLVM (INTEL_GROUP_VLV | INTEL_TYPE_MOBILE) 80 #define INTEL_MODEL_BDW (INTEL_GROUP_BDW) 81 #define INTEL_MODEL_BDWM (INTEL_GROUP_BDW | INTEL_TYPE_MOBILE) 82 #define INTEL_MODEL_SKY (INTEL_GROUP_SKY) 83 #define INTEL_MODEL_SKYM (INTEL_GROUP_SKY | INTEL_TYPE_MOBILE) 84 #define INTEL_MODEL_SKYS (INTEL_GROUP_SKY | INTEL_TYPE_SERVER) 85 86 #define INTEL_PCH_DEVICE_ID_MASK 0xff80 87 #define INTEL_PCH_IBX_DEVICE_ID 0x3b00 88 #define INTEL_PCH_CPT_DEVICE_ID 0x1c00 89 #define INTEL_PCH_PPT_DEVICE_ID 0x1e00 90 #define INTEL_PCH_LPT_DEVICE_ID 0x8c00 91 #define INTEL_PCH_LPT_LP_DEVICE_ID 0x9c00 92 #define INTEL_PCH_WPT_DEVICE_ID 0x8c80 93 #define INTEL_PCH_WPT_LP_DEVICE_ID 0x9c80 94 #define INTEL_PCH_SPT_DEVICE_ID 0xa100 95 #define INTEL_PCH_SPT_LP_DEVICE_ID 0x9d00 96 #define INTEL_PCH_KBP_DEVICE_ID 0xa280 97 #define INTEL_PCH_CNP_DEVICE_ID 0xa300 98 #define INTEL_PCH_CNP_LP_DEVICE_ID 0x9d80 99 #define INTEL_PCH_ICP_DEVICE_ID 0x3480 100 #define INTEL_PCH_P2X_DEVICE_ID 0x7100 101 #define INTEL_PCH_P3X_DEVICE_ID 0x7000 102 103 // ValleyView MMIO offset 104 #define VLV_DISPLAY_BASE 0x180000 105 106 #define DEVICE_NAME "intel_extreme" 107 #define INTEL_ACCELERANT_NAME "intel_extreme.accelerant" 108 109 // We encode the register block into the value and extract/translate it when 110 // actually accessing. 111 #define REGISTER_BLOCK_COUNT 6 112 #define REGISTER_BLOCK_SHIFT 24 113 #define REGISTER_BLOCK_MASK 0xff000000 114 #define REGISTER_REGISTER_MASK 0x00ffffff 115 #define REGISTER_BLOCK(x) ((x & REGISTER_BLOCK_MASK) >> REGISTER_BLOCK_SHIFT) 116 #define REGISTER_REGISTER(x) (x & REGISTER_REGISTER_MASK) 117 118 #define REGS_FLAT (0 << REGISTER_BLOCK_SHIFT) 119 #define REGS_NORTH_SHARED (1 << REGISTER_BLOCK_SHIFT) 120 #define REGS_NORTH_PIPE_AND_PORT (2 << REGISTER_BLOCK_SHIFT) 121 #define REGS_NORTH_PLANE_CONTROL (3 << REGISTER_BLOCK_SHIFT) 122 #define REGS_SOUTH_SHARED (4 << REGISTER_BLOCK_SHIFT) 123 #define REGS_SOUTH_TRANSCODER_PORT (5 << REGISTER_BLOCK_SHIFT) 124 125 // register blocks for (G)MCH/ICH based platforms 126 #define MCH_SHARED_REGISTER_BASE 0x00000 127 #define MCH_PIPE_AND_PORT_REGISTER_BASE 0x60000 128 #define MCH_PLANE_CONTROL_REGISTER_BASE 0x70000 129 130 #define ICH_SHARED_REGISTER_BASE 0x00000 131 #define ICH_PORT_REGISTER_BASE 0x60000 132 133 // PCH - Platform Control Hub - Some hardware moves from a MCH/ICH based 134 // setup to a PCH based one, that means anything that used to communicate via 135 // (G)MCH registers needs to use different ones on PCH based platforms 136 // (Ironlake, SandyBridge, IvyBridge, Some Haswell). 137 #define PCH_NORTH_SHARED_REGISTER_BASE 0x40000 138 #define PCH_NORTH_PIPE_AND_PORT_REGISTER_BASE 0x60000 139 #define PCH_NORTH_PLANE_CONTROL_REGISTER_BASE 0x70000 140 #define PCH_SOUTH_SHARED_REGISTER_BASE 0xc0000 141 #define PCH_SOUTH_TRANSCODER_AND_PORT_REGISTER_BASE 0xe0000 142 143 144 struct DeviceType { 145 uint32 type; 146 147 DeviceType(int t) 148 { 149 type = t; 150 } 151 152 DeviceType& operator=(int t) 153 { 154 type = t; 155 return *this; 156 } 157 158 bool InFamily(uint32 family) const 159 { 160 return (type & INTEL_FAMILY_MASK) == family; 161 } 162 163 bool InGroup(uint32 group) const 164 { 165 return (type & INTEL_GROUP_MASK) == group; 166 } 167 168 bool IsModel(uint32 model) const 169 { 170 return (type & INTEL_MODEL_MASK) == model; 171 } 172 173 bool IsMobile() const 174 { 175 return (type & INTEL_TYPE_MASK) == INTEL_TYPE_MOBILE; 176 } 177 178 bool SupportsHDMI() const 179 { 180 return InGroup(INTEL_GROUP_G4x) || InFamily(INTEL_FAMILY_SER5) 181 || InFamily(INTEL_FAMILY_SOC0); 182 } 183 184 bool HasDDI() const 185 { 186 // Intel Digital Display Interface 187 return InGroup(INTEL_GROUP_HAS) || (Generation() >= 8); 188 } 189 190 int Generation() const 191 { 192 if (InFamily(INTEL_FAMILY_8xx)) 193 return 2; 194 if (InGroup(INTEL_GROUP_91x) || InGroup(INTEL_GROUP_94x) 195 || IsModel(INTEL_MODEL_G33) || InGroup(INTEL_GROUP_PIN)) 196 return 3; 197 if (InFamily(INTEL_FAMILY_9xx)) 198 return 4; 199 if (InGroup(INTEL_GROUP_ILK)) 200 return 5; 201 if (InGroup(INTEL_GROUP_SNB)) 202 return 6; 203 if (InFamily(INTEL_FAMILY_SER5) || InGroup(INTEL_GROUP_VLV)) 204 return 7; 205 if (InGroup(INTEL_GROUP_CHV) || InGroup(INTEL_GROUP_BDW)) 206 return 8; 207 if (InFamily(INTEL_FAMILY_LAKE)) 208 return 9; 209 210 // Generation 0 means something is wrong :-) 211 return 0; 212 } 213 }; 214 215 enum pch_info { 216 INTEL_PCH_NONE = 0, // No PCH present 217 INTEL_PCH_IBX, // Ibexpeak 218 INTEL_PCH_CPT, // Cougarpoint 219 INTEL_PCH_LPT, // Lynxpoint 220 INTEL_PCH_SPT, // SunrisePoint 221 INTEL_PCH_KBP, // KabyLake 222 INTEL_PCH_CNP, // CannonLake 223 INTEL_PCH_ICP, // IceLake 224 INTEL_PCH_NOP 225 }; 226 227 // info about PLL on graphics card 228 struct pll_info { 229 uint32 reference_frequency; 230 uint32 max_frequency; 231 uint32 min_frequency; 232 uint32 divisor_register; 233 }; 234 235 struct ring_buffer { 236 struct lock lock; 237 uint32 register_base; 238 uint32 offset; 239 uint32 size; 240 uint32 position; 241 uint32 space_left; 242 uint8* base; 243 }; 244 245 struct overlay_registers; 246 247 struct intel_shared_info { 248 area_id mode_list_area; // area containing display mode list 249 uint32 mode_count; 250 251 display_mode panel_mode; // VBIOS VBT panel mode 252 uint32 bytes_per_row; 253 uint32 bits_per_pixel; 254 uint32 dpms_mode; 255 256 area_id registers_area; // area of memory mapped registers 257 uint32 register_blocks[REGISTER_BLOCK_COUNT]; 258 259 uint8* status_page; 260 phys_addr_t physical_status_page; 261 uint8* graphics_memory; 262 phys_addr_t physical_graphics_memory; 263 uint32 graphics_memory_size; 264 265 addr_t frame_buffer; 266 uint32 frame_buffer_offset; 267 268 uint32 fdi_link_frequency; // In Mhz 269 270 bool got_vbt; 271 bool single_head_locked; 272 273 struct lock accelerant_lock; 274 struct lock engine_lock; 275 276 ring_buffer primary_ring_buffer; 277 278 int32 overlay_channel_used; 279 bool overlay_active; 280 uintptr_t overlay_token; 281 phys_addr_t physical_overlay_registers; 282 uint32 overlay_offset; 283 284 bool hardware_cursor_enabled; 285 sem_id vblank_sem; 286 287 uint8* cursor_memory; 288 phys_addr_t physical_cursor_memory; 289 uint32 cursor_buffer_offset; 290 uint32 cursor_format; 291 bool cursor_visible; 292 uint16 cursor_hot_x; 293 uint16 cursor_hot_y; 294 295 DeviceType device_type; 296 char device_identifier[32]; 297 struct pll_info pll_info; 298 299 enum pch_info pch_info; 300 301 edid1_info vesa_edid_info; 302 bool has_vesa_edid_info; 303 }; 304 305 enum pipe_index { 306 INTEL_PIPE_ANY, 307 INTEL_PIPE_A, 308 INTEL_PIPE_B, 309 INTEL_PIPE_C 310 }; 311 312 //----------------- ioctl() interface ---------------- 313 314 // magic code for ioctls 315 #define INTEL_PRIVATE_DATA_MAGIC 'itic' 316 317 // list ioctls 318 enum { 319 INTEL_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1, 320 321 INTEL_GET_DEVICE_NAME, 322 INTEL_ALLOCATE_GRAPHICS_MEMORY, 323 INTEL_FREE_GRAPHICS_MEMORY 324 }; 325 326 // retrieve the area_id of the kernel/accelerant shared info 327 struct intel_get_private_data { 328 uint32 magic; // magic number 329 area_id shared_info_area; 330 }; 331 332 // allocate graphics memory 333 struct intel_allocate_graphics_memory { 334 uint32 magic; 335 uint32 size; 336 uint32 alignment; 337 uint32 flags; 338 addr_t buffer_base; 339 }; 340 341 // free graphics memory 342 struct intel_free_graphics_memory { 343 uint32 magic; 344 addr_t buffer_base; 345 }; 346 347 //---------------------------------------------------------- 348 // Register definitions, taken from X driver 349 350 // PCI bridge memory management 351 #define INTEL_GRAPHICS_MEMORY_CONTROL 0x52 // i830+ 352 353 // GGC - (G)MCH Graphics Control Register 354 #define MEMORY_CONTROL_ENABLED 0x0004 355 #define MEMORY_MASK 0x0001 356 #define STOLEN_MEMORY_MASK 0x00f0 357 #define i965_GTT_MASK 0x000e 358 #define G33_GTT_MASK 0x0300 359 #define G4X_GTT_MASK 0x0f00 // GGMS (GSM Memory Size) mask 360 361 // models i830 and up 362 #define i830_LOCAL_MEMORY_ONLY 0x10 363 #define i830_STOLEN_512K 0x20 364 #define i830_STOLEN_1M 0x30 365 #define i830_STOLEN_8M 0x40 366 #define i830_FRAME_BUFFER_64M 0x01 367 #define i830_FRAME_BUFFER_128M 0x00 368 369 // models i855 and up 370 #define i855_STOLEN_MEMORY_1M 0x10 371 #define i855_STOLEN_MEMORY_4M 0x20 372 #define i855_STOLEN_MEMORY_8M 0x30 373 #define i855_STOLEN_MEMORY_16M 0x40 374 #define i855_STOLEN_MEMORY_32M 0x50 375 #define i855_STOLEN_MEMORY_48M 0x60 376 #define i855_STOLEN_MEMORY_64M 0x70 377 #define i855_STOLEN_MEMORY_128M 0x80 378 #define i855_STOLEN_MEMORY_256M 0x90 379 380 #define G4X_STOLEN_MEMORY_96MB 0xa0 // GMS - Graphics Mode Select 381 #define G4X_STOLEN_MEMORY_160MB 0xb0 382 #define G4X_STOLEN_MEMORY_224MB 0xc0 383 #define G4X_STOLEN_MEMORY_352MB 0xd0 384 385 // SandyBridge (SNB) 386 387 #define SNB_GRAPHICS_MEMORY_CONTROL 0x50 388 389 #define SNB_STOLEN_MEMORY_MASK 0xf8 390 #define SNB_STOLEN_MEMORY_32MB (1 << 3) 391 #define SNB_STOLEN_MEMORY_64MB (2 << 3) 392 #define SNB_STOLEN_MEMORY_96MB (3 << 3) 393 #define SNB_STOLEN_MEMORY_128MB (4 << 3) 394 #define SNB_STOLEN_MEMORY_160MB (5 << 3) 395 #define SNB_STOLEN_MEMORY_192MB (6 << 3) 396 #define SNB_STOLEN_MEMORY_224MB (7 << 3) 397 #define SNB_STOLEN_MEMORY_256MB (8 << 3) 398 #define SNB_STOLEN_MEMORY_288MB (9 << 3) 399 #define SNB_STOLEN_MEMORY_320MB (10 << 3) 400 #define SNB_STOLEN_MEMORY_352MB (11 << 3) 401 #define SNB_STOLEN_MEMORY_384MB (12 << 3) 402 #define SNB_STOLEN_MEMORY_416MB (13 << 3) 403 #define SNB_STOLEN_MEMORY_448MB (14 << 3) 404 #define SNB_STOLEN_MEMORY_480MB (15 << 3) 405 #define SNB_STOLEN_MEMORY_512MB (16 << 3) 406 407 #define SNB_GTT_SIZE_MASK (3 << 8) 408 #define SNB_GTT_SIZE_NONE (0 << 8) 409 #define SNB_GTT_SIZE_1MB (1 << 8) 410 #define SNB_GTT_SIZE_2MB (2 << 8) 411 412 // graphics page translation table 413 #define INTEL_PAGE_TABLE_CONTROL 0x02020 414 #define PAGE_TABLE_ENABLED 0x00000001 415 #define INTEL_PAGE_TABLE_ERROR 0x02024 416 #define INTEL_HARDWARE_STATUS_PAGE 0x02080 417 #define i915_GTT_BASE 0x1c 418 #define i830_GTT_BASE 0x10000 // (- 0x2ffff) 419 #define i830_GTT_SIZE 0x20000 420 #define i965_GTT_BASE 0x80000 // (- 0xfffff) 421 #define i965_GTT_SIZE 0x80000 422 #define i965_GTT_128K (2 << 1) 423 #define i965_GTT_256K (1 << 1) 424 #define i965_GTT_512K (0 << 1) 425 #define G33_GTT_1M (1 << 8) 426 #define G33_GTT_2M (2 << 8) 427 #define G4X_GTT_NONE 0x000 // GGMS - GSM Memory Size 428 #define G4X_GTT_1M_NO_IVT 0x100 // no Intel Virtualization Tech. 429 #define G4X_GTT_2M_NO_IVT 0x300 430 #define G4X_GTT_2M_IVT 0x900 // with Intel Virt. Tech. 431 #define G4X_GTT_3M_IVT 0xa00 432 #define G4X_GTT_4M_IVT 0xb00 433 434 435 #define GTT_ENTRY_VALID 0x01 436 #define GTT_ENTRY_LOCAL_MEMORY 0x02 437 #define GTT_PAGE_SHIFT 12 438 439 440 // ring buffer 441 #define INTEL_PRIMARY_RING_BUFFER 0x02030 442 #define INTEL_SECONDARY_RING_BUFFER_0 0x02100 443 #define INTEL_SECONDARY_RING_BUFFER_1 0x02110 444 // offsets for the ring buffer base registers above 445 #define RING_BUFFER_TAIL 0x0 446 #define RING_BUFFER_HEAD 0x4 447 #define RING_BUFFER_START 0x8 448 #define RING_BUFFER_CONTROL 0xc 449 #define INTEL_RING_BUFFER_SIZE_MASK 0x001ff000 450 #define INTEL_RING_BUFFER_HEAD_MASK 0x001ffffc 451 #define INTEL_RING_BUFFER_ENABLED 1 452 453 // interrupts 454 #define INTEL_INTERRUPT_ENABLED 0x020a0 455 #define INTEL_INTERRUPT_IDENTITY 0x020a4 456 #define INTEL_INTERRUPT_MASK 0x020a8 457 #define INTEL_INTERRUPT_STATUS 0x020ac 458 #define INTERRUPT_VBLANK_PIPEA (1 << 7) 459 #define INTERRUPT_VBLANK_PIPEB (1 << 5) 460 461 // PCH interrupts 462 #define PCH_INTERRUPT_STATUS 0x44000 463 #define PCH_INTERRUPT_MASK 0x44004 464 #define PCH_INTERRUPT_IDENTITY 0x44008 465 #define PCH_INTERRUPT_ENABLED 0x4400c 466 467 #define PCH_INTERRUPT_VBLANK_PIPEA (1 << 0) 468 #define PCH_INTERRUPT_VBLANK_PIPEB (1 << 5) 469 #define PCH_INTERRUPT_VBLANK_PIPEC (1 << 10) 470 471 // SandyBridge had only two pipes, and things were shuffled aroud again with 472 // the introduction of pipe C. 473 #define PCH_INTERRUPT_VBLANK_PIPEA_SNB (1 << 7) 474 #define PCH_INTERRUPT_VBLANK_PIPEB_SNB (1 << 15) 475 #define PCH_INTERRUPT_GLOBAL_SNB (1 << 31) 476 477 // graphics port control 478 #define DISPLAY_MONITOR_PORT_ENABLED (1UL << 31) 479 #define DISPLAY_MONITOR_PIPE_B (1UL << 30) 480 #define DISPLAY_MONITOR_VGA_POLARITY (1UL << 15) 481 #define DISPLAY_MONITOR_MODE_MASK (3UL << 10) 482 #define DISPLAY_MONITOR_ON 0 483 #define DISPLAY_MONITOR_SUSPEND (1UL << 10) 484 #define DISPLAY_MONITOR_STAND_BY (2UL << 10) 485 #define DISPLAY_MONITOR_OFF (3UL << 10) 486 #define DISPLAY_MONITOR_POLARITY_MASK (3UL << 3) 487 #define DISPLAY_MONITOR_POSITIVE_HSYNC (1UL << 3) 488 #define DISPLAY_MONITOR_POSITIVE_VSYNC (2UL << 3) 489 #define DISPLAY_MONITOR_PORT_DETECTED (1UL << 2) // TMDS/DisplayPort only 490 491 // Cougar Point transcoder pipe selection 492 // (replaces DISPLAY_MONITOR_PIPE_B) 493 #define PORT_TRANS_A_SEL_CPT 0 494 #define PORT_TRANS_B_SEL_CPT (1<<29) 495 #define PORT_TRANS_C_SEL_CPT (2<<29) 496 #define PORT_TRANS_SEL_MASK (3<<29) 497 498 #define LVDS_POST2_RATE_SLOW 14 // PLL Divisors 499 #define LVDS_POST2_RATE_FAST 7 500 #define LVDS_B0B3_POWER_MASK (3UL << 2) 501 #define LVDS_B0B3_POWER_UP (3UL << 2) 502 #define LVDS_CLKB_POWER_MASK (3UL << 4) 503 #define LVDS_CLKB_POWER_UP (3UL << 4) 504 #define LVDS_A3_POWER_MASK (3UL << 6) 505 #define LVDS_A3_POWER_UP (3UL << 6) 506 #define LVDS_A0A2_CLKA_POWER_UP (3UL << 8) 507 #define LVDS_BORDER_ENABLE (1UL << 15) 508 #define LVDS_HSYNC_POLARITY (1UL << 20) 509 #define LVDS_VSYNC_POLARITY (1UL << 21) 510 #define LVDS_18BIT_DITHER (1UL << 25) 511 #define LVDS_PORT_EN (1UL << 31) 512 513 // PLL flags 514 #define DISPLAY_PLL_ENABLED (1UL << 31) 515 #define DISPLAY_PLL_2X_CLOCK (1UL << 30) 516 #define DISPLAY_PLL_SYNC_LOCK_ENABLED (1UL << 29) 517 #define DISPLAY_PLL_NO_VGA_CONTROL (1UL << 28) 518 #define DISPLAY_PLL_MODE_NORMAL (1UL << 26) 519 #define DISPLAY_PLL_MODE_LVDS (2UL << 26) 520 #define DISPLAY_PLL_DIVIDE_HIGH (1UL << 24) 521 #define DISPLAY_PLL_DIVIDE_4X (1UL << 23) 522 #define DISPLAY_PLL_POST1_DIVIDE_2 (1UL << 21) 523 #define DISPLAY_PLL_POST1_DIVISOR_MASK 0x001f0000 524 #define DISPLAY_PLL_9xx_POST1_DIVISOR_MASK 0x00ff0000 525 #define DISPLAY_PLL_SNB_FP0_POST1_DIVISOR_MASK 0x000000ff 526 #define DISPLAY_PLL_IGD_POST1_DIVISOR_MASK 0x00ff8000 527 #define DISPLAY_PLL_POST1_DIVISOR_SHIFT 16 528 #define DISPLAY_PLL_SNB_FP0_POST1_DIVISOR_SHIFT 0 529 #define DISPLAY_PLL_IGD_POST1_DIVISOR_SHIFT 15 530 #define DISPLAY_PLL_DIVISOR_1 (1UL << 8) 531 #define DISPLAY_PLL_N_DIVISOR_MASK 0x001f0000 532 #define DISPLAY_PLL_IGD_N_DIVISOR_MASK 0x00ff0000 533 #define DISPLAY_PLL_M1_DIVISOR_MASK 0x00001f00 534 #define DISPLAY_PLL_M2_DIVISOR_MASK 0x0000001f 535 #define DISPLAY_PLL_IGD_M2_DIVISOR_MASK 0x000000ff 536 #define DISPLAY_PLL_N_DIVISOR_SHIFT 16 537 #define DISPLAY_PLL_M1_DIVISOR_SHIFT 8 538 #define DISPLAY_PLL_M2_DIVISOR_SHIFT 0 539 #define DISPLAY_PLL_PULSE_PHASE_SHIFT 9 540 541 // display 542 543 #define INTEL_DISPLAY_OFFSET 0x1000 544 545 #define INTEL_DISPLAY_A_HTOTAL (0x0000 | REGS_NORTH_PIPE_AND_PORT) 546 #define INTEL_DISPLAY_A_HBLANK (0x0004 | REGS_NORTH_PIPE_AND_PORT) 547 #define INTEL_DISPLAY_A_HSYNC (0x0008 | REGS_NORTH_PIPE_AND_PORT) 548 #define INTEL_DISPLAY_A_VTOTAL (0x000c | REGS_NORTH_PIPE_AND_PORT) 549 #define INTEL_DISPLAY_A_VBLANK (0x0010 | REGS_NORTH_PIPE_AND_PORT) 550 #define INTEL_DISPLAY_A_VSYNC (0x0014 | REGS_NORTH_PIPE_AND_PORT) 551 #define INTEL_DISPLAY_B_HTOTAL (0x1000 | REGS_NORTH_PIPE_AND_PORT) 552 #define INTEL_DISPLAY_B_HBLANK (0x1004 | REGS_NORTH_PIPE_AND_PORT) 553 #define INTEL_DISPLAY_B_HSYNC (0x1008 | REGS_NORTH_PIPE_AND_PORT) 554 #define INTEL_DISPLAY_B_VTOTAL (0x100c | REGS_NORTH_PIPE_AND_PORT) 555 #define INTEL_DISPLAY_B_VBLANK (0x1010 | REGS_NORTH_PIPE_AND_PORT) 556 #define INTEL_DISPLAY_B_VSYNC (0x1014 | REGS_NORTH_PIPE_AND_PORT) 557 558 #define INTEL_DISPLAY_A_PIPE_SIZE (0x001c | REGS_NORTH_PIPE_AND_PORT) 559 #define INTEL_DISPLAY_B_PIPE_SIZE (0x101c | REGS_NORTH_PIPE_AND_PORT) 560 561 // on PCH we also have to set the transcoder 562 #define INTEL_TRANSCODER_A_HTOTAL (0x0000 | REGS_SOUTH_TRANSCODER_PORT) 563 #define INTEL_TRANSCODER_A_HBLANK (0x0004 | REGS_SOUTH_TRANSCODER_PORT) 564 #define INTEL_TRANSCODER_A_HSYNC (0x0008 | REGS_SOUTH_TRANSCODER_PORT) 565 #define INTEL_TRANSCODER_A_VTOTAL (0x000c | REGS_SOUTH_TRANSCODER_PORT) 566 #define INTEL_TRANSCODER_A_VBLANK (0x0010 | REGS_SOUTH_TRANSCODER_PORT) 567 #define INTEL_TRANSCODER_A_VSYNC (0x0014 | REGS_SOUTH_TRANSCODER_PORT) 568 #define INTEL_TRANSCODER_B_HTOTAL (0x1000 | REGS_SOUTH_TRANSCODER_PORT) 569 #define INTEL_TRANSCODER_B_HBLANK (0x1004 | REGS_SOUTH_TRANSCODER_PORT) 570 #define INTEL_TRANSCODER_B_HSYNC (0x1008 | REGS_SOUTH_TRANSCODER_PORT) 571 #define INTEL_TRANSCODER_B_VTOTAL (0x100c | REGS_SOUTH_TRANSCODER_PORT) 572 #define INTEL_TRANSCODER_B_VBLANK (0x1010 | REGS_SOUTH_TRANSCODER_PORT) 573 #define INTEL_TRANSCODER_B_VSYNC (0x1014 | REGS_SOUTH_TRANSCODER_PORT) 574 575 // transcoder M/N DATA AND LINK VALUES (refreshrate) 576 #define INTEL_TRANSCODER_A_DATA_M1 (0x0030 | REGS_SOUTH_TRANSCODER_PORT) 577 #define INTEL_TRANSCODER_A_DATA_M2 (0x0038 | REGS_SOUTH_TRANSCODER_PORT) 578 #define INTEL_TRANSCODER_B_DATA_M1 (0x1030 | REGS_SOUTH_TRANSCODER_PORT) 579 #define INTEL_TRANSCODER_B_DATA_M2 (0x1038 | REGS_SOUTH_TRANSCODER_PORT) 580 #define INTEL_TRANSCODER_C_DATA_M1 (0x2030 | REGS_SOUTH_TRANSCODER_PORT) 581 #define INTEL_TRANSCODER_C_DATA_M2 (0x2038 | REGS_SOUTH_TRANSCODER_PORT) 582 #define INTEL_TRANSCODER_A_DATA_N1 (0x0034 | REGS_SOUTH_TRANSCODER_PORT) 583 #define INTEL_TRANSCODER_A_DATA_N2 (0x003c | REGS_SOUTH_TRANSCODER_PORT) 584 #define INTEL_TRANSCODER_B_DATA_N1 (0x1034 | REGS_SOUTH_TRANSCODER_PORT) 585 #define INTEL_TRANSCODER_B_DATA_N2 (0x103c | REGS_SOUTH_TRANSCODER_PORT) 586 #define INTEL_TRANSCODER_C_DATA_N1 (0x2034 | REGS_SOUTH_TRANSCODER_PORT) 587 #define INTEL_TRANSCODER_C_DATA_N2 (0x203c | REGS_SOUTH_TRANSCODER_PORT) 588 #define INTEL_TRANSCODER_A_LINK_M1 (0x0040 | REGS_SOUTH_TRANSCODER_PORT) 589 #define INTEL_TRANSCODER_A_LINK_M2 (0x0048 | REGS_SOUTH_TRANSCODER_PORT) 590 #define INTEL_TRANSCODER_B_LINK_M1 (0x1040 | REGS_SOUTH_TRANSCODER_PORT) 591 #define INTEL_TRANSCODER_B_LINK_M2 (0x1048 | REGS_SOUTH_TRANSCODER_PORT) 592 #define INTEL_TRANSCODER_C_LINK_M1 (0x2040 | REGS_SOUTH_TRANSCODER_PORT) 593 #define INTEL_TRANSCODER_C_LINK_M2 (0x2048 | REGS_SOUTH_TRANSCODER_PORT) 594 #define INTEL_TRANSCODER_A_LINK_N1 (0x0044 | REGS_SOUTH_TRANSCODER_PORT) 595 #define INTEL_TRANSCODER_A_LINK_N2 (0x004c | REGS_SOUTH_TRANSCODER_PORT) 596 #define INTEL_TRANSCODER_B_LINK_N1 (0x1044 | REGS_SOUTH_TRANSCODER_PORT) 597 #define INTEL_TRANSCODER_B_LINK_N2 (0x104c | REGS_SOUTH_TRANSCODER_PORT) 598 #define INTEL_TRANSCODER_C_LINK_N1 (0x2044 | REGS_SOUTH_TRANSCODER_PORT) 599 #define INTEL_TRANSCODER_C_LINK_N2 (0x204c | REGS_SOUTH_TRANSCODER_PORT) 600 #define INTEL_TRANSCODER_MN_TU_SIZE_MASK (0x3f << 25) 601 #define INTEL_TRANSCODER_MN_VALUE_MASK (0xffffff << 0) 602 603 #define INTEL_TRANSCODER_A_IMAGE_SIZE (0x001c | REGS_SOUTH_TRANSCODER_PORT) 604 #define INTEL_TRANSCODER_B_IMAGE_SIZE (0x101c | REGS_SOUTH_TRANSCODER_PORT) 605 606 // TODO: Is there consolidation that could happen here with digital ports? 607 608 #define INTEL_ANALOG_PORT (0x1100 | REGS_SOUTH_TRANSCODER_PORT) 609 #define INTEL_DIGITAL_PORT_A (0x1120 | REGS_SOUTH_TRANSCODER_PORT) 610 #define INTEL_DIGITAL_PORT_B (0x1140 | REGS_SOUTH_TRANSCODER_PORT) 611 #define INTEL_DIGITAL_PORT_C (0x1160 | REGS_SOUTH_TRANSCODER_PORT) 612 #define INTEL_DIGITAL_LVDS_PORT (0x1180 | REGS_SOUTH_TRANSCODER_PORT) 613 614 #define INTEL_HDMI_PORT_B (0x1140 | REGS_SOUTH_TRANSCODER_PORT) 615 #define INTEL_HDMI_PORT_C (0x1160 | REGS_SOUTH_TRANSCODER_PORT) 616 617 #define PCH_HDMI_PORT_B (0x1140 | REGS_SOUTH_TRANSCODER_PORT) 618 #define PCH_HDMI_PORT_C (0x1150 | REGS_SOUTH_TRANSCODER_PORT) 619 #define PCH_HDMI_PORT_D (0x1160 | REGS_SOUTH_TRANSCODER_PORT) 620 621 #define GEN4_HDMI_PORT_B (0x1140 | REGS_SOUTH_TRANSCODER_PORT) 622 #define GEN4_HDMI_PORT_C (0x1160 | REGS_SOUTH_TRANSCODER_PORT) 623 #define CHV_HDMI_PORT_D (0x116C | REGS_SOUTH_TRANSCODER_PORT) 624 625 // DDI Buffer Control (This replaces DP on Haswell+) 626 #define DDI_BUF_CTL_A (0x4000 | REGS_NORTH_PIPE_AND_PORT) 627 #define DDI_BUF_CTL_B (0x4100 | REGS_NORTH_PIPE_AND_PORT) 628 #define DDI_BUF_CTL_C (0x4200 | REGS_NORTH_PIPE_AND_PORT) 629 #define DDI_BUF_CTL_D (0x4300 | REGS_NORTH_PIPE_AND_PORT) 630 #define DDI_BUF_CTL_E (0x4400 | REGS_NORTH_PIPE_AND_PORT) 631 #define DDI_BUF_CTL_ENABLE (1 << 31) 632 #define DDI_BUF_TRANS_SELECT(n) ((n) << 24) 633 #define DDI_BUF_EMP_MASK (0xf << 24) 634 #define DDI_BUF_PORT_REVERSAL (1 << 16) 635 #define DDI_BUF_IS_IDLE (1 << 7) 636 #define DDI_A_4_LANES (1 << 4) 637 #define DDI_PORT_WIDTH(width) (((width) - 1) << 1) 638 #define DDI_INIT_DISPLAY_DETECTED (1 << 0) 639 640 // DP_A always @ 6xxxx, DP_B-DP_D move with PCH 641 #define INTEL_DISPLAY_PORT_A (0x4000 | REGS_NORTH_PIPE_AND_PORT) 642 #define INTEL_DISPLAY_PORT_B (0x4100 | REGS_SOUTH_TRANSCODER_PORT) 643 #define INTEL_DISPLAY_PORT_C (0x4200 | REGS_SOUTH_TRANSCODER_PORT) 644 #define INTEL_DISPLAY_PORT_D (0x4300 | REGS_SOUTH_TRANSCODER_PORT) 645 646 // Unless you're a damn Valley/CherryView unicorn :-( 647 #define VLV_DISPLAY_PORT_B (VLV_DISPLAY_BASE + 0x64100) 648 #define VLV_DISPLAY_PORT_C (VLV_DISPLAY_BASE + 0x64200) 649 #define CHV_DISPLAY_PORT_D (VLV_DISPLAY_BASE + 0x64300) 650 651 // DP AUX channels 652 #define INTEL_DP_AUX_CTL_A (0x4010 | REGS_NORTH_PIPE_AND_PORT) 653 #define INTEL_DP_AUX_CTL_B (0x4110 | REGS_SOUTH_TRANSCODER_PORT) 654 #define INTEL_DP_AUX_CTL_C (0x4210 | REGS_SOUTH_TRANSCODER_PORT) 655 #define INTEL_DP_AUX_CTL_D (0x4310 | REGS_SOUTH_TRANSCODER_PORT) 656 657 #define VLV_DP_AUX_CTL_B (VLV_DISPLAY_BASE + 0x64110) 658 #define VLV_DP_AUX_CTL_C (VLV_DISPLAY_BASE + 0x64210) 659 #define CHV_DP_AUX_CTL_D (VLV_DISPLAY_BASE + 0x64310) 660 661 #define INTEL_DP_AUX_CTL_BUSY (1 << 31) 662 #define INTEL_DP_AUX_CTL_DONE (1 << 30) 663 #define INTEL_DP_AUX_CTL_INTERRUPT (1 << 29) 664 #define INTEL_DP_AUX_CTL_TIMEOUT_ERROR (1 << 28) 665 #define INTEL_DP_AUX_CTL_TIMEOUT_400us (0 << 26) 666 #define INTEL_DP_AUX_CTL_TIMEOUT_600us (1 << 26) 667 #define INTEL_DP_AUX_CTL_TIMEOUT_800us (2 << 26) 668 #define INTEL_DP_AUX_CTL_TIMEOUT_1600us (3 << 26) 669 #define INTEL_DP_AUX_CTL_TIMEOUT_MASK (3 << 26) 670 #define INTEL_DP_AUX_CTL_RECEIVE_ERROR (1 << 25) 671 #define INTEL_DP_AUX_CTL_MSG_SIZE_MASK (0x1f << 20) 672 #define INTEL_DP_AUX_CTL_MSG_SIZE_SHIFT 20 673 #define INTEL_DP_AUX_CTL_PRECHARGE_2US_MASK (0xf << 16) 674 #define INTEL_DP_AUX_CTL_PRECHARGE_2US_SHIFT 16 675 #define INTEL_DP_AUX_CTL_BIT_CLOCK_2X_MASK (0x7ff) 676 #define INTEL_DP_AUX_CTL_BIT_CLOCK_2X_SHIFT 0 677 #define INTEL_DP_AUX_CTL_SYNC_PULSE_SKL(c) ((c) - 1) 678 679 // planes 680 #define INTEL_PIPE_ENABLED (1UL << 31) 681 #define INTEL_PIPE_STATE (1UL << 30) 682 683 #define INTEL_PLANE_OFFSET 0x1000 684 685 #define INTEL_DISPLAY_A_PIPE_CONTROL (0x0008 | REGS_NORTH_PLANE_CONTROL) 686 #define INTEL_DISPLAY_B_PIPE_CONTROL (0x1008 | REGS_NORTH_PLANE_CONTROL) 687 #define INTEL_DISPLAY_C_PIPE_CONTROL (0x2008 | REGS_NORTH_PLANE_CONTROL) 688 #define INTEL_DISPLAY_A_PIPE_STATUS (0x0024 | REGS_NORTH_PLANE_CONTROL) 689 #define INTEL_DISPLAY_B_PIPE_STATUS (0x1024 | REGS_NORTH_PLANE_CONTROL) 690 691 #define INTEL_DISPLAY_A_PIPE_WATERMARK (0x5100 | REGS_NORTH_PLANE_CONTROL) 692 #define INTEL_DISPLAY_B_PIPE_WATERMARK (0x5104 | REGS_NORTH_PLANE_CONTROL) 693 #define INTEL_DISPLAY_C_PIPE_WATERMARK (0x5200 | REGS_NORTH_PLANE_CONTROL) 694 695 #define DISPLAY_PIPE_VBLANK_ENABLED (1UL << 17) 696 #define DISPLAY_PIPE_VBLANK_STATUS (1UL << 1) 697 698 #define INTEL_DISPLAY_A_CONTROL (0x0180 | REGS_NORTH_PLANE_CONTROL) 699 #define INTEL_DISPLAY_A_BASE (0x0184 | REGS_NORTH_PLANE_CONTROL) 700 #define INTEL_DISPLAY_A_BYTES_PER_ROW (0x0188 | REGS_NORTH_PLANE_CONTROL) 701 #define INTEL_DISPLAY_A_POS (0x018c | REGS_NORTH_PLANE_CONTROL) 702 // reserved on A 703 #define INTEL_DISPLAY_A_IMAGE_SIZE (0x0190 | REGS_NORTH_PLANE_CONTROL) 704 #define INTEL_DISPLAY_A_SURFACE (0x019c | REGS_NORTH_PLANE_CONTROL) 705 // i965 and up only 706 707 #define INTEL_DISPLAY_B_CONTROL (0x1180 | REGS_NORTH_PLANE_CONTROL) 708 #define INTEL_DISPLAY_B_BASE (0x1184 | REGS_NORTH_PLANE_CONTROL) 709 #define INTEL_DISPLAY_B_BYTES_PER_ROW (0x1188 | REGS_NORTH_PLANE_CONTROL) 710 #define INTEL_DISPLAY_B_POS (0x118c | REGS_NORTH_PLANE_CONTROL) 711 #define INTEL_DISPLAY_B_IMAGE_SIZE (0x1190 | REGS_NORTH_PLANE_CONTROL) 712 #define INTEL_DISPLAY_B_SURFACE (0x119c | REGS_NORTH_PLANE_CONTROL) 713 // i965 and up only 714 715 // INTEL_DISPLAY_A_CONTROL source pixel format 716 #define DISPLAY_CONTROL_ENABLED (1UL << 31) 717 #define DISPLAY_CONTROL_GAMMA (1UL << 30) 718 #define DISPLAY_CONTROL_COLOR_MASK (0x0fUL << 26) 719 #define DISPLAY_CONTROL_CMAP8 (2UL << 26) 720 #define DISPLAY_CONTROL_RGB15 (4UL << 26) 721 #define DISPLAY_CONTROL_RGB16 (5UL << 26) 722 #define DISPLAY_CONTROL_RGB32 (6UL << 26) 723 724 // INTEL_DISPLAY_A_PIPE_CONTROL ILK+ 725 #define INTEL_PIPE_DITHER_TYPE_MASK (0x0000000c) 726 #define INTEL_PIPE_DITHER_TYPE_SP (0 << 2) 727 #define INTEL_PIPE_DITHER_TYPE_ST1 (1 << 2) 728 #define INTEL_PIPE_DITHER_TYPE_ST2 (2 << 2) 729 #define INTEL_PIPE_DITHER_TYPE_TEMP (3 << 2) 730 #define INTEL_PIPE_DITHER_EN (1 << 4) 731 #define INTEL_PIPE_COLOR_SHIFT 5 732 #define INTEL_PIPE_BPC(x) ((x) << INTEL_PIPE_COLOR_SHIFT) 733 #define INTEL_PIPE_BPC_MASK (7 << INTEL_PIPE_COLOR_SHIFT) 734 #define INTEL_PIPE_8BPC 0 735 #define INTEL_PIPE_10BPC 1 736 #define INTEL_PIPE_6BPC 2 737 #define INTEL_PIPE_12BPC 3 738 #define INTEL_PIPE_PROGRESSIVE (0 << 21) 739 740 // cursors 741 #define INTEL_CURSOR_CONTROL (0x0080 | REGS_NORTH_PLANE_CONTROL) 742 #define INTEL_CURSOR_BASE (0x0084 | REGS_NORTH_PLANE_CONTROL) 743 #define INTEL_CURSOR_POSITION (0x0088 | REGS_NORTH_PLANE_CONTROL) 744 #define INTEL_CURSOR_PALETTE (0x0090 | REGS_NORTH_PLANE_CONTROL) 745 // (- 0x009f) 746 #define INTEL_CURSOR_SIZE (0x00a0 | REGS_NORTH_PLANE_CONTROL) 747 #define CURSOR_ENABLED (1UL << 31) 748 #define CURSOR_FORMAT_2_COLORS (0UL << 24) 749 #define CURSOR_FORMAT_3_COLORS (1UL << 24) 750 #define CURSOR_FORMAT_4_COLORS (2UL << 24) 751 #define CURSOR_FORMAT_ARGB (4UL << 24) 752 #define CURSOR_FORMAT_XRGB (5UL << 24) 753 #define CURSOR_POSITION_NEGATIVE 0x8000 754 #define CURSOR_POSITION_MASK 0x3fff 755 756 // palette registers 757 #define INTEL_DISPLAY_A_PALETTE (0xa000 | REGS_NORTH_SHARED) 758 #define INTEL_DISPLAY_B_PALETTE (0xa800 | REGS_NORTH_SHARED) 759 760 // Ironlake PCH reference clk control 761 #define PCH_DREF_CONTROL (0x6200 | REGS_SOUTH_SHARED) 762 #define DREF_CONTROL_MASK 0x7fc3 763 #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0 << 13) 764 #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2 << 13) 765 #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3 << 13) 766 #define DREF_CPU_SOURCE_OUTPUT_MASK (3 << 13) 767 #define DREF_SSC_SOURCE_DISABLE (0 << 11) 768 #define DREF_SSC_SOURCE_ENABLE (2 << 11) 769 #define DREF_SSC_SOURCE_MASK (3 << 11) 770 #define DREF_NONSPREAD_SOURCE_DISABLE (0 << 9) 771 #define DREF_NONSPREAD_CK505_ENABLE (1 << 9) 772 #define DREF_NONSPREAD_SOURCE_ENABLE (2 << 9) 773 #define DREF_NONSPREAD_SOURCE_MASK (3 << 9) 774 #define DREF_SUPERSPREAD_SOURCE_DISABLE (0 << 7) 775 #define DREF_SUPERSPREAD_SOURCE_ENABLE (2 << 7) 776 #define DREF_SUPERSPREAD_SOURCE_MASK (3 << 7) 777 #define DREF_SSC4_DOWNSPREAD (0 << 6) 778 #define DREF_SSC4_CENTERSPREAD (1 << 6) 779 #define DREF_SSC1_DISABLE (0 << 1) 780 #define DREF_SSC1_ENABLE (1 << 1) 781 #define DREF_SSC4_DISABLE (0 << 0) 782 #define DREF_SSC4_ENABLE (1 << 0) 783 784 // PLL registers 785 // Multiplier Divisor 786 #define INTEL_DISPLAY_A_PLL (0x6014 | REGS_SOUTH_SHARED) 787 #define INTEL_DISPLAY_B_PLL (0x6018 | REGS_SOUTH_SHARED) 788 #define INTEL_DISPLAY_A_PLL_MD (0x601C | REGS_SOUTH_SHARED) 789 #define INTEL_DISPLAY_B_PLL_MD (0x6020 | REGS_SOUTH_SHARED) 790 #define CHV_DISPLAY_C_PLL (0x6030 | REGS_SOUTH_SHARED) 791 #define CHV_DISPLAY_B_PLL_MD (0x603C | REGS_SOUTH_SHARED) 792 793 #define INTEL_DISPLAY_A_PLL_DIVISOR_0 (0x6040 | REGS_SOUTH_SHARED) 794 #define INTEL_DISPLAY_A_PLL_DIVISOR_1 (0x6044 | REGS_SOUTH_SHARED) 795 #define INTEL_DISPLAY_B_PLL_DIVISOR_0 (0x6048 | REGS_SOUTH_SHARED) 796 #define INTEL_DISPLAY_B_PLL_DIVISOR_1 (0x604c | REGS_SOUTH_SHARED) 797 798 #define SNB_DPLL_SEL (0x7000 | REGS_SOUTH_SHARED) 799 800 // i2c 801 #define INTEL_I2C_IO_A (0x5010 | REGS_SOUTH_SHARED) 802 #define INTEL_I2C_IO_B (0x5014 | REGS_SOUTH_SHARED) 803 #define INTEL_I2C_IO_C (0x5018 | REGS_SOUTH_SHARED) 804 #define INTEL_I2C_IO_D (0x501c | REGS_SOUTH_SHARED) 805 #define INTEL_I2C_IO_E (0x5020 | REGS_SOUTH_SHARED) 806 #define INTEL_I2C_IO_F (0x5024 | REGS_SOUTH_SHARED) 807 #define INTEL_I2C_IO_G (0x5028 | REGS_SOUTH_SHARED) 808 #define INTEL_I2C_IO_H (0x502c | REGS_SOUTH_SHARED) 809 810 #define I2C_CLOCK_DIRECTION_MASK (1 << 0) 811 #define I2C_CLOCK_DIRECTION_OUT (1 << 1) 812 #define I2C_CLOCK_VALUE_MASK (1 << 2) 813 #define I2C_CLOCK_VALUE_OUT (1 << 3) 814 #define I2C_CLOCK_VALUE_IN (1 << 4) 815 #define I2C_DATA_DIRECTION_MASK (1 << 8) 816 #define I2C_DATA_DIRECTION_OUT (1 << 9) 817 #define I2C_DATA_VALUE_MASK (1 << 10) 818 #define I2C_DATA_VALUE_OUT (1 << 11) 819 #define I2C_DATA_VALUE_IN (1 << 12) 820 #define I2C_RESERVED ((1 << 13) | (1 << 5)) 821 822 // TODO: on IronLake this is in the north shared block at 0x41000 823 #define INTEL_VGA_DISPLAY_CONTROL (0x1400 | REGS_NORTH_PLANE_CONTROL) 824 #define VGA_DISPLAY_DISABLED (1UL << 31) 825 826 // LVDS panel 827 #define INTEL_PANEL_STATUS (0x1200 | REGS_NORTH_PIPE_AND_PORT) 828 #define INTEL_PANEL_CONTROL (0x1204 | REGS_NORTH_PIPE_AND_PORT) 829 #define INTEL_PANEL_FIT_CONTROL (0x1230 | REGS_NORTH_PIPE_AND_PORT) 830 #define INTEL_PANEL_FIT_RATIOS (0x1234 | REGS_NORTH_PIPE_AND_PORT) 831 832 // LVDS on IronLake and up 833 #define PCH_PANEL_STATUS (0x7200 | REGS_SOUTH_SHARED) 834 #define PCH_PANEL_CONTROL (0x7204 | REGS_SOUTH_SHARED) 835 #define PCH_PANEL_ON_DELAYS (0x7208 | REGS_SOUTH_SHARED) 836 #define PCH_PANEL_OFF_DELAYS (0x720c | REGS_SOUTH_SHARED) 837 #define PCH_PANEL_DIVISOR (0x7210 | REGS_SOUTH_SHARED) 838 #define PCH_LVDS_DETECTED (1 << 1) 839 840 #define PANEL_STATUS_POWER_ON (1UL << 31) 841 #define PANEL_CONTROL_POWER_TARGET_OFF (0UL << 0) 842 #define PANEL_CONTROL_POWER_TARGET_ON (1UL << 0) 843 #define PANEL_CONTROL_POWER_TARGET_RST (1UL << 1) 844 #define PANEL_REGISTER_UNLOCK (0xabcd << 16) 845 846 // PCH_PANEL_ON_DELAYS 847 #define PANEL_DELAY_PORT_SELECT_MASK (3 << 30) 848 #define PANEL_DELAY_PORT_SELECT_LVDS (0 << 30) 849 #define PANEL_DELAY_PORT_SELECT_DPA (1 << 30) 850 #define PANEL_DELAY_PORT_SELECT_DPC (2 << 30) 851 #define PANEL_DELAY_PORT_SELECT_DPD (3 << 30) 852 853 // PCH_PANEL_DIVISOR 854 #define PANEL_DIVISOR_REFERENCE_DIV_MASK 0xffffff00 855 #define PANEL_DIVISOR_REFERENCE_DIV_SHIFT 8 856 #define PANEL_DIVISOR_POW_CYCLE_DLY_MASK 0x1f 857 #define PANEL_DIVISOR_POW_CYCLE_DLY_SHIFT 0x1f 858 859 // Backlight control registers 860 #define PCH_BLC_PWM_CTL2 (0x8250 | REGS_NORTH_SHARED) 861 #define PCH_BLC_PWM_CTL (0x8254 | REGS_NORTH_SHARED) 862 #define PCH_SBLC_PWM_CTL2 (0x8254 | REGS_SOUTH_SHARED) 863 864 #define MCH_BLC_PWM_CTL (0x1254 | REGS_NORTH_PIPE_AND_PORT) 865 866 // ring buffer commands 867 868 #define COMMAND_NOOP 0x00 869 #define COMMAND_WAIT_FOR_EVENT (0x03 << 23) 870 #define COMMAND_WAIT_FOR_OVERLAY_FLIP (1 << 16) 871 872 #define COMMAND_FLUSH (0x04 << 23) 873 874 // overlay flip 875 #define COMMAND_OVERLAY_FLIP (0x11 << 23) 876 #define COMMAND_OVERLAY_CONTINUE (0 << 21) 877 #define COMMAND_OVERLAY_ON (1 << 21) 878 #define COMMAND_OVERLAY_OFF (2 << 21) 879 #define OVERLAY_UPDATE_COEFFICIENTS 0x1 880 881 // 2D acceleration 882 #define XY_COMMAND_SOURCE_BLIT 0x54c00006 883 #define XY_COMMAND_COLOR_BLIT 0x54000004 884 #define XY_COMMAND_SETUP_MONO_PATTERN 0x44400007 885 #define XY_COMMAND_SCANLINE_BLIT 0x49400001 886 #define COMMAND_COLOR_BLIT 0x50000003 887 #define COMMAND_BLIT_RGBA 0x00300000 888 889 #define COMMAND_MODE_SOLID_PATTERN 0x80 890 #define COMMAND_MODE_CMAP8 0x00 891 #define COMMAND_MODE_RGB15 0x02 892 #define COMMAND_MODE_RGB16 0x01 893 #define COMMAND_MODE_RGB32 0x03 894 895 // overlay 896 #define INTEL_OVERLAY_UPDATE 0x30000 897 #define INTEL_OVERLAY_TEST 0x30004 898 #define INTEL_OVERLAY_STATUS 0x30008 899 #define INTEL_OVERLAY_EXTENDED_STATUS 0x3000c 900 #define INTEL_OVERLAY_GAMMA_5 0x30010 901 #define INTEL_OVERLAY_GAMMA_4 0x30014 902 #define INTEL_OVERLAY_GAMMA_3 0x30018 903 #define INTEL_OVERLAY_GAMMA_2 0x3001c 904 #define INTEL_OVERLAY_GAMMA_1 0x30020 905 #define INTEL_OVERLAY_GAMMA_0 0x30024 906 907 // FDI - Flexible Display Interface, the interface between the (CPU-internal) 908 // GPU and the PCH display outputs. Proprietary interface, based on DisplayPort 909 // though, so similar link training and all... 910 // There's an FDI transmitter (TX) on the CPU and an FDI receiver (RX) on the 911 // PCH for each display pipe. 912 // FDI receiver A is hooked up to transcoder A, FDI receiver B is hooked up to 913 // transcoder B, so we have the same mapping as with the display pipes. 914 #define PCH_FDI_RX_BASE_REGISTER 0xf0000 915 #define PCH_FDI_RX_PIPE_OFFSET 0x01000 916 #define PCH_FDI_RX_CONTROL 0x00c 917 #define PCH_FDI_RX_MISC 0x010 918 #define PCH_FDI_RX_IIR 0x014 919 #define PCH_FDI_RX_IMR 0x018 920 921 #define FDI_RX_ENABLE (1 << 31) 922 #define FDI_RX_PLL_ENABLED (1 << 13) 923 924 #define FDI_RX_LINK_COLOR_SHIFT 16 925 #define FDI_RX_LINK_BPC(x) ((x) << FDI_RX_LINK_COLOR_SHIFT) 926 #define FDI_RX_LINK_BPC_MASK (7 << FDI_RX_LINK_COLOR_SHIFT) 927 928 // Transcoder - same base as FDI_RX 929 #define PCH_TRANS_CONF_A 0x0008 930 #define PCH_TRANS_CONF_B 0x1008 931 #define PCH_TRANS_CONF_C 0x2008 932 933 #define TRANS_ENABLE (1 << 31) 934 #define TRANS_ENABLED (1 << 30) 935 936 // FDI_tX interrupt register 937 #define FDI_RX_INTER_LANE_ALIGN (1 << 10) 938 #define FDI_RX_SYMBOL_LOCK (1 << 9) 939 #define FDI_RX_BIT_LOCK (1 << 8) 940 #define FDI_RX_TRAIN_PATTERN_2_FAIL (1 << 7) 941 #define FDI_RX_FS_CODE_ERR (1 << 6) 942 #define FDI_RX_FE_CODE_ERR (1 << 5) 943 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1 << 4) 944 #define FDI_RX_HDCP_LINK_FAIL (1 << 3) 945 #define FDI_RX_PIXEL_FIFO_OVERFLOW (1 << 2) 946 #define FDI_RX_CROSS_CLOCK_OVERFLOW (1 << 1) 947 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1 << 0) 948 949 #define FDI_FS_ERRC_ENABLE (1 << 27) 950 #define FDI_FE_ERRC_ENABLE (1 << 26) 951 952 #define PCH_FDI_RX_TRANS_UNIT_SIZE_1 0x30 953 #define PCH_FDI_RX_TRANS_UNIT_SIZE_2 0x38 954 #define FDI_RX_TRANS_UNIT_SIZE(x) ((x - 1) << 25) 955 #define FDI_RX_TRANS_UNIT_MASK 0x7e000000 956 957 #define FDI_RX_ENHANCE_FRAME_ENABLE (1 << 6) 958 #define FDI_RX_CLOCK_MASK (1 << 4) 959 #define FDI_RX_CLOCK_RAW (0 << 4) 960 #define FDI_RX_CLOCK_PCD (1 << 4) 961 962 // FDI RX MISC 963 #define FDI_RX_PWRDN_LANE1_MASK (3 << 26) 964 #define FDI_RX_PWRDN_LANE1_VAL(x) ((x) << 26) 965 #define FDI_RX_PWRDN_LANE0_MASK (3 << 24) 966 #define FDI_RX_PWRDN_LANE0_VAL(x) ((x) << 24) 967 #define FDI_RX_TP1_TO_TP2_48 (2 << 20) 968 #define FDI_RX_TP1_TO_TP2_64 (3 << 20) 969 #define FDI_RX_FDI_DELAY_90 (0x90 << 0) 970 971 #define PCH_FDI_TX_BASE_REGISTER 0x60000 972 #define PCH_FDI_TX_PIPE_OFFSET 0x01000 973 #define PCH_FDI_TX_CONTROL 0x100 974 #define FDI_TX_ENABLE (1 << 31) 975 #define FDI_LINK_TRAIN_PATTERN_1 (0 << 28) 976 #define FDI_LINK_TRAIN_PATTERN_2 (1 << 28) 977 #define FDI_LINK_TRAIN_PATTERN_IDLE (2 << 28) 978 #define FDI_LINK_TRAIN_NONE (3 << 28) 979 #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0 << 25) 980 #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1 << 25) 981 #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2 << 25) 982 #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3 << 25) 983 #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0 << 22) 984 #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1 << 22) 985 #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2 << 22) 986 #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3 << 22) 987 988 //FDI PIPE M/N DATA AND LINK VALUES (refreshrate) 989 #define PCH_FDI_PIPE_A_DATA_M1 0x0030 990 #define PCH_FDI_PIPE_A_DATA_M2 0x0038 991 #define PCH_FDI_PIPE_B_DATA_M1 0x1030 992 #define PCH_FDI_PIPE_B_DATA_M2 0x1038 993 #define PCH_FDI_PIPE_C_DATA_M1 0x2030 994 #define PCH_FDI_PIPE_C_DATA_M2 0x2038 995 #define PCH_FDI_PIPE_A_DATA_N1 0x0034 996 #define PCH_FDI_PIPE_A_DATA_N2 0x003c 997 #define PCH_FDI_PIPE_B_DATA_N1 0x1034 998 #define PCH_FDI_PIPE_B_DATA_N2 0x103c 999 #define PCH_FDI_PIPE_C_DATA_N1 0x2034 1000 #define PCH_FDI_PIPE_C_DATA_N2 0x203c 1001 #define PCH_FDI_PIPE_A_LINK_M1 0x0040 1002 #define PCH_FDI_PIPE_A_LINK_M2 0x0048 1003 #define PCH_FDI_PIPE_B_LINK_M1 0x1040 1004 #define PCH_FDI_PIPE_B_LINK_M2 0x1048 1005 #define PCH_FDI_PIPE_C_LINK_M1 0x2040 1006 #define PCH_FDI_PIPE_C_LINK_M2 0x2048 1007 #define PCH_FDI_PIPE_A_LINK_N1 0x0044 1008 #define PCH_FDI_PIPE_A_LINK_N2 0x004c 1009 #define PCH_FDI_PIPE_B_LINK_N1 0x1044 1010 #define PCH_FDI_PIPE_B_LINK_N2 0x104c 1011 #define PCH_FDI_PIPE_C_LINK_N1 0x2044 1012 #define PCH_FDI_PIPE_C_LINK_N2 0x204c 1013 #define FDI_PIPE_MN_TU_SIZE_MASK (0x3f << 25) 1014 #define FDI_PIPE_MN_VALUE_MASK (0xffffff << 0) 1015 1016 // SNB A stepping 1017 #define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22) 1018 #define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22) 1019 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22) 1020 #define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x00 << 22) 1021 1022 // SNB B stepping 1023 #define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x00 << 22) 1024 #define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a << 22) 1025 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39 << 22) 1026 #define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38 << 22) 1027 #define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f << 22) 1028 #define FDI_TX_ENHANCE_FRAME_ENABLE (1 << 18) 1029 #define FDI_TX_PLL_ENABLED (1 << 14) 1030 1031 #define FDI_DP_PORT_WIDTH_SHIFT 19 1032 #define FDI_DP_PORT_WIDTH_MASK (7 << FDI_DP_PORT_WIDTH_SHIFT) 1033 #define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT) 1034 1035 #define FDI_PLL_BIOS_0 0x46000 1036 #define FDI_PLL_FB_CLOCK_MASK 0xff 1037 #define FDI_PLL_BIOS_1 0x46004 1038 #define FDI_PLL_BIOS_2 0x46008 1039 1040 #define FDI_AUTO_TRAINING (1 << 10) 1041 #define FDI_AUTO_TRAIN_DONE (1 << 1) 1042 1043 #define FDI_LINK_TRAIN_PATTERN_1_CPT (0 << 8) 1044 #define FDI_LINK_TRAIN_PATTERN_2_CPT (1 << 8) 1045 #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2 << 8) 1046 #define FDI_LINK_TRAIN_NORMAL_CPT (3 << 8) 1047 #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3 << 8) 1048 1049 // IvyBridge changes it up because... they hate developers? 1050 #define FDI_LINK_TRAIN_PATTERN_1_IVB (0 << 8) 1051 #define FDI_LINK_TRAIN_PATTERN_2_IVB (1 << 8) 1052 #define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2 << 8) 1053 #define FDI_LINK_TRAIN_NONE_IVB (3 << 8) 1054 1055 #define PCH_FDI_RXA_CHICKEN (0x200c | REGS_SOUTH_SHARED) 1056 #define PCH_FDI_RXB_CHICKEN (0x2010 | REGS_SOUTH_SHARED) 1057 #define FDI_RX_PHASE_SYNC_POINTER_EN (1 << 0) 1058 #define FDI_RX_PHASE_SYNC_POINTER_OVR (1 << 1) 1059 1060 // CPU Panel Fitters - These are for IronLake and up and are the CPU internal 1061 // panel fitters. 1062 #define PCH_PANEL_FITTER_BASE_REGISTER 0x68000 1063 #define PCH_PANEL_FITTER_PIPE_OFFSET 0x00800 1064 1065 #define PCH_PANEL_FITTER_WINDOW_POS 0x70 1066 #define PCH_PANEL_FITTER_WINDOW_SIZE 0x74 1067 #define PCH_PANEL_FITTER_CONTROL 0x80 1068 //not on IvyBridge: 1069 #define PCH_PANEL_FITTER_V_SCALE 0x84 1070 #define PCH_PANEL_FITTER_H_SCALE 0x90 1071 1072 #define PANEL_FITTER_ENABLED (1 << 31) 1073 #define PANEL_FITTER_PIPE_MASK (3 << 29) 1074 #define PANEL_FITTER_PIPE_A (0 << 29) 1075 #define PANEL_FITTER_PIPE_B (1 << 29) 1076 #define PANEL_FITTER_PIPE_C (2 << 29) 1077 #define PANEL_FITTER_SCALING_MODE_MASK (7 << 26) 1078 #define PANEL_FITTER_FILTER_MASK (3 << 24) 1079 1080 struct overlay_scale { 1081 uint32 _reserved0 : 3; 1082 uint32 horizontal_scale_fraction : 12; 1083 uint32 _reserved1 : 1; 1084 uint32 horizontal_downscale_factor : 3; 1085 uint32 _reserved2 : 1; 1086 uint32 vertical_scale_fraction : 12; 1087 }; 1088 1089 #define OVERLAY_FORMAT_RGB15 0x2 1090 #define OVERLAY_FORMAT_RGB16 0x3 1091 #define OVERLAY_FORMAT_RGB32 0x1 1092 #define OVERLAY_FORMAT_YCbCr422 0x8 1093 #define OVERLAY_FORMAT_YCbCr411 0x9 1094 #define OVERLAY_FORMAT_YCbCr420 0xc 1095 1096 #define OVERLAY_MIRROR_NORMAL 0x0 1097 #define OVERLAY_MIRROR_HORIZONTAL 0x1 1098 #define OVERLAY_MIRROR_VERTICAL 0x2 1099 1100 // The real overlay registers are written to using an update buffer 1101 1102 struct overlay_registers { 1103 uint32 buffer_rgb0; 1104 uint32 buffer_rgb1; 1105 uint32 buffer_u0; 1106 uint32 buffer_v0; 1107 uint32 buffer_u1; 1108 uint32 buffer_v1; 1109 // (0x18) OSTRIDE - overlay stride 1110 uint16 stride_rgb; 1111 uint16 stride_uv; 1112 // (0x1c) YRGB_VPH - Y/RGB vertical phase 1113 uint16 vertical_phase0_rgb; 1114 uint16 vertical_phase1_rgb; 1115 // (0x20) UV_VPH - UV vertical phase 1116 uint16 vertical_phase0_uv; 1117 uint16 vertical_phase1_uv; 1118 // (0x24) HORZ_PH - horizontal phase 1119 uint16 horizontal_phase_rgb; 1120 uint16 horizontal_phase_uv; 1121 // (0x28) INIT_PHS - initial phase shift 1122 uint32 initial_vertical_phase0_shift_rgb0 : 4; 1123 uint32 initial_vertical_phase1_shift_rgb0 : 4; 1124 uint32 initial_horizontal_phase_shift_rgb0 : 4; 1125 uint32 initial_vertical_phase0_shift_uv : 4; 1126 uint32 initial_vertical_phase1_shift_uv : 4; 1127 uint32 initial_horizontal_phase_shift_uv : 4; 1128 uint32 _reserved0 : 8; 1129 // (0x2c) DWINPOS - destination window position 1130 uint16 window_left; 1131 uint16 window_top; 1132 // (0x30) DWINSZ - destination window size 1133 uint16 window_width; 1134 uint16 window_height; 1135 // (0x34) SWIDTH - source width 1136 uint16 source_width_rgb; 1137 uint16 source_width_uv; 1138 // (0x38) SWITDHSW - source width in 8 byte steps 1139 uint16 source_bytes_per_row_rgb; 1140 uint16 source_bytes_per_row_uv; 1141 uint16 source_height_rgb; 1142 uint16 source_height_uv; 1143 overlay_scale scale_rgb; 1144 overlay_scale scale_uv; 1145 // (0x48) OCLRC0 - overlay color correction 0 1146 uint32 brightness_correction : 8; // signed, -128 to 127 1147 uint32 _reserved1 : 10; 1148 uint32 contrast_correction : 9; // fixed point: 3.6 bits 1149 uint32 _reserved2 : 5; 1150 // (0x4c) OCLRC1 - overlay color correction 1 1151 uint32 saturation_cos_correction : 10; // fixed point: 3.7 bits 1152 uint32 _reserved3 : 6; 1153 uint32 saturation_sin_correction : 11; // signed fixed point: 3.7 bits 1154 uint32 _reserved4 : 5; 1155 // (0x50) DCLRKV - destination color key value 1156 uint32 color_key_blue : 8; 1157 uint32 color_key_green : 8; 1158 uint32 color_key_red : 8; 1159 uint32 _reserved5 : 8; 1160 // (0x54) DCLRKM - destination color key mask 1161 uint32 color_key_mask_blue : 8; 1162 uint32 color_key_mask_green : 8; 1163 uint32 color_key_mask_red : 8; 1164 uint32 _reserved6 : 7; 1165 uint32 color_key_enabled : 1; 1166 // (0x58) SCHRKVH - source chroma key high value 1167 uint32 source_chroma_key_high_red : 8; 1168 uint32 source_chroma_key_high_blue : 8; 1169 uint32 source_chroma_key_high_green : 8; 1170 uint32 _reserved7 : 8; 1171 // (0x5c) SCHRKVL - source chroma key low value 1172 uint32 source_chroma_key_low_red : 8; 1173 uint32 source_chroma_key_low_blue : 8; 1174 uint32 source_chroma_key_low_green : 8; 1175 uint32 _reserved8 : 8; 1176 // (0x60) SCHRKEN - source chroma key enable 1177 uint32 _reserved9 : 24; 1178 uint32 source_chroma_key_red_enabled : 1; 1179 uint32 source_chroma_key_blue_enabled : 1; 1180 uint32 source_chroma_key_green_enabled : 1; 1181 uint32 _reserved10 : 5; 1182 // (0x64) OCONFIG - overlay configuration 1183 uint32 _reserved11 : 3; 1184 uint32 color_control_output_mode : 1; 1185 uint32 yuv_to_rgb_bypass : 1; 1186 uint32 _reserved12 : 11; 1187 uint32 gamma2_enabled : 1; 1188 uint32 _reserved13 : 1; 1189 uint32 select_pipe : 1; 1190 uint32 slot_time : 8; 1191 uint32 _reserved14 : 5; 1192 // (0x68) OCOMD - overlay command 1193 uint32 overlay_enabled : 1; 1194 uint32 active_field : 1; 1195 uint32 active_buffer : 2; 1196 uint32 test_mode : 1; 1197 uint32 buffer_field_mode : 1; 1198 uint32 _reserved15 : 1; 1199 uint32 tv_flip_field_enabled : 1; 1200 uint32 _reserved16 : 1; 1201 uint32 tv_flip_field_parity : 1; 1202 uint32 source_format : 4; 1203 uint32 ycbcr422_order : 2; 1204 uint32 _reserved18 : 1; 1205 uint32 mirroring_mode : 2; 1206 uint32 _reserved19 : 13; 1207 1208 uint32 _reserved20; 1209 1210 uint32 start_0y; 1211 uint32 start_1y; 1212 uint32 start_0u; 1213 uint32 start_0v; 1214 uint32 start_1u; 1215 uint32 start_1v; 1216 uint32 _reserved21[6]; 1217 #if 0 1218 // (0x70) AWINPOS - alpha blend window position 1219 uint32 awinpos; 1220 // (0x74) AWINSZ - alpha blend window size 1221 uint32 awinsz; 1222 1223 uint32 _reserved21[10]; 1224 #endif 1225 1226 // (0xa0) FASTHSCALE - fast horizontal downscale (strangely enough, 1227 // the next two registers switch the usual Y/RGB vs. UV order) 1228 uint16 horizontal_scale_uv; 1229 uint16 horizontal_scale_rgb; 1230 // (0xa4) UVSCALEV - vertical downscale 1231 uint16 vertical_scale_uv; 1232 uint16 vertical_scale_rgb; 1233 1234 uint32 _reserved22[86]; 1235 1236 // (0x200) polyphase filter coefficients 1237 uint16 vertical_coefficients_rgb[128]; 1238 uint16 horizontal_coefficients_rgb[128]; 1239 1240 uint32 _reserved23[64]; 1241 1242 // (0x500) 1243 uint16 vertical_coefficients_uv[128]; 1244 uint16 horizontal_coefficients_uv[128]; 1245 }; 1246 1247 // i965 overlay support is currently realized using its 3D hardware 1248 #define INTEL_i965_OVERLAY_STATE_SIZE 36864 1249 #define INTEL_i965_3D_CONTEXT_SIZE 32768 1250 1251 inline bool 1252 intel_uses_physical_overlay(intel_shared_info &info) 1253 { 1254 return !info.device_type.InGroup(INTEL_GROUP_Gxx); 1255 } 1256 1257 1258 struct hardware_status { 1259 uint32 interrupt_status_register; 1260 uint32 _reserved0[3]; 1261 void* primary_ring_head_storage; 1262 uint32 _reserved1[3]; 1263 void* secondary_ring_0_head_storage; 1264 void* secondary_ring_1_head_storage; 1265 uint32 _reserved2[2]; 1266 void* binning_head_storage; 1267 uint32 _reserved3[3]; 1268 uint32 store[1008]; 1269 }; 1270 1271 #endif /* INTEL_EXTREME_H */ 1272