1 /* 2 * Copyright 2006-2009, Haiku, Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Axel Dörfler, axeld@pinc-software.de 7 */ 8 #ifndef INTEL_EXTREME_H 9 #define INTEL_EXTREME_H 10 11 12 #include "lock.h" 13 14 #include <Accelerant.h> 15 #include <Drivers.h> 16 #include <PCI.h> 17 18 19 #define VENDOR_ID_INTEL 0x8086 20 21 #define INTEL_TYPE_FAMILY_MASK 0xf000 22 #define INTEL_TYPE_GROUP_MASK 0xfff0 23 #define INTEL_TYPE_MODEL_MASK 0xffff 24 // families 25 #define INTEL_TYPE_7xx 0x1000 26 #define INTEL_TYPE_8xx 0x2000 27 #define INTEL_TYPE_9xx 0x4000 28 // groups 29 #define INTEL_TYPE_83x (INTEL_TYPE_8xx | 0x0010) 30 #define INTEL_TYPE_85x (INTEL_TYPE_8xx | 0x0020) 31 #define INTEL_TYPE_91x (INTEL_TYPE_9xx | 0x0040) 32 #define INTEL_TYPE_94x (INTEL_TYPE_9xx | 0x0080) 33 #define INTEL_TYPE_96x (INTEL_TYPE_9xx | 0x0100) 34 #define INTEL_TYPE_Gxx (INTEL_TYPE_9xx | 0x0200) 35 #define INTEL_TYPE_G4x (INTEL_TYPE_9xx | 0x0400) 36 #define INTEL_TYPE_IGD (INTEL_TYPE_9xx | 0x0800) 37 // models 38 #define INTEL_TYPE_MOBILE 0x0008 39 #define INTEL_TYPE_915 (INTEL_TYPE_91x) 40 #define INTEL_TYPE_945 (INTEL_TYPE_94x) 41 #define INTEL_TYPE_945M (INTEL_TYPE_94x | INTEL_TYPE_MOBILE) 42 #define INTEL_TYPE_965 (INTEL_TYPE_96x) 43 #define INTEL_TYPE_965M (INTEL_TYPE_96x | INTEL_TYPE_MOBILE) 44 #define INTEL_TYPE_G33 (INTEL_TYPE_Gxx) 45 #define INTEL_TYPE_G45 (INTEL_TYPE_G4x) 46 #define INTEL_TYPE_GM45 (INTEL_TYPE_G4x | INTEL_TYPE_MOBILE) 47 #define INTEL_TYPE_IGDG (INTEL_TYPE_IGD) 48 #define INTEL_TYPE_IGDGM (INTEL_TYPE_IGD | INTEL_TYPE_MOBILE) 49 50 #define DEVICE_NAME "intel_extreme" 51 #define INTEL_ACCELERANT_NAME "intel_extreme.accelerant" 52 53 struct DeviceType { 54 uint32 type; 55 56 DeviceType(int t) 57 { 58 type = t; 59 } 60 61 DeviceType& operator=(int t) 62 { 63 type = t; 64 return *this; 65 } 66 67 bool InFamily(uint32 family) const 68 { 69 return (type & INTEL_TYPE_FAMILY_MASK) == family; 70 } 71 72 bool InGroup(uint32 group) const 73 { 74 return (type & INTEL_TYPE_GROUP_MASK) == group; 75 } 76 77 bool IsModel(uint32 model) const 78 { 79 return (type & INTEL_TYPE_MODEL_MASK) == model; 80 } 81 }; 82 83 // info about PLL on graphics card 84 struct pll_info { 85 uint32 reference_frequency; 86 uint32 max_frequency; 87 uint32 min_frequency; 88 uint32 divisor_register; 89 }; 90 91 struct ring_buffer { 92 struct lock lock; 93 uint32 register_base; 94 uint32 offset; 95 uint32 size; 96 uint32 position; 97 uint32 space_left; 98 uint8* base; 99 }; 100 101 struct overlay_registers; 102 103 struct intel_shared_info { 104 area_id mode_list_area; // area containing display mode list 105 uint32 mode_count; 106 107 display_mode current_mode; 108 uint32 bytes_per_row; 109 uint32 bits_per_pixel; 110 uint32 dpms_mode; 111 112 area_id registers_area; // area of memory mapped registers 113 uint8* status_page; 114 phys_addr_t physical_status_page; 115 uint8* graphics_memory; 116 phys_addr_t physical_graphics_memory; 117 uint32 graphics_memory_size; 118 119 addr_t frame_buffer; 120 uint32 frame_buffer_offset; 121 122 struct lock accelerant_lock; 123 struct lock engine_lock; 124 125 ring_buffer primary_ring_buffer; 126 127 int32 overlay_channel_used; 128 bool overlay_active; 129 uint32 overlay_token; 130 phys_addr_t physical_overlay_registers; 131 uint32 overlay_offset; 132 133 bool hardware_cursor_enabled; 134 sem_id vblank_sem; 135 136 uint8* cursor_memory; 137 phys_addr_t physical_cursor_memory; 138 uint32 cursor_buffer_offset; 139 uint32 cursor_format; 140 bool cursor_visible; 141 uint16 cursor_hot_x; 142 uint16 cursor_hot_y; 143 144 DeviceType device_type; 145 char device_identifier[32]; 146 struct pll_info pll_info; 147 }; 148 149 //----------------- ioctl() interface ---------------- 150 151 // magic code for ioctls 152 #define INTEL_PRIVATE_DATA_MAGIC 'itic' 153 154 // list ioctls 155 enum { 156 INTEL_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1, 157 158 INTEL_GET_DEVICE_NAME, 159 INTEL_ALLOCATE_GRAPHICS_MEMORY, 160 INTEL_FREE_GRAPHICS_MEMORY 161 }; 162 163 // retrieve the area_id of the kernel/accelerant shared info 164 struct intel_get_private_data { 165 uint32 magic; // magic number 166 area_id shared_info_area; 167 }; 168 169 // allocate graphics memory 170 struct intel_allocate_graphics_memory { 171 uint32 magic; 172 uint32 size; 173 uint32 alignment; 174 uint32 flags; 175 uint32 buffer_base; 176 }; 177 178 // free graphics memory 179 struct intel_free_graphics_memory { 180 uint32 magic; 181 uint32 buffer_base; 182 }; 183 184 //---------------------------------------------------------- 185 // Register definitions, taken from X driver 186 187 // PCI bridge memory management 188 #define INTEL_GRAPHICS_MEMORY_CONTROL 0x52 // GGC - (G)MCH Graphics Control Register 189 #define MEMORY_CONTROL_ENABLED 0x0004 190 #define MEMORY_MASK 0x0001 191 #define STOLEN_MEMORY_MASK 0x00f0 192 #define i965_GTT_MASK 0x000e 193 #define G33_GTT_MASK 0x0300 194 #define G4X_GTT_MASK 0x0f00 // GGMS (GSM Memory Size) mask 195 196 // models i830 and up 197 #define i830_LOCAL_MEMORY_ONLY 0x10 198 #define i830_STOLEN_512K 0x20 199 #define i830_STOLEN_1M 0x30 200 #define i830_STOLEN_8M 0x40 201 #define i830_FRAME_BUFFER_64M 0x01 202 #define i830_FRAME_BUFFER_128M 0x00 203 204 // models i855 and up 205 #define i855_STOLEN_MEMORY_1M 0x10 206 #define i855_STOLEN_MEMORY_4M 0x20 207 #define i855_STOLEN_MEMORY_8M 0x30 208 #define i855_STOLEN_MEMORY_16M 0x40 209 #define i855_STOLEN_MEMORY_32M 0x50 210 #define i855_STOLEN_MEMORY_48M 0x60 211 #define i855_STOLEN_MEMORY_64M 0x70 212 #define i855_STOLEN_MEMORY_128M 0x80 213 #define i855_STOLEN_MEMORY_256M 0x90 214 215 #define G4X_STOLEN_MEMORY_96MB 0xa0 // GMS - Graphics Mode Select 216 #define G4X_STOLEN_MEMORY_160MB 0xb0 217 #define G4X_STOLEN_MEMORY_224MB 0xc0 218 #define G4X_STOLEN_MEMORY_352MB 0xd0 219 220 221 // graphics page translation table 222 #define INTEL_PAGE_TABLE_CONTROL 0x02020 223 #define PAGE_TABLE_ENABLED 0x00000001 224 #define INTEL_PAGE_TABLE_ERROR 0x02024 225 #define INTEL_HARDWARE_STATUS_PAGE 0x02080 226 #define i915_GTT_BASE 0x1c 227 #define i830_GTT_BASE 0x10000 // (- 0x2ffff) 228 #define i830_GTT_SIZE 0x20000 229 #define i965_GTT_BASE 0x80000 // (- 0xfffff) 230 #define i965_GTT_SIZE 0x80000 231 #define i965_GTT_128K (2 << 1) 232 #define i965_GTT_256K (1 << 1) 233 #define i965_GTT_512K (0 << 1) 234 #define G33_GTT_1M (1 << 8) 235 #define G33_GTT_2M (2 << 8) 236 #define G4X_GTT_NONE 0x000 // GGMS - GSM Memory Size 237 #define G4X_GTT_1M_NO_IVT 0x100 // no Intel Virtualization Tech. 238 #define G4X_GTT_2M_NO_IVT 0x300 239 #define G4X_GTT_2M_IVT 0x900 // with Intel Virt. Tech. 240 #define G4X_GTT_3M_IVT 0xa00 241 #define G4X_GTT_4M_IVT 0xb00 242 243 244 #define GTT_ENTRY_VALID 0x01 245 #define GTT_ENTRY_LOCAL_MEMORY 0x02 246 #define GTT_PAGE_SHIFT 12 247 248 // interrupts 249 #define INTEL_INTERRUPT_ENABLED 0x020a0 250 #define INTEL_INTERRUPT_IDENTITY 0x020a4 251 #define INTEL_INTERRUPT_MASK 0x020a8 252 #define INTEL_INTERRUPT_STATUS 0x020ac 253 #define INTERRUPT_VBLANK_PIPEA (1 << 7) 254 #define INTERRUPT_VBLANK_PIPEB (1 << 5) 255 256 // ring buffer 257 #define INTEL_PRIMARY_RING_BUFFER 0x02030 258 #define INTEL_SECONDARY_RING_BUFFER_0 0x02100 259 #define INTEL_SECONDARY_RING_BUFFER_1 0x02110 260 // offsets for the ring buffer base registers above 261 #define RING_BUFFER_TAIL 0x0 262 #define RING_BUFFER_HEAD 0x4 263 #define RING_BUFFER_START 0x8 264 #define RING_BUFFER_CONTROL 0xc 265 #define INTEL_RING_BUFFER_SIZE_MASK 0x001ff000 266 #define INTEL_RING_BUFFER_HEAD_MASK 0x001ffffc 267 #define INTEL_RING_BUFFER_ENABLED 1 268 269 // display ports 270 #define INTEL_DISPLAY_A_ANALOG_PORT 0x61100 271 #define DISPLAY_MONITOR_PORT_ENABLED (1UL << 31) 272 #define DISPLAY_MONITOR_PIPE_B (1UL << 30) 273 #define DISPLAY_MONITOR_VGA_POLARITY (1UL << 15) 274 #define DISPLAY_MONITOR_MODE_MASK (3UL << 10) 275 #define DISPLAY_MONITOR_ON 0 276 #define DISPLAY_MONITOR_SUSPEND (1UL << 10) 277 #define DISPLAY_MONITOR_STAND_BY (2UL << 10) 278 #define DISPLAY_MONITOR_OFF (3UL << 10) 279 #define DISPLAY_MONITOR_POLARITY_MASK (3UL << 3) 280 #define DISPLAY_MONITOR_POSITIVE_HSYNC (1UL << 3) 281 #define DISPLAY_MONITOR_POSITIVE_VSYNC (2UL << 3) 282 #define INTEL_DISPLAY_A_DIGITAL_PORT 0x61120 283 #define INTEL_DISPLAY_C_DIGITAL 0x61160 284 #define INTEL_DISPLAY_LVDS_PORT 0x61180 285 #define LVDS_POST2_RATE_SLOW 14 // PLL Divisors 286 #define LVDS_POST2_RATE_FAST 7 287 #define LVDS_CLKB_POWER_MASK (3 << 4) 288 #define LVDS_CLKB_POWER_UP (3 << 4) 289 #define LVDS_PORT_EN (1 << 31) 290 #define LVDS_A0A2_CLKA_POWER_UP (3 << 8) 291 #define LVDS_PIPEB_SELECT (1 << 30) 292 #define LVDS_B0B3PAIRS_POWER_UP (3 << 2) 293 #define LVDS_PLL_MODE_LVDS (2 << 26) 294 #define LVDS_18BIT_DITHER (1 << 25) 295 296 // PLL flags 297 #define DISPLAY_PLL_ENABLED (1UL << 31) 298 #define DISPLAY_PLL_2X_CLOCK (1UL << 30) 299 #define DISPLAY_PLL_SYNC_LOCK_ENABLED (1UL << 29) 300 #define DISPLAY_PLL_NO_VGA_CONTROL (1UL << 28) 301 #define DISPLAY_PLL_MODE_ANALOG (1UL << 26) 302 #define DISPLAY_PLL_DIVIDE_HIGH (1UL << 24) 303 #define DISPLAY_PLL_DIVIDE_4X (1UL << 23) 304 #define DISPLAY_PLL_POST1_DIVIDE_2 (1UL << 21) 305 #define DISPLAY_PLL_POST1_DIVISOR_MASK 0x001f0000 306 #define DISPLAY_PLL_9xx_POST1_DIVISOR_MASK 0x00ff0000 307 #define DISPLAY_PLL_IGD_POST1_DIVISOR_MASK 0x00ff8000 308 #define DISPLAY_PLL_POST1_DIVISOR_SHIFT 16 309 #define DISPLAY_PLL_IGD_POST1_DIVISOR_SHIFT 15 310 #define DISPLAY_PLL_DIVISOR_1 (1UL << 8) 311 #define DISPLAY_PLL_N_DIVISOR_MASK 0x001f0000 312 #define DISPLAY_PLL_IGD_N_DIVISOR_MASK 0x00ff0000 313 #define DISPLAY_PLL_M1_DIVISOR_MASK 0x00001f00 314 #define DISPLAY_PLL_M2_DIVISOR_MASK 0x0000001f 315 #define DISPLAY_PLL_IGD_M2_DIVISOR_MASK 0x000000ff 316 #define DISPLAY_PLL_N_DIVISOR_SHIFT 16 317 #define DISPLAY_PLL_M1_DIVISOR_SHIFT 8 318 #define DISPLAY_PLL_M2_DIVISOR_SHIFT 0 319 #define DISPLAY_PLL_PULSE_PHASE_SHIFT 9 320 321 // display A 322 #define INTEL_DISPLAY_A_HTOTAL 0x60000 323 #define INTEL_DISPLAY_A_HBLANK 0x60004 324 #define INTEL_DISPLAY_A_HSYNC 0x60008 325 #define INTEL_DISPLAY_A_VTOTAL 0x6000c 326 #define INTEL_DISPLAY_A_VBLANK 0x60010 327 #define INTEL_DISPLAY_A_VSYNC 0x60014 328 #define INTEL_DISPLAY_A_IMAGE_SIZE 0x6001c 329 330 #define INTEL_DISPLAY_A_CONTROL 0x70180 331 #define INTEL_DISPLAY_A_BASE 0x70184 332 #define INTEL_DISPLAY_A_BYTES_PER_ROW 0x70188 333 #define INTEL_DISPLAY_A_SURFACE 0x7019c // i965 and up only 334 #define DISPLAY_CONTROL_ENABLED (1UL << 31) 335 #define DISPLAY_CONTROL_GAMMA (1UL << 30) 336 #define DISPLAY_CONTROL_COLOR_MASK (0x0fUL << 26) 337 #define DISPLAY_CONTROL_CMAP8 (2UL << 26) 338 #define DISPLAY_CONTROL_RGB15 (4UL << 26) 339 #define DISPLAY_CONTROL_RGB16 (5UL << 26) 340 #define DISPLAY_CONTROL_RGB32 (6UL << 26) 341 342 #define INTEL_VGA_DISPLAY_CONTROL 0x71400 343 #define VGA_DISPLAY_DISABLED (1UL << 31) 344 345 #define INTEL_DISPLAY_A_PALETTE 0x0a000 346 347 #define INTEL_DISPLAY_A_PIPE_CONTROL 0x70008 348 #define DISPLAY_PIPE_ENABLED (1UL << 31) 349 #define INTEL_DISPLAY_A_PIPE_STATUS 0x70024 350 #define DISPLAY_PIPE_VBLANK_ENABLED (1UL << 17) 351 #define DISPLAY_PIPE_VBLANK_STATUS (1UL << 1) 352 353 #define INTEL_DISPLAY_A_PLL 0x06014 354 #define INTEL_DISPLAY_A_PLL_DIVISOR_0 0x06040 355 #define INTEL_DISPLAY_A_PLL_DIVISOR_1 0x06044 356 357 // display B 358 #define INTEL_DISPLAY_B_HTOTAL 0x61000 359 #define INTEL_DISPLAY_B_HBLANK 0x61004 360 #define INTEL_DISPLAY_B_HSYNC 0x61008 361 #define INTEL_DISPLAY_B_VTOTAL 0x6100c 362 #define INTEL_DISPLAY_B_VBLANK 0x61010 363 #define INTEL_DISPLAY_B_VSYNC 0x61014 364 365 #define INTEL_DISPLAY_B_DIGITAL_PORT 0x61140 366 #define INTEL_DISPLAY_B_PIPE_SIZE 0x71190 367 368 #define INTEL_DISPLAY_B_PIPE_CONTROL 0x71008 369 #define INTEL_DISPLAY_B_PIPE_STATUS 0x71024 370 371 #define INTEL_DISPLAY_B_CONTROL 0x71180 372 #define INTEL_DISPLAY_B_BASE 0x71184 373 #define INTEL_DISPLAY_B_BYTES_PER_ROW 0x71188 374 #define INTEL_DISPLAY_B_POS 0x7118C 375 376 #define INTEL_DISPLAY_B_IMAGE_SIZE 0x6101c 377 #define INTEL_DISPLAY_B_SURFACE 0x7119c // i965 and up only 378 379 #define INTEL_DISPLAY_B_PALETTE 0x0a800 380 381 #define INTEL_DISPLAY_B_PLL 0x06018 382 #define INTEL_DISPLAY_B_PLL_MULTIPLIER_DIVISOR 0x06020 383 #define INTEL_DISPLAY_B_PLL_DIVISOR_0 0x06048 384 #define INTEL_DISPLAY_B_PLL_DIVISOR_1 0x0604c 385 386 // LVDS panel 387 #define INTEL_PANEL_STATUS 0x61200 388 #define PANEL_STATUS_POWER_ON (1UL << 31) 389 #define INTEL_PANEL_CONTROL 0x61204 390 #define PANEL_CONTROL_POWER_TARGET_ON (1UL << 0) 391 #define INTEL_PANEL_FIT_CONTROL 0x61230 392 #define INTEL_PANEL_FIT_RATIOS 0x61234 393 394 // cursor 395 #define INTEL_CURSOR_CONTROL 0x70080 396 #define INTEL_CURSOR_BASE 0x70084 397 #define INTEL_CURSOR_POSITION 0x70088 398 #define INTEL_CURSOR_PALETTE 0x70090 // (- 0x7009f) 399 #define INTEL_CURSOR_SIZE 0x700a0 400 #define CURSOR_ENABLED (1UL << 31) 401 #define CURSOR_FORMAT_2_COLORS (0UL << 24) 402 #define CURSOR_FORMAT_3_COLORS (1UL << 24) 403 #define CURSOR_FORMAT_4_COLORS (2UL << 24) 404 #define CURSOR_FORMAT_ARGB (4UL << 24) 405 #define CURSOR_FORMAT_XRGB (5UL << 24) 406 #define CURSOR_POSITION_NEGATIVE 0x8000 407 #define CURSOR_POSITION_MASK 0x3fff 408 409 // ring buffer commands 410 411 #define COMMAND_NOOP 0x00 412 #define COMMAND_WAIT_FOR_EVENT (0x03 << 23) 413 #define COMMAND_WAIT_FOR_OVERLAY_FLIP (1 << 16) 414 415 #define COMMAND_FLUSH (0x04 << 23) 416 417 // overlay flip 418 #define COMMAND_OVERLAY_FLIP (0x11 << 23) 419 #define COMMAND_OVERLAY_CONTINUE (0 << 21) 420 #define COMMAND_OVERLAY_ON (1 << 21) 421 #define COMMAND_OVERLAY_OFF (2 << 21) 422 #define OVERLAY_UPDATE_COEFFICIENTS 0x1 423 424 // 2D acceleration 425 #define XY_COMMAND_SOURCE_BLIT 0x54c00006 426 #define XY_COMMAND_COLOR_BLIT 0x54000004 427 #define XY_COMMAND_SETUP_MONO_PATTERN 0x44400007 428 #define XY_COMMAND_SCANLINE_BLIT 0x49400001 429 #define COMMAND_COLOR_BLIT 0x50000003 430 #define COMMAND_BLIT_RGBA 0x00300000 431 432 #define COMMAND_MODE_SOLID_PATTERN 0x80 433 #define COMMAND_MODE_CMAP8 0x00 434 #define COMMAND_MODE_RGB15 0x02 435 #define COMMAND_MODE_RGB16 0x01 436 #define COMMAND_MODE_RGB32 0x03 437 438 // i2c 439 440 #define INTEL_I2C_IO_A 0x5010 441 #define INTEL_I2C_IO_B 0x5014 442 #define INTEL_I2C_IO_C 0x5018 443 #define INTEL_I2C_IO_D 0x501c 444 #define INTEL_I2C_IO_E 0x5020 445 #define INTEL_I2C_IO_F 0x5024 446 #define INTEL_I2C_IO_G 0x5028 447 #define INTEL_I2C_IO_H 0x502c 448 449 #define I2C_CLOCK_DIRECTION_MASK (1 << 0) 450 #define I2C_CLOCK_DIRECTION_OUT (1 << 1) 451 #define I2C_CLOCK_VALUE_MASK (1 << 2) 452 #define I2C_CLOCK_VALUE_OUT (1 << 3) 453 #define I2C_CLOCK_VALUE_IN (1 << 4) 454 #define I2C_DATA_DIRECTION_MASK (1 << 8) 455 #define I2C_DATA_DIRECTION_OUT (1 << 9) 456 #define I2C_DATA_VALUE_MASK (1 << 10) 457 #define I2C_DATA_VALUE_OUT (1 << 11) 458 #define I2C_DATA_VALUE_IN (1 << 12) 459 #define I2C_RESERVED ((1 << 13) | (1 << 5)) 460 461 // overlay 462 463 #define INTEL_OVERLAY_UPDATE 0x30000 464 #define INTEL_OVERLAY_TEST 0x30004 465 #define INTEL_OVERLAY_STATUS 0x30008 466 #define INTEL_OVERLAY_EXTENDED_STATUS 0x3000c 467 #define INTEL_OVERLAY_GAMMA_5 0x30010 468 #define INTEL_OVERLAY_GAMMA_4 0x30014 469 #define INTEL_OVERLAY_GAMMA_3 0x30018 470 #define INTEL_OVERLAY_GAMMA_2 0x3001c 471 #define INTEL_OVERLAY_GAMMA_1 0x30020 472 #define INTEL_OVERLAY_GAMMA_0 0x30024 473 474 struct overlay_scale { 475 uint32 _reserved0 : 3; 476 uint32 horizontal_scale_fraction : 12; 477 uint32 _reserved1 : 1; 478 uint32 horizontal_downscale_factor : 3; 479 uint32 _reserved2 : 1; 480 uint32 vertical_scale_fraction : 12; 481 }; 482 483 #define OVERLAY_FORMAT_RGB15 0x2 484 #define OVERLAY_FORMAT_RGB16 0x3 485 #define OVERLAY_FORMAT_RGB32 0x1 486 #define OVERLAY_FORMAT_YCbCr422 0x8 487 #define OVERLAY_FORMAT_YCbCr411 0x9 488 #define OVERLAY_FORMAT_YCbCr420 0xc 489 490 #define OVERLAY_MIRROR_NORMAL 0x0 491 #define OVERLAY_MIRROR_HORIZONTAL 0x1 492 #define OVERLAY_MIRROR_VERTICAL 0x2 493 494 // The real overlay registers are written to using an update buffer 495 496 struct overlay_registers { 497 uint32 buffer_rgb0; 498 uint32 buffer_rgb1; 499 uint32 buffer_u0; 500 uint32 buffer_v0; 501 uint32 buffer_u1; 502 uint32 buffer_v1; 503 // (0x18) OSTRIDE - overlay stride 504 uint16 stride_rgb; 505 uint16 stride_uv; 506 // (0x1c) YRGB_VPH - Y/RGB vertical phase 507 uint16 vertical_phase0_rgb; 508 uint16 vertical_phase1_rgb; 509 // (0x20) UV_VPH - UV vertical phase 510 uint16 vertical_phase0_uv; 511 uint16 vertical_phase1_uv; 512 // (0x24) HORZ_PH - horizontal phase 513 uint16 horizontal_phase_rgb; 514 uint16 horizontal_phase_uv; 515 // (0x28) INIT_PHS - initial phase shift 516 uint32 initial_vertical_phase0_shift_rgb0 : 4; 517 uint32 initial_vertical_phase1_shift_rgb0 : 4; 518 uint32 initial_horizontal_phase_shift_rgb0 : 4; 519 uint32 initial_vertical_phase0_shift_uv : 4; 520 uint32 initial_vertical_phase1_shift_uv : 4; 521 uint32 initial_horizontal_phase_shift_uv : 4; 522 uint32 _reserved0 : 8; 523 // (0x2c) DWINPOS - destination window position 524 uint16 window_left; 525 uint16 window_top; 526 // (0x30) DWINSZ - destination window size 527 uint16 window_width; 528 uint16 window_height; 529 // (0x34) SWIDTH - source width 530 uint16 source_width_rgb; 531 uint16 source_width_uv; 532 // (0x38) SWITDHSW - source width in 8 byte steps 533 uint16 source_bytes_per_row_rgb; 534 uint16 source_bytes_per_row_uv; 535 uint16 source_height_rgb; 536 uint16 source_height_uv; 537 overlay_scale scale_rgb; 538 overlay_scale scale_uv; 539 // (0x48) OCLRC0 - overlay color correction 0 540 uint32 brightness_correction : 8; // signed, -128 to 127 541 uint32 _reserved1 : 10; 542 uint32 contrast_correction : 9; // fixed point: 3.6 bits 543 uint32 _reserved2 : 5; 544 // (0x4c) OCLRC1 - overlay color correction 1 545 uint32 saturation_cos_correction : 10; // fixed point: 3.7 bits 546 uint32 _reserved3 : 6; 547 uint32 saturation_sin_correction : 11; // signed fixed point: 3.7 bits 548 uint32 _reserved4 : 5; 549 // (0x50) DCLRKV - destination color key value 550 uint32 color_key_blue : 8; 551 uint32 color_key_green : 8; 552 uint32 color_key_red : 8; 553 uint32 _reserved5 : 8; 554 // (0x54) DCLRKM - destination color key mask 555 uint32 color_key_mask_blue : 8; 556 uint32 color_key_mask_green : 8; 557 uint32 color_key_mask_red : 8; 558 uint32 _reserved6 : 7; 559 uint32 color_key_enabled : 1; 560 // (0x58) SCHRKVH - source chroma key high value 561 uint32 source_chroma_key_high_red : 8; 562 uint32 source_chroma_key_high_blue : 8; 563 uint32 source_chroma_key_high_green : 8; 564 uint32 _reserved7 : 8; 565 // (0x5c) SCHRKVL - source chroma key low value 566 uint32 source_chroma_key_low_red : 8; 567 uint32 source_chroma_key_low_blue : 8; 568 uint32 source_chroma_key_low_green : 8; 569 uint32 _reserved8 : 8; 570 // (0x60) SCHRKEN - source chroma key enable 571 uint32 _reserved9 : 24; 572 uint32 source_chroma_key_red_enabled : 1; 573 uint32 source_chroma_key_blue_enabled : 1; 574 uint32 source_chroma_key_green_enabled : 1; 575 uint32 _reserved10 : 5; 576 // (0x64) OCONFIG - overlay configuration 577 uint32 _reserved11 : 3; 578 uint32 color_control_output_mode : 1; 579 uint32 yuv_to_rgb_bypass : 1; 580 uint32 _reserved12 : 11; 581 uint32 gamma2_enabled : 1; 582 uint32 _reserved13 : 1; 583 uint32 select_pipe : 1; 584 uint32 slot_time : 8; 585 uint32 _reserved14 : 5; 586 // (0x68) OCOMD - overlay command 587 uint32 overlay_enabled : 1; 588 uint32 active_field : 1; 589 uint32 active_buffer : 2; 590 uint32 test_mode : 1; 591 uint32 buffer_field_mode : 1; 592 uint32 _reserved15 : 1; 593 uint32 tv_flip_field_enabled : 1; 594 uint32 _reserved16 : 1; 595 uint32 tv_flip_field_parity : 1; 596 uint32 source_format : 4; 597 uint32 ycbcr422_order : 2; 598 uint32 _reserved18 : 1; 599 uint32 mirroring_mode : 2; 600 uint32 _reserved19 : 13; 601 602 uint32 _reserved20; 603 604 uint32 start_0y; 605 uint32 start_1y; 606 uint32 start_0u; 607 uint32 start_0v; 608 uint32 start_1u; 609 uint32 start_1v; 610 uint32 _reserved21[6]; 611 #if 0 612 // (0x70) AWINPOS - alpha blend window position 613 uint32 awinpos; 614 // (0x74) AWINSZ - alpha blend window size 615 uint32 awinsz; 616 617 uint32 _reserved21[10]; 618 #endif 619 620 // (0xa0) FASTHSCALE - fast horizontal downscale (strangely enough, 621 // the next two registers switch the usual Y/RGB vs. UV order) 622 uint16 horizontal_scale_uv; 623 uint16 horizontal_scale_rgb; 624 // (0xa4) UVSCALEV - vertical downscale 625 uint16 vertical_scale_uv; 626 uint16 vertical_scale_rgb; 627 628 uint32 _reserved22[86]; 629 630 // (0x200) polyphase filter coefficients 631 uint16 vertical_coefficients_rgb[128]; 632 uint16 horizontal_coefficients_rgb[128]; 633 634 uint32 _reserved23[64]; 635 636 // (0x500) 637 uint16 vertical_coefficients_uv[128]; 638 uint16 horizontal_coefficients_uv[128]; 639 }; 640 641 // i965 overlay support is currently realized using its 3D hardware 642 #define INTEL_i965_OVERLAY_STATE_SIZE 36864 643 #define INTEL_i965_3D_CONTEXT_SIZE 32768 644 645 inline bool 646 intel_uses_physical_overlay(intel_shared_info &info) 647 { 648 return !info.device_type.InGroup(INTEL_TYPE_Gxx); 649 } 650 651 652 struct hardware_status { 653 uint32 interrupt_status_register; 654 uint32 _reserved0[3]; 655 void* primary_ring_head_storage; 656 uint32 _reserved1[3]; 657 void* secondary_ring_0_head_storage; 658 void* secondary_ring_1_head_storage; 659 uint32 _reserved2[2]; 660 void* binning_head_storage; 661 uint32 _reserved3[3]; 662 uint32 store[1008]; 663 }; 664 665 #endif /* INTEL_EXTREME_H */ 666