1 /* 2 * Copyright 2006-2016, Haiku, Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Axel Dörfler, axeld@pinc-software.de 7 * Alexander von Gluck, kallisti5@unixzen.com 8 */ 9 #ifndef INTEL_EXTREME_H 10 #define INTEL_EXTREME_H 11 12 13 #include "lock.h" 14 15 #include <Accelerant.h> 16 #include <Drivers.h> 17 #include <PCI.h> 18 19 #include <edid.h> 20 21 22 #define VENDOR_ID_INTEL 0x8086 23 24 #define INTEL_FAMILY_MASK 0x00ff0000 25 #define INTEL_GROUP_MASK 0x00fffff0 26 #define INTEL_MODEL_MASK 0x00ffffff 27 #define INTEL_TYPE_MASK 0x0000000f 28 29 // families 30 #define INTEL_FAMILY_8xx 0x00020000 // Second Gen 31 #define INTEL_FAMILY_9xx 0x00040000 // Third Gen + 32 #define INTEL_FAMILY_SER5 0x00080000 // Intel5 Series 33 #define INTEL_FAMILY_SOC0 0x00200000 // Atom SOC 34 #define INTEL_FAMILY_LAKE 0x00400000 // Intel Lakes 35 36 // groups 37 #define INTEL_GROUP_83x (INTEL_FAMILY_8xx | 0x0010) 38 #define INTEL_GROUP_85x (INTEL_FAMILY_8xx | 0x0020) 39 #define INTEL_GROUP_91x (INTEL_FAMILY_9xx | 0x0010) 40 #define INTEL_GROUP_94x (INTEL_FAMILY_9xx | 0x0020) 41 #define INTEL_GROUP_96x (INTEL_FAMILY_9xx | 0x0040) 42 #define INTEL_GROUP_Gxx (INTEL_FAMILY_9xx | 0x0080) 43 #define INTEL_GROUP_G4x (INTEL_FAMILY_9xx | 0x0100) 44 #define INTEL_GROUP_PIN (INTEL_FAMILY_9xx | 0x0200) // PineView 45 #define INTEL_GROUP_ILK (INTEL_FAMILY_SER5 | 0x0010) // IronLake 46 #define INTEL_GROUP_SNB (INTEL_FAMILY_SER5 | 0x0020) // SandyBridge 47 #define INTEL_GROUP_IVB (INTEL_FAMILY_SER5 | 0x0040) // IvyBridge 48 #define INTEL_GROUP_HAS (INTEL_FAMILY_SER5 | 0x0080) // Haswell 49 #define INTEL_GROUP_VLV (INTEL_FAMILY_SOC0 | 0x0010) // ValleyView 50 #define INTEL_GROUP_CHV (INTEL_FAMILY_SOC0 | 0x0020) // CherryView 51 #define INTEL_GROUP_BDW (INTEL_FAMILY_SOC0 | 0x0040) // Broadwell 52 #define INTEL_GROUP_SKY (INTEL_FAMILY_LAKE | 0x0010) // SkyLake 53 #define INTEL_GROUP_KBY (INTEL_FAMILY_LAKE | 0x0020) // KabyLake 54 #define INTEL_GROUP_CFL (INTEL_FAMILY_LAKE | 0x0040) // CoffeeLake 55 #define INTEL_GROUP_CML (INTEL_FAMILY_LAKE | 0x0080) // CometLake 56 #define INTEL_GROUP_JSL (INTEL_FAMILY_LAKE | 0x0100) // JasperLake 57 // models 58 #define INTEL_TYPE_SERVER 0x0004 59 #define INTEL_TYPE_MOBILE 0x0008 60 #define INTEL_MODEL_915 (INTEL_GROUP_91x) 61 #define INTEL_MODEL_915M (INTEL_GROUP_91x | INTEL_TYPE_MOBILE) 62 #define INTEL_MODEL_945 (INTEL_GROUP_94x) 63 #define INTEL_MODEL_945M (INTEL_GROUP_94x | INTEL_TYPE_MOBILE) 64 #define INTEL_MODEL_965 (INTEL_GROUP_96x) 65 #define INTEL_MODEL_965M (INTEL_GROUP_96x | INTEL_TYPE_MOBILE) 66 #define INTEL_MODEL_G33 (INTEL_GROUP_Gxx) 67 #define INTEL_MODEL_G45 (INTEL_GROUP_G4x) 68 #define INTEL_MODEL_GM45 (INTEL_GROUP_G4x | INTEL_TYPE_MOBILE) 69 #define INTEL_MODEL_PINE (INTEL_GROUP_PIN) 70 #define INTEL_MODEL_PINEM (INTEL_GROUP_PIN | INTEL_TYPE_MOBILE) 71 #define INTEL_MODEL_ILKG (INTEL_GROUP_ILK) 72 #define INTEL_MODEL_ILKGM (INTEL_GROUP_ILK | INTEL_TYPE_MOBILE) 73 #define INTEL_MODEL_SNBG (INTEL_GROUP_SNB) 74 #define INTEL_MODEL_SNBGM (INTEL_GROUP_SNB | INTEL_TYPE_MOBILE) 75 #define INTEL_MODEL_SNBGS (INTEL_GROUP_SNB | INTEL_TYPE_SERVER) 76 #define INTEL_MODEL_IVBG (INTEL_GROUP_IVB) 77 #define INTEL_MODEL_IVBGM (INTEL_GROUP_IVB | INTEL_TYPE_MOBILE) 78 #define INTEL_MODEL_IVBGS (INTEL_GROUP_IVB | INTEL_TYPE_SERVER) 79 #define INTEL_MODEL_HAS (INTEL_GROUP_HAS) 80 #define INTEL_MODEL_HASM (INTEL_GROUP_HAS | INTEL_TYPE_MOBILE) 81 #define INTEL_MODEL_VLV (INTEL_GROUP_VLV) 82 #define INTEL_MODEL_VLVM (INTEL_GROUP_VLV | INTEL_TYPE_MOBILE) 83 #define INTEL_MODEL_BDW (INTEL_GROUP_BDW) 84 #define INTEL_MODEL_BDWM (INTEL_GROUP_BDW | INTEL_TYPE_MOBILE) 85 #define INTEL_MODEL_SKY (INTEL_GROUP_SKY) 86 #define INTEL_MODEL_SKYM (INTEL_GROUP_SKY | INTEL_TYPE_MOBILE) 87 #define INTEL_MODEL_SKYS (INTEL_GROUP_SKY | INTEL_TYPE_SERVER) 88 #define INTEL_MODEL_KBY (INTEL_GROUP_KBY) 89 #define INTEL_MODEL_KBYM (INTEL_GROUP_KBY | INTEL_TYPE_MOBILE) 90 #define INTEL_MODEL_CFL (INTEL_GROUP_CFL) 91 #define INTEL_MODEL_CFLM (INTEL_GROUP_CFL | INTEL_TYPE_MOBILE) 92 #define INTEL_MODEL_CML (INTEL_GROUP_CML) 93 #define INTEL_MODEL_JSL (INTEL_GROUP_JSL) 94 #define INTEL_MODEL_JSLM (INTEL_GROUP_JSL | INTEL_TYPE_MOBILE) 95 96 #define INTEL_PCH_DEVICE_ID_MASK 0xff80 97 #define INTEL_PCH_IBX_DEVICE_ID 0x3b00 98 #define INTEL_PCH_CPT_DEVICE_ID 0x1c00 99 #define INTEL_PCH_PPT_DEVICE_ID 0x1e00 100 #define INTEL_PCH_LPT_DEVICE_ID 0x8c00 101 #define INTEL_PCH_LPT_LP_DEVICE_ID 0x9c00 102 #define INTEL_PCH_WPT_DEVICE_ID 0x8c80 103 #define INTEL_PCH_WPT_LP_DEVICE_ID 0x9c80 104 #define INTEL_PCH_SPT_DEVICE_ID 0xa100 105 #define INTEL_PCH_SPT_LP_DEVICE_ID 0x9d00 106 #define INTEL_PCH_KBP_DEVICE_ID 0xa280 107 #define INTEL_PCH_CNP_DEVICE_ID 0xa300 108 #define INTEL_PCH_CNP_LP_DEVICE_ID 0x9d80 109 #define INTEL_PCH_CMP_DEVICE_ID 0x0280 110 #define INTEL_PCH_CMP2_DEVICE_ID 0x0680 111 #define INTEL_PCH_CMP_V_DEVICE_ID 0xa380 112 #define INTEL_PCH_ICP_DEVICE_ID 0x3480 113 #define INTEL_PCH_MCC_DEVICE_ID 0x4b00 114 #define INTEL_PCH_TGP_DEVICE_ID 0xa080 115 #define INTEL_PCH_TGP2_DEVICE_ID 0x4380 116 #define INTEL_PCH_JSP_DEVICE_ID 0x4d80 117 #define INTEL_PCH_JSP2_DEVICE_ID 0x3880 118 #define INTEL_PCH_ADP_DEVICE_ID 0x7a80 119 #define INTEL_PCH_ADP2_DEVICE_ID 0x5180 120 #define INTEL_PCH_P2X_DEVICE_ID 0x7100 121 #define INTEL_PCH_P3X_DEVICE_ID 0x7000 122 123 // ValleyView MMIO offset 124 #define VLV_DISPLAY_BASE 0x180000 125 126 #define DEVICE_NAME "intel_extreme" 127 #define INTEL_ACCELERANT_NAME "intel_extreme.accelerant" 128 129 // We encode the register block into the value and extract/translate it when 130 // actually accessing. 131 #define REGISTER_BLOCK_COUNT 6 132 #define REGISTER_BLOCK_SHIFT 24 133 #define REGISTER_BLOCK_MASK 0xff000000 134 #define REGISTER_REGISTER_MASK 0x00ffffff 135 #define REGISTER_BLOCK(x) ((x & REGISTER_BLOCK_MASK) >> REGISTER_BLOCK_SHIFT) 136 #define REGISTER_REGISTER(x) (x & REGISTER_REGISTER_MASK) 137 138 #define REGS_FLAT (0 << REGISTER_BLOCK_SHIFT) 139 #define REGS_NORTH_SHARED (1 << REGISTER_BLOCK_SHIFT) 140 #define REGS_NORTH_PIPE_AND_PORT (2 << REGISTER_BLOCK_SHIFT) 141 #define REGS_NORTH_PLANE_CONTROL (3 << REGISTER_BLOCK_SHIFT) 142 #define REGS_SOUTH_SHARED (4 << REGISTER_BLOCK_SHIFT) 143 #define REGS_SOUTH_TRANSCODER_PORT (5 << REGISTER_BLOCK_SHIFT) 144 145 // register blocks for (G)MCH/ICH based platforms 146 #define MCH_SHARED_REGISTER_BASE 0x00000 147 #define MCH_PIPE_AND_PORT_REGISTER_BASE 0x60000 148 #define MCH_PLANE_CONTROL_REGISTER_BASE 0x70000 149 150 #define ICH_SHARED_REGISTER_BASE 0x00000 151 #define ICH_PORT_REGISTER_BASE 0x60000 152 153 // PCH - Platform Control Hub - Some hardware moves from a MCH/ICH based 154 // setup to a PCH based one, that means anything that used to communicate via 155 // (G)MCH registers needs to use different ones on PCH based platforms 156 // (Ironlake, SandyBridge, IvyBridge, Some Haswell). 157 #define PCH_NORTH_SHARED_REGISTER_BASE 0x40000 158 #define PCH_NORTH_PIPE_AND_PORT_REGISTER_BASE 0x60000 159 #define PCH_NORTH_PLANE_CONTROL_REGISTER_BASE 0x70000 160 #define PCH_SOUTH_SHARED_REGISTER_BASE 0xc0000 161 #define PCH_SOUTH_TRANSCODER_AND_PORT_REGISTER_BASE 0xe0000 162 163 164 struct DeviceType { 165 uint32 type; 166 167 DeviceType(int t) 168 { 169 type = t; 170 } 171 172 DeviceType& operator=(int t) 173 { 174 type = t; 175 return *this; 176 } 177 178 bool InFamily(uint32 family) const 179 { 180 return (type & INTEL_FAMILY_MASK) == family; 181 } 182 183 bool InGroup(uint32 group) const 184 { 185 return (type & INTEL_GROUP_MASK) == group; 186 } 187 188 bool IsModel(uint32 model) const 189 { 190 return (type & INTEL_MODEL_MASK) == model; 191 } 192 193 bool IsMobile() const 194 { 195 return (type & INTEL_TYPE_MASK) == INTEL_TYPE_MOBILE; 196 } 197 198 bool SupportsHDMI() const 199 { 200 return InGroup(INTEL_GROUP_G4x) || InFamily(INTEL_FAMILY_SER5) 201 || InFamily(INTEL_FAMILY_SOC0); 202 } 203 204 bool HasDDI() const 205 { 206 // Intel Digital Display Interface 207 return InGroup(INTEL_GROUP_HAS) || (Generation() >= 8); 208 } 209 210 int Generation() const 211 { 212 if (InFamily(INTEL_FAMILY_8xx)) 213 return 2; 214 if (InGroup(INTEL_GROUP_91x) || InGroup(INTEL_GROUP_94x) 215 || IsModel(INTEL_MODEL_G33) || InGroup(INTEL_GROUP_PIN)) 216 return 3; 217 if (InFamily(INTEL_FAMILY_9xx)) 218 return 4; 219 if (InGroup(INTEL_GROUP_ILK)) 220 return 5; 221 if (InGroup(INTEL_GROUP_SNB)) 222 return 6; 223 if (InFamily(INTEL_FAMILY_SER5) || InGroup(INTEL_GROUP_VLV)) 224 return 7; 225 if (InGroup(INTEL_GROUP_CHV) || InGroup(INTEL_GROUP_BDW)) 226 return 8; 227 if (InFamily(INTEL_FAMILY_LAKE)) 228 return 9; 229 230 // Generation 0 means something is wrong :-) 231 return 0; 232 } 233 }; 234 235 enum port_index { 236 INTEL_PORT_ANY, // wildcard for lookup functions 237 INTEL_PORT_A, 238 INTEL_PORT_B, 239 INTEL_PORT_C, 240 INTEL_PORT_D, 241 INTEL_PORT_E, 242 INTEL_PORT_F 243 }; 244 245 enum pch_info { 246 INTEL_PCH_NONE = 0, // No PCH present 247 INTEL_PCH_IBX, // Ibexpeak 248 INTEL_PCH_CPT, // Cougarpoint 249 INTEL_PCH_LPT, // Lynxpoint 250 INTEL_PCH_SPT, // SunrisePoint 251 INTEL_PCH_CNP, // CannonLake 252 INTEL_PCH_ICP, // IceLake 253 INTEL_PCH_JSP, // JasperLake 254 INTEL_PCH_MCC, // Mule Creek Canyon 255 INTEL_PCH_TGP, // TigerLake 256 INTEL_PCH_ADP, // AlderLake 257 INTEL_PCH_NOP 258 }; 259 260 // info about PLL on graphics card 261 struct pll_info { 262 uint32 reference_frequency; 263 uint32 max_frequency; 264 uint32 min_frequency; 265 uint32 divisor_register; 266 }; 267 268 struct ring_buffer { 269 struct lock lock; 270 uint32 register_base; 271 uint32 offset; 272 uint32 size; 273 uint32 position; 274 uint32 space_left; 275 uint8* base; 276 }; 277 278 struct overlay_registers; 279 280 struct intel_shared_info { 281 area_id mode_list_area; // area containing display mode list 282 uint32 mode_count; 283 284 display_mode current_mode; // pretty much a hack until per-display modes 285 display_timing panel_timing; // Hardware timings of the LVDS panel, extracted from BIOS 286 uint32 bytes_per_row; 287 uint32 bits_per_pixel; 288 uint32 dpms_mode; 289 290 area_id registers_area; // area of memory mapped registers 291 uint32 register_blocks[REGISTER_BLOCK_COUNT]; 292 293 uint8* status_page; 294 phys_addr_t physical_status_page; 295 uint8* graphics_memory; 296 phys_addr_t physical_graphics_memory; 297 uint32 graphics_memory_size; 298 299 addr_t frame_buffer; 300 uint32 frame_buffer_offset; 301 302 uint32 fdi_link_frequency; // In Mhz 303 304 bool got_vbt; 305 bool single_head_locked; 306 307 struct lock accelerant_lock; 308 struct lock engine_lock; 309 310 ring_buffer primary_ring_buffer; 311 312 int32 overlay_channel_used; 313 bool overlay_active; 314 uintptr_t overlay_token; 315 phys_addr_t physical_overlay_registers; 316 uint32 overlay_offset; 317 318 bool hardware_cursor_enabled; 319 sem_id vblank_sem; 320 321 uint8* cursor_memory; 322 phys_addr_t physical_cursor_memory; 323 uint32 cursor_buffer_offset; 324 uint32 cursor_format; 325 bool cursor_visible; 326 uint16 cursor_hot_x; 327 uint16 cursor_hot_y; 328 329 DeviceType device_type; 330 char device_identifier[32]; 331 struct pll_info pll_info; 332 333 enum pch_info pch_info; 334 335 edid1_info vesa_edid_info; 336 bool has_vesa_edid_info; 337 }; 338 339 enum pipe_index { 340 INTEL_PIPE_ANY, 341 INTEL_PIPE_A, 342 INTEL_PIPE_B, 343 INTEL_PIPE_C, 344 INTEL_PIPE_D 345 }; 346 347 class pipes { 348 public: 349 pipes() : bitmask(0) {} 350 351 bool HasPipe(pipe_index pipe) 352 { 353 if (pipe == INTEL_PIPE_ANY) 354 return bitmask != 0; 355 356 return (bitmask & (1 << pipe)) != 0; 357 } 358 359 void SetPipe(pipe_index pipe) 360 { 361 if (pipe == INTEL_PIPE_ANY) { 362 bitmask = ~1; 363 // first bit corresponds to INTEL_PIPE_ANY but it's never used, 364 // so it should be 0 365 } 366 bitmask |= (1 << pipe); 367 } 368 369 void ClearPipe(pipe_index pipe) 370 { 371 if (pipe == INTEL_PIPE_ANY) 372 bitmask = 0; 373 374 bitmask &= ~(1 << pipe); 375 } 376 377 private: 378 uint8 bitmask; 379 }; 380 381 //----------------- ioctl() interface ---------------- 382 383 // magic code for ioctls 384 #define INTEL_PRIVATE_DATA_MAGIC 'itic' 385 386 // list ioctls 387 enum { 388 INTEL_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1, 389 390 INTEL_GET_DEVICE_NAME, 391 INTEL_ALLOCATE_GRAPHICS_MEMORY, 392 INTEL_FREE_GRAPHICS_MEMORY 393 }; 394 395 // retrieve the area_id of the kernel/accelerant shared info 396 struct intel_get_private_data { 397 uint32 magic; // magic number 398 area_id shared_info_area; 399 }; 400 401 // allocate graphics memory 402 struct intel_allocate_graphics_memory { 403 uint32 magic; 404 uint32 size; 405 uint32 alignment; 406 uint32 flags; 407 addr_t buffer_base; 408 }; 409 410 // free graphics memory 411 struct intel_free_graphics_memory { 412 uint32 magic; 413 addr_t buffer_base; 414 }; 415 416 //---------------------------------------------------------- 417 // Register definitions, taken from X driver 418 419 // PCI bridge memory management 420 #define INTEL_GRAPHICS_MEMORY_CONTROL 0x52 // i830+ 421 422 // GGC - (G)MCH Graphics Control Register 423 #define MEMORY_CONTROL_ENABLED 0x0004 424 #define MEMORY_MASK 0x0001 425 #define STOLEN_MEMORY_MASK 0x00f0 426 #define i965_GTT_MASK 0x000e 427 #define G33_GTT_MASK 0x0300 428 #define G4X_GTT_MASK 0x0f00 // GGMS (GSM Memory Size) mask 429 430 // models i830 and up 431 #define i830_LOCAL_MEMORY_ONLY 0x10 432 #define i830_STOLEN_512K 0x20 433 #define i830_STOLEN_1M 0x30 434 #define i830_STOLEN_8M 0x40 435 #define i830_FRAME_BUFFER_64M 0x01 436 #define i830_FRAME_BUFFER_128M 0x00 437 438 // models i855 and up 439 #define i855_STOLEN_MEMORY_1M 0x10 440 #define i855_STOLEN_MEMORY_4M 0x20 441 #define i855_STOLEN_MEMORY_8M 0x30 442 #define i855_STOLEN_MEMORY_16M 0x40 443 #define i855_STOLEN_MEMORY_32M 0x50 444 #define i855_STOLEN_MEMORY_48M 0x60 445 #define i855_STOLEN_MEMORY_64M 0x70 446 #define i855_STOLEN_MEMORY_128M 0x80 447 #define i855_STOLEN_MEMORY_256M 0x90 448 449 #define G4X_STOLEN_MEMORY_96MB 0xa0 // GMS - Graphics Mode Select 450 #define G4X_STOLEN_MEMORY_160MB 0xb0 451 #define G4X_STOLEN_MEMORY_224MB 0xc0 452 #define G4X_STOLEN_MEMORY_352MB 0xd0 453 454 // SandyBridge (SNB) 455 456 #define SNB_GRAPHICS_MEMORY_CONTROL 0x50 457 458 #define SNB_STOLEN_MEMORY_MASK 0xf8 459 #define SNB_STOLEN_MEMORY_32MB (1 << 3) 460 #define SNB_STOLEN_MEMORY_64MB (2 << 3) 461 #define SNB_STOLEN_MEMORY_96MB (3 << 3) 462 #define SNB_STOLEN_MEMORY_128MB (4 << 3) 463 #define SNB_STOLEN_MEMORY_160MB (5 << 3) 464 #define SNB_STOLEN_MEMORY_192MB (6 << 3) 465 #define SNB_STOLEN_MEMORY_224MB (7 << 3) 466 #define SNB_STOLEN_MEMORY_256MB (8 << 3) 467 #define SNB_STOLEN_MEMORY_288MB (9 << 3) 468 #define SNB_STOLEN_MEMORY_320MB (10 << 3) 469 #define SNB_STOLEN_MEMORY_352MB (11 << 3) 470 #define SNB_STOLEN_MEMORY_384MB (12 << 3) 471 #define SNB_STOLEN_MEMORY_416MB (13 << 3) 472 #define SNB_STOLEN_MEMORY_448MB (14 << 3) 473 #define SNB_STOLEN_MEMORY_480MB (15 << 3) 474 #define SNB_STOLEN_MEMORY_512MB (16 << 3) 475 476 #define SNB_GTT_SIZE_MASK (3 << 8) 477 #define SNB_GTT_SIZE_NONE (0 << 8) 478 #define SNB_GTT_SIZE_1MB (1 << 8) 479 #define SNB_GTT_SIZE_2MB (2 << 8) 480 481 // BDW+ (GGC_0_0_0_PCI) 482 483 #define BDW_GRAPHICS_MEMORY_CONTROL 0x50 484 485 #define BDW_STOLEN_MEMORY_MASK 0xff00 486 #define BDW_STOLEN_MEMORY_32MB (1 << 8) 487 #define BDW_STOLEN_MEMORY_64MB (2 << 8) 488 #define BDW_STOLEN_MEMORY_96MB (3 << 8) 489 #define BDW_STOLEN_MEMORY_128MB (4 << 8) 490 #define BDW_STOLEN_MEMORY_160MB (5 << 8) 491 #define BDW_STOLEN_MEMORY_192MB (6 << 8) 492 #define BDW_STOLEN_MEMORY_224MB (7 << 8) 493 #define BDW_STOLEN_MEMORY_256MB (8 << 8) 494 #define BDW_STOLEN_MEMORY_288MB (9 << 8) 495 #define BDW_STOLEN_MEMORY_320MB (10 << 8) 496 #define BDW_STOLEN_MEMORY_352MB (11 << 8) 497 #define BDW_STOLEN_MEMORY_384MB (12 << 8) 498 #define BDW_STOLEN_MEMORY_416MB (13 << 8) 499 #define BDW_STOLEN_MEMORY_448MB (14 << 8) 500 #define BDW_STOLEN_MEMORY_480MB (15 << 8) 501 #define BDW_STOLEN_MEMORY_512MB (16 << 8) 502 #define BDW_STOLEN_MEMORY_1024MB (32 << 8) 503 #define BDW_STOLEN_MEMORY_1536MB (48 << 8) 504 #define BDW_STOLEN_MEMORY_2016MB (63 << 8) 505 #define SKL_STOLEN_MEMORY_2048MB (64 << 8) 506 #define SKL_STOLEN_MEMORY_4MB (240 << 8) 507 #define SKL_STOLEN_MEMORY_8MB (241 << 8) 508 #define SKL_STOLEN_MEMORY_12MB (242 << 8) 509 #define SKL_STOLEN_MEMORY_16MB (243 << 8) 510 #define SKL_STOLEN_MEMORY_20MB (244 << 8) 511 #define SKL_STOLEN_MEMORY_24MB (245 << 8) 512 #define SKL_STOLEN_MEMORY_28MB (246 << 8) 513 #define SKL_STOLEN_MEMORY_32MB (247 << 8) 514 #define SKL_STOLEN_MEMORY_36MB (248 << 8) 515 #define SKL_STOLEN_MEMORY_40MB (249 << 8) 516 #define SKL_STOLEN_MEMORY_44MB (250 << 8) 517 #define SKL_STOLEN_MEMORY_48MB (251 << 8) 518 #define SKL_STOLEN_MEMORY_52MB (252 << 8) 519 #define SKL_STOLEN_MEMORY_56MB (253 << 8) 520 #define SKL_STOLEN_MEMORY_60MB (254 << 8) 521 522 523 #define BDW_GTT_SIZE_MASK (3 << 6) 524 #define BDW_GTT_SIZE_NONE (0 << 6) 525 #define BDW_GTT_SIZE_2MB (1 << 6) 526 #define BDW_GTT_SIZE_4MB (2 << 6) 527 #define BDW_GTT_SIZE_8MB (3 << 6) 528 529 // graphics page translation table 530 #define INTEL_PAGE_TABLE_CONTROL 0x02020 531 #define PAGE_TABLE_ENABLED 0x00000001 532 #define INTEL_PAGE_TABLE_ERROR 0x02024 533 #define INTEL_HARDWARE_STATUS_PAGE 0x02080 534 #define i915_GTT_BASE 0x1c 535 #define i830_GTT_BASE 0x10000 // (- 0x2ffff) 536 #define i830_GTT_SIZE 0x20000 537 #define i965_GTT_BASE 0x80000 // (- 0xfffff) 538 #define i965_GTT_SIZE 0x80000 539 #define i965_GTT_128K (2 << 1) 540 #define i965_GTT_256K (1 << 1) 541 #define i965_GTT_512K (0 << 1) 542 #define G33_GTT_1M (1 << 8) 543 #define G33_GTT_2M (2 << 8) 544 #define G4X_GTT_NONE 0x000 // GGMS - GSM Memory Size 545 #define G4X_GTT_1M_NO_IVT 0x100 // no Intel Virtualization Tech. 546 #define G4X_GTT_2M_NO_IVT 0x300 547 #define G4X_GTT_2M_IVT 0x900 // with Intel Virt. Tech. 548 #define G4X_GTT_3M_IVT 0xa00 549 #define G4X_GTT_4M_IVT 0xb00 550 551 552 #define GTT_ENTRY_VALID 0x01 553 #define GTT_ENTRY_LOCAL_MEMORY 0x02 554 #define GTT_PAGE_SHIFT 12 555 556 557 // ring buffer 558 #define INTEL_PRIMARY_RING_BUFFER 0x02030 559 #define INTEL_SECONDARY_RING_BUFFER_0 0x02100 560 #define INTEL_SECONDARY_RING_BUFFER_1 0x02110 561 // offsets for the ring buffer base registers above 562 #define RING_BUFFER_TAIL 0x0 563 #define RING_BUFFER_HEAD 0x4 564 #define RING_BUFFER_START 0x8 565 #define RING_BUFFER_CONTROL 0xc 566 #define INTEL_RING_BUFFER_SIZE_MASK 0x001ff000 567 #define INTEL_RING_BUFFER_HEAD_MASK 0x001ffffc 568 #define INTEL_RING_BUFFER_ENABLED 1 569 570 // interrupts 571 #define INTEL_INTERRUPT_ENABLED 0x020a0 572 #define INTEL_INTERRUPT_IDENTITY 0x020a4 573 #define INTEL_INTERRUPT_MASK 0x020a8 574 #define INTEL_INTERRUPT_STATUS 0x020ac 575 #define INTERRUPT_VBLANK_PIPEA (1 << 7) 576 #define INTERRUPT_VBLANK_PIPEB (1 << 5) 577 578 // PCH interrupts 579 #define PCH_INTERRUPT_STATUS 0x44000 580 #define PCH_INTERRUPT_MASK 0x44004 581 #define PCH_INTERRUPT_IDENTITY 0x44008 582 #define PCH_INTERRUPT_ENABLED 0x4400c 583 584 #define PCH_INTERRUPT_VBLANK_PIPEA (1 << 0) 585 #define PCH_INTERRUPT_VBLANK_PIPEB (1 << 5) 586 #define PCH_INTERRUPT_VBLANK_PIPEC (1 << 10) 587 588 // SandyBridge had only two pipes, and things were shuffled aroud again with 589 // the introduction of pipe C. 590 #define PCH_INTERRUPT_VBLANK_PIPEA_SNB (1 << 7) 591 #define PCH_INTERRUPT_VBLANK_PIPEB_SNB (1 << 15) 592 #define PCH_INTERRUPT_GLOBAL_SNB (1 << 31) 593 594 #define PCH_MASTER_INT_CTL_BDW 0x44200 595 596 #define PCH_MASTER_INT_CTL_PIPE_PENDING_BDW(pipe) (1 << (15 + pipe)) 597 #define PCH_MASTER_INT_CTL_GLOBAL_BDW (1 << 31) 598 599 #define PCH_INTERRUPT_PIPE_STATUS_BDW(pipe) (0x44400 + (pipe - 1) * 0x10) 600 #define PCH_INTERRUPT_PIPE_MASK_BDW(pipe) (0x44404 + (pipe - 1) * 0x10) 601 #define PCH_INTERRUPT_PIPE_IDENTITY_BDW(pipe) (0x44408 + (pipe - 1) * 0x10) 602 #define PCH_INTERRUPT_PIPE_ENABLED_BDW(pipe) (0x4440c + (pipe - 1) * 0x10) 603 604 #define PCH_INTERRUPT_VBLANK_BDW (1 << 0) 605 606 // graphics port control (i.e. G45) 607 #define DISPLAY_MONITOR_PORT_ENABLED (1UL << 31) 608 #define DISPLAY_MONITOR_PIPE_B (1UL << 30) 609 #define DISPLAY_MONITOR_VGA_POLARITY (1UL << 15) 610 #define DISPLAY_MONITOR_MODE_MASK (3UL << 10) 611 #define DISPLAY_MONITOR_ON 0 612 #define DISPLAY_MONITOR_SUSPEND (1UL << 10) 613 #define DISPLAY_MONITOR_STAND_BY (2UL << 10) 614 #define DISPLAY_MONITOR_OFF (3UL << 10) 615 #define DISPLAY_MONITOR_POLARITY_MASK (3UL << 3) 616 #define DISPLAY_MONITOR_POSITIVE_HSYNC (1UL << 3) 617 #define DISPLAY_MONITOR_POSITIVE_VSYNC (2UL << 3) 618 #define DISPLAY_MONITOR_PORT_DETECTED (1UL << 2) // TMDS/DisplayPort only 619 620 // Cougar Point transcoder pipe selection 621 // (replaces DISPLAY_MONITOR_PIPE_B) 622 #define PORT_TRANS_A_SEL_CPT 0 623 #define PORT_TRANS_B_SEL_CPT (1<<29) 624 #define PORT_TRANS_C_SEL_CPT (2<<29) 625 #define PORT_TRANS_SEL_MASK (3<<29) 626 627 #define LVDS_POST2_RATE_SLOW 14 // PLL Divisors 628 #define LVDS_POST2_RATE_FAST 7 629 #define LVDS_B0B3_POWER_MASK (3UL << 2) 630 #define LVDS_B0B3_POWER_UP (3UL << 2) 631 #define LVDS_CLKB_POWER_MASK (3UL << 4) 632 #define LVDS_CLKB_POWER_UP (3UL << 4) 633 #define LVDS_A3_POWER_MASK (3UL << 6) 634 #define LVDS_A3_POWER_UP (3UL << 6) 635 #define LVDS_A0A2_CLKA_POWER_UP (3UL << 8) 636 #define LVDS_BORDER_ENABLE (1UL << 15) 637 #define LVDS_HSYNC_POLARITY (1UL << 20) 638 #define LVDS_VSYNC_POLARITY (1UL << 21) 639 #define LVDS_18BIT_DITHER (1UL << 25) 640 #define LVDS_PORT_EN (1UL << 31) 641 642 // PLL flags (pre-DDI) 643 #define DISPLAY_PLL_ENABLED (1UL << 31) 644 #define DISPLAY_PLL_2X_CLOCK (1UL << 30) 645 #define DISPLAY_PLL_SYNC_LOCK_ENABLED (1UL << 29) 646 #define DISPLAY_PLL_NO_VGA_CONTROL (1UL << 28) 647 #define DISPLAY_PLL_MODE_NORMAL (1UL << 26) 648 #define DISPLAY_PLL_MODE_LVDS (2UL << 26) 649 #define DISPLAY_PLL_DIVIDE_HIGH (1UL << 24) 650 #define DISPLAY_PLL_DIVIDE_4X (1UL << 23) 651 #define DISPLAY_PLL_POST1_DIVIDE_2 (1UL << 21) 652 #define DISPLAY_PLL_POST1_DIVISOR_MASK 0x001f0000 653 #define DISPLAY_PLL_9xx_POST1_DIVISOR_MASK 0x00ff0000 654 #define DISPLAY_PLL_SNB_FP0_POST1_DIVISOR_MASK 0x000000ff 655 #define DISPLAY_PLL_IGD_POST1_DIVISOR_MASK 0x00ff8000 656 #define DISPLAY_PLL_POST1_DIVISOR_SHIFT 16 657 #define DISPLAY_PLL_SNB_FP0_POST1_DIVISOR_SHIFT 0 658 #define DISPLAY_PLL_IGD_POST1_DIVISOR_SHIFT 15 659 #define DISPLAY_PLL_DIVISOR_1 (1UL << 8) 660 #define DISPLAY_PLL_N_DIVISOR_MASK 0x001f0000 661 #define DISPLAY_PLL_IGD_N_DIVISOR_MASK 0x00ff0000 662 #define DISPLAY_PLL_M1_DIVISOR_MASK 0x00001f00 663 #define DISPLAY_PLL_M2_DIVISOR_MASK 0x0000001f 664 #define DISPLAY_PLL_IGD_M2_DIVISOR_MASK 0x000000ff 665 #define DISPLAY_PLL_N_DIVISOR_SHIFT 16 666 #define DISPLAY_PLL_M1_DIVISOR_SHIFT 8 667 #define DISPLAY_PLL_M2_DIVISOR_SHIFT 0 668 #define DISPLAY_PLL_PULSE_PHASE_SHIFT 9 669 670 // Skylake PLLs 671 #define SKL_DPLL1_CFGCR1 (0xc040 | REGS_NORTH_PIPE_AND_PORT) 672 #define SKL_DPLL1_CFGCR2 (0xc044 | REGS_NORTH_PIPE_AND_PORT) 673 #define SKL_DPLL2_CFGCR1 (0xc048 | REGS_NORTH_PIPE_AND_PORT) 674 #define SKL_DPLL2_CFGCR2 (0xc04c | REGS_NORTH_PIPE_AND_PORT) 675 #define SKL_DPLL3_CFGCR1 (0xc050 | REGS_NORTH_PIPE_AND_PORT) 676 #define SKL_DPLL3_CFGCR2 (0xc054 | REGS_NORTH_PIPE_AND_PORT) 677 // These exist also still in CoffeeLake (confirmed): 678 #define SKL_DPLL_CTRL1 (0xc058 | REGS_NORTH_PIPE_AND_PORT) 679 #define SKL_DPLL_CTRL2 (0xc05c | REGS_NORTH_PIPE_AND_PORT) 680 #define SKL_DPLL_STATUS (0xc060 | REGS_NORTH_PIPE_AND_PORT) 681 #define SKL_DPLL0_DP_LINKRATE_SHIFT 1 682 #define SKL_DPLL1_DP_LINKRATE_SHIFT 7 683 #define SKL_DPLL2_DP_LINKRATE_SHIFT 13 684 #define SKL_DPLL3_DP_LINKRATE_SHIFT 19 685 #define SKL_DPLL_DP_LINKRATE_MASK 7 686 #define SKL_DPLL_CTRL1_2700 0 687 #define SKL_DPLL_CTRL1_1350 1 688 #define SKL_DPLL_CTRL1_810 2 689 #define SKL_DPLL_CTRL1_1620 3 690 #define SKL_DPLL_CTRL1_1080 4 691 #define SKL_DPLL_CTRL1_2160 5 692 693 // Icelake PLLs 694 #define ICL_DSSM 0x51004 695 #define ICL_DSSM_REF_FREQ_SHIFT 29 696 #define ICL_DSSM_REF_FREQ_MASK (7 << ICL_DSSM_REF_FREQ_SHIFT) 697 #define ICL_DSSM_24000 0 698 #define ICL_DSSM_19200 1 699 #define ICL_DSSM_38400 2 700 701 // display 702 703 #define INTEL_DISPLAY_OFFSET 0x1000 704 705 // Note: on Skylake below registers are part of the transcoder 706 #define INTEL_DISPLAY_A_HTOTAL (0x0000 | REGS_NORTH_PIPE_AND_PORT) 707 #define INTEL_DISPLAY_A_HBLANK (0x0004 | REGS_NORTH_PIPE_AND_PORT) 708 #define INTEL_DISPLAY_A_HSYNC (0x0008 | REGS_NORTH_PIPE_AND_PORT) 709 #define INTEL_DISPLAY_A_VTOTAL (0x000c | REGS_NORTH_PIPE_AND_PORT) 710 #define INTEL_DISPLAY_A_VBLANK (0x0010 | REGS_NORTH_PIPE_AND_PORT) 711 #define INTEL_DISPLAY_A_VSYNC (0x0014 | REGS_NORTH_PIPE_AND_PORT) 712 #define INTEL_DISPLAY_B_HTOTAL (0x1000 | REGS_NORTH_PIPE_AND_PORT) 713 #define INTEL_DISPLAY_B_HBLANK (0x1004 | REGS_NORTH_PIPE_AND_PORT) 714 #define INTEL_DISPLAY_B_HSYNC (0x1008 | REGS_NORTH_PIPE_AND_PORT) 715 #define INTEL_DISPLAY_B_VTOTAL (0x100c | REGS_NORTH_PIPE_AND_PORT) 716 #define INTEL_DISPLAY_B_VBLANK (0x1010 | REGS_NORTH_PIPE_AND_PORT) 717 #define INTEL_DISPLAY_B_VSYNC (0x1014 | REGS_NORTH_PIPE_AND_PORT) 718 719 #define INTEL_DISPLAY_A_PIPE_SIZE (0x001c | REGS_NORTH_PIPE_AND_PORT) 720 #define INTEL_DISPLAY_B_PIPE_SIZE (0x101c | REGS_NORTH_PIPE_AND_PORT) 721 722 //G45 displayport link 723 #define INTEL_PIPE_A_DATA_M (0x0050 | REGS_NORTH_PLANE_CONTROL) 724 #define INTEL_PIPE_B_DATA_M (0x1050 | REGS_NORTH_PLANE_CONTROL) 725 #define INTEL_PIPE_A_DATA_N (0x0054 | REGS_NORTH_PLANE_CONTROL) 726 #define INTEL_PIPE_B_DATA_N (0x1054 | REGS_NORTH_PLANE_CONTROL) 727 #define INTEL_PIPE_A_LINK_M (0x0060 | REGS_NORTH_PLANE_CONTROL) 728 #define INTEL_PIPE_B_LINK_M (0x1060 | REGS_NORTH_PLANE_CONTROL) 729 #define INTEL_PIPE_A_LINK_N (0x0064 | REGS_NORTH_PLANE_CONTROL) 730 #define INTEL_PIPE_B_LINK_N (0x1064 | REGS_NORTH_PLANE_CONTROL) 731 732 //DDI port link 733 #define INTEL_DDI_PIPE_A_DATA_M (0x0030 | REGS_NORTH_PIPE_AND_PORT) 734 #define INTEL_DDI_PIPE_B_DATA_M (0x1030 | REGS_NORTH_PIPE_AND_PORT) 735 #define INTEL_DDI_PIPE_A_DATA_N (0x0034 | REGS_NORTH_PIPE_AND_PORT) 736 #define INTEL_DDI_PIPE_B_DATA_N (0x1034 | REGS_NORTH_PIPE_AND_PORT) 737 #define INTEL_DDI_PIPE_A_LINK_M (0x0040 | REGS_NORTH_PIPE_AND_PORT) 738 #define INTEL_DDI_PIPE_B_LINK_M (0x1040 | REGS_NORTH_PIPE_AND_PORT) 739 #define INTEL_DDI_PIPE_A_LINK_N (0x0044 | REGS_NORTH_PIPE_AND_PORT) 740 #define INTEL_DDI_PIPE_B_LINK_N (0x1044 | REGS_NORTH_PIPE_AND_PORT) 741 742 // on PCH we also have to set the transcoder 743 #define INTEL_TRANSCODER_A_HTOTAL (0x0000 | REGS_SOUTH_TRANSCODER_PORT) 744 #define INTEL_TRANSCODER_A_HBLANK (0x0004 | REGS_SOUTH_TRANSCODER_PORT) 745 #define INTEL_TRANSCODER_A_HSYNC (0x0008 | REGS_SOUTH_TRANSCODER_PORT) 746 #define INTEL_TRANSCODER_A_VTOTAL (0x000c | REGS_SOUTH_TRANSCODER_PORT) 747 #define INTEL_TRANSCODER_A_VBLANK (0x0010 | REGS_SOUTH_TRANSCODER_PORT) 748 #define INTEL_TRANSCODER_A_VSYNC (0x0014 | REGS_SOUTH_TRANSCODER_PORT) 749 #define INTEL_TRANSCODER_B_HTOTAL (0x1000 | REGS_SOUTH_TRANSCODER_PORT) 750 #define INTEL_TRANSCODER_B_HBLANK (0x1004 | REGS_SOUTH_TRANSCODER_PORT) 751 #define INTEL_TRANSCODER_B_HSYNC (0x1008 | REGS_SOUTH_TRANSCODER_PORT) 752 #define INTEL_TRANSCODER_B_VTOTAL (0x100c | REGS_SOUTH_TRANSCODER_PORT) 753 #define INTEL_TRANSCODER_B_VBLANK (0x1010 | REGS_SOUTH_TRANSCODER_PORT) 754 #define INTEL_TRANSCODER_B_VSYNC (0x1014 | REGS_SOUTH_TRANSCODER_PORT) 755 756 // transcoder M/N DATA AND LINK VALUES (refreshrate) 757 #define INTEL_TRANSCODER_A_DATA_M1 (0x0030 | REGS_SOUTH_TRANSCODER_PORT) 758 #define INTEL_TRANSCODER_A_DATA_M2 (0x0038 | REGS_SOUTH_TRANSCODER_PORT) 759 #define INTEL_TRANSCODER_B_DATA_M1 (0x1030 | REGS_SOUTH_TRANSCODER_PORT) 760 #define INTEL_TRANSCODER_B_DATA_M2 (0x1038 | REGS_SOUTH_TRANSCODER_PORT) 761 #define INTEL_TRANSCODER_C_DATA_M1 (0x2030 | REGS_SOUTH_TRANSCODER_PORT) 762 #define INTEL_TRANSCODER_C_DATA_M2 (0x2038 | REGS_SOUTH_TRANSCODER_PORT) 763 #define INTEL_TRANSCODER_A_DATA_N1 (0x0034 | REGS_SOUTH_TRANSCODER_PORT) 764 #define INTEL_TRANSCODER_A_DATA_N2 (0x003c | REGS_SOUTH_TRANSCODER_PORT) 765 #define INTEL_TRANSCODER_B_DATA_N1 (0x1034 | REGS_SOUTH_TRANSCODER_PORT) 766 #define INTEL_TRANSCODER_B_DATA_N2 (0x103c | REGS_SOUTH_TRANSCODER_PORT) 767 #define INTEL_TRANSCODER_C_DATA_N1 (0x2034 | REGS_SOUTH_TRANSCODER_PORT) 768 #define INTEL_TRANSCODER_C_DATA_N2 (0x203c | REGS_SOUTH_TRANSCODER_PORT) 769 #define INTEL_TRANSCODER_A_LINK_M1 (0x0040 | REGS_SOUTH_TRANSCODER_PORT) 770 #define INTEL_TRANSCODER_A_LINK_M2 (0x0048 | REGS_SOUTH_TRANSCODER_PORT) 771 #define INTEL_TRANSCODER_B_LINK_M1 (0x1040 | REGS_SOUTH_TRANSCODER_PORT) 772 #define INTEL_TRANSCODER_B_LINK_M2 (0x1048 | REGS_SOUTH_TRANSCODER_PORT) 773 #define INTEL_TRANSCODER_C_LINK_M1 (0x2040 | REGS_SOUTH_TRANSCODER_PORT) 774 #define INTEL_TRANSCODER_C_LINK_M2 (0x2048 | REGS_SOUTH_TRANSCODER_PORT) 775 #define INTEL_TRANSCODER_A_LINK_N1 (0x0044 | REGS_SOUTH_TRANSCODER_PORT) 776 #define INTEL_TRANSCODER_A_LINK_N2 (0x004c | REGS_SOUTH_TRANSCODER_PORT) 777 #define INTEL_TRANSCODER_B_LINK_N1 (0x1044 | REGS_SOUTH_TRANSCODER_PORT) 778 #define INTEL_TRANSCODER_B_LINK_N2 (0x104c | REGS_SOUTH_TRANSCODER_PORT) 779 #define INTEL_TRANSCODER_C_LINK_N1 (0x2044 | REGS_SOUTH_TRANSCODER_PORT) 780 #define INTEL_TRANSCODER_C_LINK_N2 (0x204c | REGS_SOUTH_TRANSCODER_PORT) 781 #define INTEL_TRANSCODER_MN_TU_SIZE_MASK (0x3f << 25) 782 #define INTEL_TRANSCODER_MN_VALUE_MASK (0xffffff << 0) 783 784 #define INTEL_TRANSCODER_A_IMAGE_SIZE (0x001c | REGS_SOUTH_TRANSCODER_PORT) 785 #define INTEL_TRANSCODER_B_IMAGE_SIZE (0x101c | REGS_SOUTH_TRANSCODER_PORT) 786 787 // TODO: Is there consolidation that could happen here with digital ports? 788 789 #define INTEL_ANALOG_PORT (0x1100 | REGS_SOUTH_TRANSCODER_PORT) 790 #define INTEL_DIGITAL_PORT_A (0x1120 | REGS_SOUTH_TRANSCODER_PORT) 791 #define INTEL_DIGITAL_PORT_B (0x1140 | REGS_SOUTH_TRANSCODER_PORT) 792 #define INTEL_DIGITAL_PORT_C (0x1160 | REGS_SOUTH_TRANSCODER_PORT) 793 #define INTEL_DIGITAL_LVDS_PORT (0x1180 | REGS_SOUTH_TRANSCODER_PORT) 794 795 #define INTEL_HDMI_PORT_B (0x1140 | REGS_SOUTH_TRANSCODER_PORT) 796 #define INTEL_HDMI_PORT_C (0x1160 | REGS_SOUTH_TRANSCODER_PORT) 797 798 #define PCH_HDMI_PORT_B (0x1140 | REGS_SOUTH_TRANSCODER_PORT) 799 #define PCH_HDMI_PORT_C (0x1150 | REGS_SOUTH_TRANSCODER_PORT) 800 #define PCH_HDMI_PORT_D (0x1160 | REGS_SOUTH_TRANSCODER_PORT) 801 802 #define GEN4_HDMI_PORT_B (0x1140 | REGS_SOUTH_TRANSCODER_PORT) 803 #define GEN4_HDMI_PORT_C (0x1160 | REGS_SOUTH_TRANSCODER_PORT) 804 #define CHV_HDMI_PORT_D (0x116C | REGS_SOUTH_TRANSCODER_PORT) 805 806 // DDI Buffer Control (This replaces DP on Haswell+) 807 #define DDI_BUF_CTL_A (0x4000 | REGS_NORTH_PIPE_AND_PORT) 808 #define DDI_BUF_CTL_B (0x4100 | REGS_NORTH_PIPE_AND_PORT) 809 #define DDI_BUF_CTL_C (0x4200 | REGS_NORTH_PIPE_AND_PORT) 810 #define DDI_BUF_CTL_D (0x4300 | REGS_NORTH_PIPE_AND_PORT) 811 #define DDI_BUF_CTL_E (0x4400 | REGS_NORTH_PIPE_AND_PORT) 812 #define DDI_BUF_CTL_F (0x4500 | REGS_NORTH_PIPE_AND_PORT) 813 #define DDI_BUF_CTL_ENABLE (1 << 31) 814 #define DDI_BUF_TRANS_SELECT(n) ((n) << 24) 815 #define DDI_BUF_EMP_MASK (0xf << 24) 816 #define DDI_BUF_PORT_REVERSAL (1 << 16) 817 #define DDI_BUF_IS_IDLE (1 << 7) 818 #define DDI_A_4_LANES (1 << 4) 819 #define DDI_PORT_WIDTH(width) (((width) - 1) << 1) 820 #define DDI_INIT_DISPLAY_DETECTED (1 << 0) 821 822 #define PIPE_DDI_FUNC_CTL_A (0x0400 | REGS_NORTH_PIPE_AND_PORT) 823 #define PIPE_DDI_FUNC_CTL_B (0x1400 | REGS_NORTH_PIPE_AND_PORT) 824 #define PIPE_DDI_FUNC_CTL_C (0x2400 | REGS_NORTH_PIPE_AND_PORT) 825 #define PIPE_DDI_FUNC_CTL_EDP (0xF400 | REGS_NORTH_PIPE_AND_PORT) 826 #define PIPE_DDI_FUNC_CTL_ENABLE (1 << 31) 827 #define PIPE_DDI_SELECT_SHIFT 28 828 #define PIPE_DDI_SELECT_PORT(x) ((x) << PIPE_DDI_SELECT_SHIFT) 829 #define PIPE_DDI_SELECT_MASK (7 << PIPE_DDI_SELECT_SHIFT) 830 #define PIPE_DDI_PORT_NONE 0 831 #define PIPE_DDI_PORT_B 1 832 #define PIPE_DDI_PORT_C 2 833 #define PIPE_DDI_PORT_D 3 834 #define PIPE_DDI_PORT_E 4 835 #define PIPE_DDI_PORT_F 5 836 #define PIPE_DDI_MODESEL_SHIFT 24 837 #define PIPE_DDI_MODESEL_MODE(x) ((x) << PIPE_DDI_MODESEL_SHIFT) 838 #define PIPE_DDI_MODESEL_MASK (7 << PIPE_DDI_MODESEL_SHIFT) 839 #define PIPE_DDI_MODE_HDMI 0 840 #define PIPE_DDI_MODE_DVI 1 841 #define PIPE_DDI_MODE_DP_SST 2 842 #define PIPE_DDI_MODE_DP_MST 3 843 #define PIPE_DDI_COLOR_SHIFT 20 844 #define PIPE_DDI_BPC(x) ((x) << PIPE_DDI_COLOR_SHIFT) 845 #define PIPE_DDI_BPC_MASK (7 << PIPE_DDI_COLOR_SHIFT) 846 #define PIPE_DDI_8BPC 0 847 #define PIPE_DDI_10BPC 1 848 #define PIPE_DDI_6BPC 2 849 #define PIPE_DDI_12BPC 3 850 #define PIPE_DDI_DP_WIDTH_SHIFT 1 851 #define PIPE_DDI_DP_WIDTH_SEL(x) ((x) << PIPE_DDI_DP_WIDTH_SHIFT) 852 #define PIPE_DDI_DP_WIDTH_MASK (7 << PIPE_DDI_DP_WIDTH_SHIFT) 853 #define PIPE_DDI_DP_WIDTH_1 0 854 #define PIPE_DDI_DP_WIDTH_2 1 855 #define PIPE_DDI_DP_WIDTH_4 2 856 857 // DP_A always @ 6xxxx, DP_B-DP_D move with PCH 858 #define INTEL_DISPLAY_PORT_A (0x4000 | REGS_NORTH_PIPE_AND_PORT) 859 #define INTEL_DISPLAY_PORT_B (0x4100 | REGS_SOUTH_TRANSCODER_PORT) 860 #define INTEL_DISPLAY_PORT_C (0x4200 | REGS_SOUTH_TRANSCODER_PORT) 861 #define INTEL_DISPLAY_PORT_D (0x4300 | REGS_SOUTH_TRANSCODER_PORT) 862 863 #define INTEL_DISP_PORTA_SNB_PIPE_SHIFT 30 864 #define INTEL_DISP_PORTA_SNB_PIPE_MASK (1 << INTEL_DISP_PORTA_SNB_PIPE_SHIFT) 865 #define INTEL_DISP_PORTA_SNB_PIPE_A 0 866 #define INTEL_DISP_PORTA_SNB_PIPE_B 1 867 #define INTEL_DISP_PORTA_IVB_PIPE_SHIFT 29 868 #define INTEL_DISP_PORTA_IVB_PIPE_MASK (3 << INTEL_DISP_PORTA_IVB_PIPE_SHIFT) 869 #define INTEL_DISP_PORTA_IVB_PIPE_A 0 870 #define INTEL_DISP_PORTA_IVB_PIPE_B 1 871 #define INTEL_DISP_PORTA_IVB_PIPE_C 2 872 873 #define INTEL_DISP_PORT_WIDTH_SHIFT 19 874 #define INTEL_DISP_PORT_WIDTH_MASK (7 << INTEL_DISP_PORT_WIDTH_SHIFT) 875 #define INTEL_DISP_PORT_WIDTH_1 0 876 #define INTEL_DISP_PORT_WIDTH_2 1 877 #define INTEL_DISP_PORT_WIDTH_4 3 878 #define INTEL_DISP_EDP_PLL_FREQ_SHIFT 16 879 #define INTEL_DISP_EDP_PLL_FREQ_MASK (3 << INTEL_DISP_EDP_PLL_FREQ_SHIFT) 880 #define INTEL_DISP_EDP_PLL_FREQ_270 0 881 #define INTEL_DISP_EDP_PLL_FREQ_162 1 882 883 #define INTEL_TRANSCODER_A_DP_CTL (0x0300 | REGS_SOUTH_TRANSCODER_PORT) 884 #define INTEL_TRANSCODER_B_DP_CTL (0x1300 | REGS_SOUTH_TRANSCODER_PORT) 885 #define INTEL_TRANSCODER_C_DP_CTL (0x2300 | REGS_SOUTH_TRANSCODER_PORT) 886 887 #define INTEL_TRANS_DP_COLOR_SHIFT 9 888 #define INTEL_TRANS_DP_BPC(x) ((x) << INTEL_TRANS_DP_COLOR_SHIFT) 889 #define INTEL_TRANS_DP_BPC_MASK (7 << INTEL_TRANS_DP_COLOR_SHIFT) 890 #define INTEL_TRANS_DP_PORT_SHIFT 29 891 #define INTEL_TRANS_DP_PORT(x) ((x) << INTEL_TRANS_DP_PORT_SHIFT) 892 #define INTEL_TRANS_DP_PORT_MASK (3 << INTEL_TRANS_DP_PORT_SHIFT) 893 #define INTEL_TRANS_DP_PORT_B 0 894 #define INTEL_TRANS_DP_PORT_C 1 895 #define INTEL_TRANS_DP_PORT_D 2 896 #define INTEL_TRANS_DP_PORT_NONE 3 897 898 // Unless you're a damn Valley/CherryView unicorn :-( 899 #define VLV_DISPLAY_PORT_B (VLV_DISPLAY_BASE + 0x64100) 900 #define VLV_DISPLAY_PORT_C (VLV_DISPLAY_BASE + 0x64200) 901 #define CHV_DISPLAY_PORT_D (VLV_DISPLAY_BASE + 0x64300) 902 903 // DP AUX channels 904 #define INTEL_DP_AUX_CTL_A (0x4010 | REGS_NORTH_PIPE_AND_PORT) 905 #define INTEL_DP_AUX_CTL_B (0x4110 | REGS_SOUTH_TRANSCODER_PORT) 906 #define INTEL_DP_AUX_CTL_C (0x4210 | REGS_SOUTH_TRANSCODER_PORT) 907 #define INTEL_DP_AUX_CTL_D (0x4310 | REGS_SOUTH_TRANSCODER_PORT) 908 909 #define VLV_DP_AUX_CTL_B (VLV_DISPLAY_BASE + 0x64110) 910 #define VLV_DP_AUX_CTL_C (VLV_DISPLAY_BASE + 0x64210) 911 #define CHV_DP_AUX_CTL_D (VLV_DISPLAY_BASE + 0x64310) 912 913 #define INTEL_DP_AUX_CTL_BUSY (1 << 31) 914 #define INTEL_DP_AUX_CTL_DONE (1 << 30) 915 #define INTEL_DP_AUX_CTL_INTERRUPT (1 << 29) 916 #define INTEL_DP_AUX_CTL_TIMEOUT_ERROR (1 << 28) 917 #define INTEL_DP_AUX_CTL_TIMEOUT_400us (0 << 26) 918 #define INTEL_DP_AUX_CTL_TIMEOUT_600us (1 << 26) 919 #define INTEL_DP_AUX_CTL_TIMEOUT_800us (2 << 26) 920 #define INTEL_DP_AUX_CTL_TIMEOUT_1600us (3 << 26) 921 #define INTEL_DP_AUX_CTL_TIMEOUT_MASK (3 << 26) 922 #define INTEL_DP_AUX_CTL_RECEIVE_ERROR (1 << 25) 923 #define INTEL_DP_AUX_CTL_MSG_SIZE_MASK (0x1f << 20) 924 #define INTEL_DP_AUX_CTL_MSG_SIZE_SHIFT 20 925 #define INTEL_DP_AUX_CTL_PRECHARGE_2US_MASK (0xf << 16) 926 #define INTEL_DP_AUX_CTL_PRECHARGE_2US_SHIFT 16 927 #define INTEL_DP_AUX_CTL_BIT_CLOCK_2X_MASK (0x7ff) 928 #define INTEL_DP_AUX_CTL_BIT_CLOCK_2X_SHIFT 0 929 #define INTEL_DP_AUX_CTL_SYNC_PULSE_SKL(c) ((c) - 1) 930 931 // planes 932 #define INTEL_PIPE_ENABLED (1UL << 31) 933 #define INTEL_PIPE_STATE (1UL << 30) 934 935 #define INTEL_PLANE_OFFSET 0x1000 936 937 #define INTEL_DISPLAY_A_PIPE_CONTROL (0x0008 | REGS_NORTH_PLANE_CONTROL) 938 #define INTEL_DISPLAY_B_PIPE_CONTROL (0x1008 | REGS_NORTH_PLANE_CONTROL) 939 #define INTEL_DISPLAY_C_PIPE_CONTROL (0x2008 | REGS_NORTH_PLANE_CONTROL) 940 #define INTEL_DISPLAY_A_PIPE_STATUS (0x0024 | REGS_NORTH_PLANE_CONTROL) 941 #define INTEL_DISPLAY_B_PIPE_STATUS (0x1024 | REGS_NORTH_PLANE_CONTROL) 942 943 #define INTEL_DISPLAY_A_PIPE_WATERMARK (0x5100 | REGS_NORTH_PLANE_CONTROL) 944 #define INTEL_DISPLAY_B_PIPE_WATERMARK (0x5104 | REGS_NORTH_PLANE_CONTROL) 945 #define INTEL_DISPLAY_C_PIPE_WATERMARK (0x5200 | REGS_NORTH_PLANE_CONTROL) 946 947 #define DISPLAY_PIPE_VBLANK_ENABLED (1UL << 17) 948 #define DISPLAY_PIPE_VBLANK_STATUS (1UL << 1) 949 950 #define INTEL_DISPLAY_A_CONTROL (0x0180 | REGS_NORTH_PLANE_CONTROL) 951 #define INTEL_DISPLAY_A_BASE (0x0184 | REGS_NORTH_PLANE_CONTROL) 952 #define INTEL_DISPLAY_A_BYTES_PER_ROW (0x0188 | REGS_NORTH_PLANE_CONTROL) 953 #define INTEL_DISPLAY_A_POS (0x018c | REGS_NORTH_PLANE_CONTROL) 954 // reserved on A 955 #define INTEL_DISPLAY_A_IMAGE_SIZE (0x0190 | REGS_NORTH_PLANE_CONTROL) 956 #define INTEL_DISPLAY_A_SURFACE (0x019c | REGS_NORTH_PLANE_CONTROL) 957 #define INTEL_DISPLAY_A_OFFSET_HAS (0x01a4 | REGS_NORTH_PLANE_CONTROL) 958 // i965 and up only 959 960 #define INTEL_DISPLAY_B_CONTROL (0x1180 | REGS_NORTH_PLANE_CONTROL) 961 #define INTEL_DISPLAY_B_BASE (0x1184 | REGS_NORTH_PLANE_CONTROL) 962 #define INTEL_DISPLAY_B_BYTES_PER_ROW (0x1188 | REGS_NORTH_PLANE_CONTROL) 963 #define INTEL_DISPLAY_B_POS (0x118c | REGS_NORTH_PLANE_CONTROL) 964 #define INTEL_DISPLAY_B_IMAGE_SIZE (0x1190 | REGS_NORTH_PLANE_CONTROL) 965 #define INTEL_DISPLAY_B_SURFACE (0x119c | REGS_NORTH_PLANE_CONTROL) 966 #define INTEL_DISPLAY_B_OFFSET_HAS (0x11a4 | REGS_NORTH_PLANE_CONTROL) 967 // i965 and up only 968 969 // INTEL_DISPLAY_A_CONTROL source pixel format 970 #define DISPLAY_CONTROL_ENABLED (1UL << 31) 971 #define DISPLAY_CONTROL_GAMMA (1UL << 30) 972 #define DISPLAY_CONTROL_COLOR_MASK (0x0fUL << 26) 973 #define DISPLAY_CONTROL_CMAP8 (2UL << 26) 974 #define DISPLAY_CONTROL_RGB15 (4UL << 26) 975 #define DISPLAY_CONTROL_RGB16 (5UL << 26) 976 #define DISPLAY_CONTROL_RGB32 (6UL << 26) 977 #define DISPLAY_CONTROL_RGB64 (0x0cUL << 26) 978 // Skylake 979 #define DISPLAY_CONTROL_COLOR_MASK_SKY (0x0fUL << 24) 980 #define DISPLAY_CONTROL_CMAP8_SKY (0x0cUL << 24) 981 #define DISPLAY_CONTROL_RGB15_SKY (0x0eUL << 24) 982 #define DISPLAY_CONTROL_RGB16_SKY (0x0eUL << 24) 983 #define DISPLAY_CONTROL_RGB32_SKY (0x04UL << 24) 984 #define DISPLAY_CONTROL_RGB64_SKY (0x06UL << 24) 985 986 // INTEL_DISPLAY_A_PIPE_CONTROL ILK+ 987 #define INTEL_PIPE_DITHER_TYPE_MASK (0x0000000c) 988 #define INTEL_PIPE_DITHER_TYPE_SP (0 << 2) 989 #define INTEL_PIPE_DITHER_TYPE_ST1 (1 << 2) 990 #define INTEL_PIPE_DITHER_TYPE_ST2 (2 << 2) 991 #define INTEL_PIPE_DITHER_TYPE_TEMP (3 << 2) 992 #define INTEL_PIPE_DITHER_EN (1 << 4) 993 #define INTEL_PIPE_COLOR_SHIFT 5 994 #define INTEL_PIPE_BPC(x) ((x) << INTEL_PIPE_COLOR_SHIFT) 995 #define INTEL_PIPE_BPC_MASK (7 << INTEL_PIPE_COLOR_SHIFT) 996 #define INTEL_PIPE_8BPC 0 997 #define INTEL_PIPE_10BPC 1 998 #define INTEL_PIPE_6BPC 2 999 #define INTEL_PIPE_12BPC 3 1000 #define INTEL_PIPE_PROGRESSIVE (0 << 21) 1001 1002 // cursors 1003 #define INTEL_CURSOR_CONTROL (0x0080 | REGS_NORTH_PLANE_CONTROL) 1004 #define INTEL_CURSOR_BASE (0x0084 | REGS_NORTH_PLANE_CONTROL) 1005 #define INTEL_CURSOR_POSITION (0x0088 | REGS_NORTH_PLANE_CONTROL) 1006 #define INTEL_CURSOR_PALETTE (0x0090 | REGS_NORTH_PLANE_CONTROL) 1007 // (- 0x009f) 1008 #define INTEL_CURSOR_SIZE (0x00a0 | REGS_NORTH_PLANE_CONTROL) 1009 #define CURSOR_ENABLED (1UL << 31) 1010 #define CURSOR_FORMAT_2_COLORS (0UL << 24) 1011 #define CURSOR_FORMAT_3_COLORS (1UL << 24) 1012 #define CURSOR_FORMAT_4_COLORS (2UL << 24) 1013 #define CURSOR_FORMAT_ARGB (4UL << 24) 1014 #define CURSOR_FORMAT_XRGB (5UL << 24) 1015 #define CURSOR_POSITION_NEGATIVE 0x8000 1016 #define CURSOR_POSITION_MASK 0x3fff 1017 1018 // palette registers 1019 #define INTEL_DISPLAY_A_PALETTE (0xa000 | REGS_NORTH_SHARED) 1020 #define INTEL_DISPLAY_B_PALETTE (0xa800 | REGS_NORTH_SHARED) 1021 1022 // Ironlake PCH reference clk control 1023 #define PCH_DREF_CONTROL (0x6200 | REGS_SOUTH_SHARED) 1024 #define DREF_CONTROL_MASK 0x7fc3 1025 #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0 << 13) 1026 #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2 << 13) 1027 #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3 << 13) 1028 #define DREF_CPU_SOURCE_OUTPUT_MASK (3 << 13) 1029 #define DREF_SSC_SOURCE_DISABLE (0 << 11) 1030 #define DREF_SSC_SOURCE_ENABLE (2 << 11) 1031 #define DREF_SSC_SOURCE_MASK (3 << 11) 1032 #define DREF_NONSPREAD_SOURCE_DISABLE (0 << 9) 1033 #define DREF_NONSPREAD_CK505_ENABLE (1 << 9) 1034 #define DREF_NONSPREAD_SOURCE_ENABLE (2 << 9) 1035 #define DREF_NONSPREAD_SOURCE_MASK (3 << 9) 1036 #define DREF_SUPERSPREAD_SOURCE_DISABLE (0 << 7) 1037 #define DREF_SUPERSPREAD_SOURCE_ENABLE (2 << 7) 1038 #define DREF_SUPERSPREAD_SOURCE_MASK (3 << 7) 1039 #define DREF_SSC4_DOWNSPREAD (0 << 6) 1040 #define DREF_SSC4_CENTERSPREAD (1 << 6) 1041 #define DREF_SSC1_DISABLE (0 << 1) 1042 #define DREF_SSC1_ENABLE (1 << 1) 1043 #define DREF_SSC4_DISABLE (0 << 0) 1044 #define DREF_SSC4_ENABLE (1 << 0) 1045 1046 // PLL registers 1047 // Multiplier Divisor 1048 #define INTEL_DISPLAY_A_PLL (0x6014 | REGS_SOUTH_SHARED) 1049 #define INTEL_DISPLAY_B_PLL (0x6018 | REGS_SOUTH_SHARED) 1050 #define INTEL_DISPLAY_A_PLL_MD (0x601C | REGS_SOUTH_SHARED) 1051 #define INTEL_DISPLAY_B_PLL_MD (0x6020 | REGS_SOUTH_SHARED) 1052 #define CHV_DISPLAY_C_PLL (0x6030 | REGS_SOUTH_SHARED) 1053 #define CHV_DISPLAY_B_PLL_MD (0x603C | REGS_SOUTH_SHARED) 1054 1055 #define INTEL_DISPLAY_A_PLL_DIVISOR_0 (0x6040 | REGS_SOUTH_SHARED) 1056 #define INTEL_DISPLAY_A_PLL_DIVISOR_1 (0x6044 | REGS_SOUTH_SHARED) 1057 #define INTEL_DISPLAY_B_PLL_DIVISOR_0 (0x6048 | REGS_SOUTH_SHARED) 1058 #define INTEL_DISPLAY_B_PLL_DIVISOR_1 (0x604c | REGS_SOUTH_SHARED) 1059 1060 #define SNB_DPLL_SEL (0x7000 | REGS_SOUTH_SHARED) 1061 1062 // i2c bit banging interface 1063 #define INTEL_I2C_IO_A (0x5010 | REGS_SOUTH_SHARED) 1064 #define INTEL_I2C_IO_B (0x5014 | REGS_SOUTH_SHARED) 1065 #define INTEL_I2C_IO_C (0x5018 | REGS_SOUTH_SHARED) 1066 #define INTEL_I2C_IO_D (0x501c | REGS_SOUTH_SHARED) 1067 #define INTEL_I2C_IO_E (0x5020 | REGS_SOUTH_SHARED) 1068 #define INTEL_I2C_IO_F (0x5024 | REGS_SOUTH_SHARED) 1069 #define INTEL_I2C_IO_G (0x5028 | REGS_SOUTH_SHARED) 1070 #define INTEL_I2C_IO_H (0x502c | REGS_SOUTH_SHARED) 1071 // i2c hardware controller 1072 #define INTEL_GMBUS0 (0x5100 | REGS_SOUTH_SHARED) 1073 #define INTEL_GMBUS4 (0x5110 | REGS_SOUTH_SHARED) 1074 1075 #define I2C_CLOCK_DIRECTION_MASK (1 << 0) 1076 #define I2C_CLOCK_DIRECTION_OUT (1 << 1) 1077 #define I2C_CLOCK_VALUE_MASK (1 << 2) 1078 #define I2C_CLOCK_VALUE_OUT (1 << 3) 1079 #define I2C_CLOCK_VALUE_IN (1 << 4) 1080 #define I2C_DATA_DIRECTION_MASK (1 << 8) 1081 #define I2C_DATA_DIRECTION_OUT (1 << 9) 1082 #define I2C_DATA_VALUE_MASK (1 << 10) 1083 #define I2C_DATA_VALUE_OUT (1 << 11) 1084 #define I2C_DATA_VALUE_IN (1 << 12) 1085 #define I2C_RESERVED ((1 << 13) | (1 << 5)) 1086 1087 // gpu block clock gating disable bits 1088 #define INTEL_DSPCLK_GATE_D (0x2020 | REGS_SOUTH_SHARED) 1089 #define PCH_GMBUSUNIT_CLK_GATE_DIS (1UL << 31) 1090 #define INTEL_GEN9_CLKGATE_DIS_4 (0x653c | REGS_NORTH_SHARED) 1091 #define BXT_GMBUSUNIT_CLK_GATE_DIS (1 << 14) 1092 1093 // gpu power wells (confirmed skylake) 1094 #define INTEL_PWR_WELL_CTL_1_BIOS (0x5400 | REGS_NORTH_SHARED) 1095 #define INTEL_PWR_WELL_CTL_2_DRIVER (0x5404 | REGS_NORTH_SHARED) 1096 1097 // gpu pll enable registers (confirmed skylake) 1098 #define INTEL_WRPLL_CTL_1_DPLL2 (0x6040 | REGS_NORTH_SHARED) 1099 #define INTEL_WRPLL_CTL_2_DPLL3 (0x6060 | REGS_NORTH_SHARED) 1100 #define WRPLL_PLL_ENABLE (1 << 31) 1101 1102 // TODO: on IronLake this is in the north shared block at 0x41000 1103 #define INTEL_VGA_DISPLAY_CONTROL (0x1400 | REGS_NORTH_PLANE_CONTROL) 1104 #define VGA_DISPLAY_DISABLED (1UL << 31) 1105 1106 // LVDS panel 1107 #define INTEL_PANEL_STATUS (0x1200 | REGS_NORTH_PIPE_AND_PORT) 1108 #define INTEL_PANEL_CONTROL (0x1204 | REGS_NORTH_PIPE_AND_PORT) 1109 #define INTEL_PANEL_FIT_CONTROL (0x1230 | REGS_NORTH_PIPE_AND_PORT) 1110 #define INTEL_PANEL_FIT_RATIOS (0x1234 | REGS_NORTH_PIPE_AND_PORT) 1111 1112 // LVDS on IronLake and up 1113 #define PCH_PANEL_STATUS (0x7200 | REGS_SOUTH_SHARED) 1114 #define PCH_PANEL_CONTROL (0x7204 | REGS_SOUTH_SHARED) 1115 #define PCH_PANEL_ON_DELAYS (0x7208 | REGS_SOUTH_SHARED) 1116 #define PCH_PANEL_OFF_DELAYS (0x720c | REGS_SOUTH_SHARED) 1117 #define PCH_PANEL_DIVISOR (0x7210 | REGS_SOUTH_SHARED) 1118 #define PCH_LVDS_DETECTED (1 << 1) 1119 1120 #define PANEL_STATUS_POWER_ON (1UL << 31) 1121 #define PANEL_CONTROL_POWER_TARGET_OFF (0UL << 0) 1122 #define PANEL_CONTROL_POWER_TARGET_ON (1UL << 0) 1123 #define PANEL_CONTROL_POWER_TARGET_RST (1UL << 1) 1124 #define PANEL_REGISTER_UNLOCK (0xabcd << 16) 1125 1126 // PCH_PANEL_ON_DELAYS 1127 #define PANEL_DELAY_PORT_SELECT_MASK (3 << 30) 1128 #define PANEL_DELAY_PORT_SELECT_LVDS (0 << 30) 1129 #define PANEL_DELAY_PORT_SELECT_DPA (1 << 30) 1130 #define PANEL_DELAY_PORT_SELECT_DPC (2 << 30) 1131 #define PANEL_DELAY_PORT_SELECT_DPD (3 << 30) 1132 1133 // PCH_PANEL_DIVISOR 1134 #define PANEL_DIVISOR_REFERENCE_DIV_MASK 0xffffff00 1135 #define PANEL_DIVISOR_REFERENCE_DIV_SHIFT 8 1136 #define PANEL_DIVISOR_POW_CYCLE_DLY_MASK 0x1f 1137 #define PANEL_DIVISOR_POW_CYCLE_DLY_SHIFT 0x1f 1138 1139 // Backlight control registers 1140 #define PCH_BLC_PWM_CTL2 (0x8250 | REGS_NORTH_SHARED) 1141 #define PCH_BLC_PWM_CTL (0x8254 | REGS_NORTH_SHARED) 1142 #define PCH_SBLC_PWM_CTL2 (0x8254 | REGS_SOUTH_SHARED) 1143 1144 #define MCH_BLC_PWM_CTL (0x1254 | REGS_NORTH_PIPE_AND_PORT) 1145 1146 // ring buffer commands 1147 1148 #define COMMAND_NOOP 0x00 1149 #define COMMAND_WAIT_FOR_EVENT (0x03 << 23) 1150 #define COMMAND_WAIT_FOR_OVERLAY_FLIP (1 << 16) 1151 1152 #define COMMAND_FLUSH (0x04 << 23) 1153 1154 // overlay flip 1155 #define COMMAND_OVERLAY_FLIP (0x11 << 23) 1156 #define COMMAND_OVERLAY_CONTINUE (0 << 21) 1157 #define COMMAND_OVERLAY_ON (1 << 21) 1158 #define COMMAND_OVERLAY_OFF (2 << 21) 1159 #define OVERLAY_UPDATE_COEFFICIENTS 0x1 1160 1161 // 2D acceleration 1162 #define XY_COMMAND_SOURCE_BLIT 0x54c00006 1163 #define XY_COMMAND_COLOR_BLIT 0x54000004 1164 #define XY_COMMAND_SETUP_MONO_PATTERN 0x44400007 1165 #define XY_COMMAND_SCANLINE_BLIT 0x49400001 1166 #define COMMAND_COLOR_BLIT 0x50000003 1167 #define COMMAND_BLIT_RGBA 0x00300000 1168 1169 #define COMMAND_MODE_SOLID_PATTERN 0x80 1170 #define COMMAND_MODE_CMAP8 0x00 1171 #define COMMAND_MODE_RGB15 0x02 1172 #define COMMAND_MODE_RGB16 0x01 1173 #define COMMAND_MODE_RGB32 0x03 1174 1175 // overlay 1176 #define INTEL_OVERLAY_UPDATE 0x30000 1177 #define INTEL_OVERLAY_TEST 0x30004 1178 #define INTEL_OVERLAY_STATUS 0x30008 1179 #define INTEL_OVERLAY_EXTENDED_STATUS 0x3000c 1180 #define INTEL_OVERLAY_GAMMA_5 0x30010 1181 #define INTEL_OVERLAY_GAMMA_4 0x30014 1182 #define INTEL_OVERLAY_GAMMA_3 0x30018 1183 #define INTEL_OVERLAY_GAMMA_2 0x3001c 1184 #define INTEL_OVERLAY_GAMMA_1 0x30020 1185 #define INTEL_OVERLAY_GAMMA_0 0x30024 1186 1187 // FDI - Flexible Display Interface, the interface between the (CPU-internal) 1188 // GPU and the PCH display outputs. Proprietary interface, based on DisplayPort 1189 // though, so similar link training and all... 1190 // There's an FDI transmitter (TX) on the CPU and an FDI receiver (RX) on the 1191 // PCH for each display pipe. 1192 // FDI receiver A is hooked up to transcoder A, FDI receiver B is hooked up to 1193 // transcoder B, so we have the same mapping as with the display pipes. 1194 #define PCH_FDI_RX_BASE_REGISTER 0xf0000 1195 #define PCH_FDI_RX_PIPE_OFFSET 0x01000 1196 #define PCH_FDI_RX_CONTROL 0x00c 1197 #define PCH_FDI_RX_MISC 0x010 1198 #define PCH_FDI_RX_IIR 0x014 1199 #define PCH_FDI_RX_IMR 0x018 1200 1201 #define FDI_RX_ENABLE (1 << 31) 1202 #define FDI_RX_PLL_ENABLED (1 << 13) 1203 1204 #define FDI_RX_LINK_COLOR_SHIFT 16 1205 #define FDI_RX_LINK_BPC(x) ((x) << FDI_RX_LINK_COLOR_SHIFT) 1206 #define FDI_RX_LINK_BPC_MASK (7 << FDI_RX_LINK_COLOR_SHIFT) 1207 1208 // Transcoder - same base as FDI_RX 1209 #define PCH_TRANS_CONF_A 0x0008 1210 #define PCH_TRANS_CONF_B 0x1008 1211 #define PCH_TRANS_CONF_C 0x2008 1212 1213 // Transcoder - skylake DDI 1214 #define DDI_SKL_TRANS_CONF_A (0x0008 | REGS_NORTH_PLANE_CONTROL) 1215 #define DDI_SKL_TRANS_CONF_B (0x1008 | REGS_NORTH_PLANE_CONTROL) 1216 #define DDI_SKL_TRANS_CONF_C (0x2008 | REGS_NORTH_PLANE_CONTROL) 1217 #define DDI_SKL_TRANS_CONF_EDP (0xf008 | REGS_NORTH_PLANE_CONTROL) 1218 1219 #define TRANS_ENABLE (1 << 31) 1220 #define TRANS_ENABLED (1 << 30) 1221 1222 // FDI_tX interrupt register 1223 #define FDI_RX_INTER_LANE_ALIGN (1 << 10) 1224 #define FDI_RX_SYMBOL_LOCK (1 << 9) 1225 #define FDI_RX_BIT_LOCK (1 << 8) 1226 #define FDI_RX_TRAIN_PATTERN_2_FAIL (1 << 7) 1227 #define FDI_RX_FS_CODE_ERR (1 << 6) 1228 #define FDI_RX_FE_CODE_ERR (1 << 5) 1229 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1 << 4) 1230 #define FDI_RX_HDCP_LINK_FAIL (1 << 3) 1231 #define FDI_RX_PIXEL_FIFO_OVERFLOW (1 << 2) 1232 #define FDI_RX_CROSS_CLOCK_OVERFLOW (1 << 1) 1233 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1 << 0) 1234 1235 #define FDI_FS_ERRC_ENABLE (1 << 27) 1236 #define FDI_FE_ERRC_ENABLE (1 << 26) 1237 1238 #define PCH_FDI_RX_TRANS_UNIT_SIZE_1 0x30 1239 #define PCH_FDI_RX_TRANS_UNIT_SIZE_2 0x38 1240 #define FDI_RX_TRANS_UNIT_SIZE(x) ((x - 1) << 25) 1241 #define FDI_RX_TRANS_UNIT_MASK 0x7e000000 1242 1243 #define FDI_RX_ENHANCE_FRAME_ENABLE (1 << 6) 1244 #define FDI_RX_CLOCK_MASK (1 << 4) 1245 #define FDI_RX_CLOCK_RAW (0 << 4) 1246 #define FDI_RX_CLOCK_PCD (1 << 4) 1247 1248 // FDI RX MISC 1249 #define FDI_RX_PWRDN_LANE1_MASK (3 << 26) 1250 #define FDI_RX_PWRDN_LANE1_VAL(x) ((x) << 26) 1251 #define FDI_RX_PWRDN_LANE0_MASK (3 << 24) 1252 #define FDI_RX_PWRDN_LANE0_VAL(x) ((x) << 24) 1253 #define FDI_RX_TP1_TO_TP2_48 (2 << 20) 1254 #define FDI_RX_TP1_TO_TP2_64 (3 << 20) 1255 #define FDI_RX_FDI_DELAY_90 (0x90 << 0) 1256 1257 #define PCH_FDI_TX_BASE_REGISTER 0x60000 1258 #define PCH_FDI_TX_PIPE_OFFSET 0x01000 1259 #define PCH_FDI_TX_CONTROL 0x100 1260 #define FDI_TX_ENABLE (1 << 31) 1261 #define FDI_LINK_TRAIN_PATTERN_1 (0 << 28) 1262 #define FDI_LINK_TRAIN_PATTERN_2 (1 << 28) 1263 #define FDI_LINK_TRAIN_PATTERN_IDLE (2 << 28) 1264 #define FDI_LINK_TRAIN_NONE (3 << 28) 1265 #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0 << 25) 1266 #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1 << 25) 1267 #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2 << 25) 1268 #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3 << 25) 1269 #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0 << 22) 1270 #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1 << 22) 1271 #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2 << 22) 1272 #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3 << 22) 1273 1274 // FDI/PIPE M/N DATA AND LINK VALUES (refreshrate) 1275 #define PCH_FDI_PIPE_A_DATA_M1 (0x0030 | REGS_NORTH_PIPE_AND_PORT) 1276 #define PCH_FDI_PIPE_A_DATA_M2 (0x0038 | REGS_NORTH_PIPE_AND_PORT) 1277 #define PCH_FDI_PIPE_B_DATA_M1 (0x1030 | REGS_NORTH_PIPE_AND_PORT) 1278 #define PCH_FDI_PIPE_B_DATA_M2 (0x1038 | REGS_NORTH_PIPE_AND_PORT) 1279 #define PCH_FDI_PIPE_C_DATA_M1 (0x2030 | REGS_NORTH_PIPE_AND_PORT) 1280 #define PCH_FDI_PIPE_C_DATA_M2 (0x2038 | REGS_NORTH_PIPE_AND_PORT) 1281 #define PCH_FDI_PIPE_A_DATA_N1 (0x0034 | REGS_NORTH_PIPE_AND_PORT) 1282 #define PCH_FDI_PIPE_A_DATA_N2 (0x003c | REGS_NORTH_PIPE_AND_PORT) 1283 #define PCH_FDI_PIPE_B_DATA_N1 (0x1034 | REGS_NORTH_PIPE_AND_PORT) 1284 #define PCH_FDI_PIPE_B_DATA_N2 (0x103c | REGS_NORTH_PIPE_AND_PORT) 1285 #define PCH_FDI_PIPE_C_DATA_N1 (0x2034 | REGS_NORTH_PIPE_AND_PORT) 1286 #define PCH_FDI_PIPE_C_DATA_N2 (0x203c | REGS_NORTH_PIPE_AND_PORT) 1287 #define PCH_FDI_PIPE_A_LINK_M1 (0x0040 | REGS_NORTH_PIPE_AND_PORT) 1288 #define PCH_FDI_PIPE_A_LINK_M2 (0x0048 | REGS_NORTH_PIPE_AND_PORT) 1289 #define PCH_FDI_PIPE_B_LINK_M1 (0x1040 | REGS_NORTH_PIPE_AND_PORT) 1290 #define PCH_FDI_PIPE_B_LINK_M2 (0x1048 | REGS_NORTH_PIPE_AND_PORT) 1291 #define PCH_FDI_PIPE_C_LINK_M1 (0x2040 | REGS_NORTH_PIPE_AND_PORT) 1292 #define PCH_FDI_PIPE_C_LINK_M2 (0x2048 | REGS_NORTH_PIPE_AND_PORT) 1293 #define PCH_FDI_PIPE_A_LINK_N1 (0x0044 | REGS_NORTH_PIPE_AND_PORT) 1294 #define PCH_FDI_PIPE_A_LINK_N2 (0x004c | REGS_NORTH_PIPE_AND_PORT) 1295 #define PCH_FDI_PIPE_B_LINK_N1 (0x1044 | REGS_NORTH_PIPE_AND_PORT) 1296 #define PCH_FDI_PIPE_B_LINK_N2 (0x104c | REGS_NORTH_PIPE_AND_PORT) 1297 #define PCH_FDI_PIPE_C_LINK_N1 (0x2044 | REGS_NORTH_PIPE_AND_PORT) 1298 #define PCH_FDI_PIPE_C_LINK_N2 (0x204c | REGS_NORTH_PIPE_AND_PORT) 1299 #define FDI_PIPE_MN_TU_SIZE_MASK (0x3f << 25) 1300 #define FDI_PIPE_MN_VALUE_MASK (0xffffff << 0) 1301 1302 // SNB A stepping 1303 #define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22) 1304 #define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22) 1305 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22) 1306 #define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x00 << 22) 1307 1308 // SNB B stepping 1309 #define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x00 << 22) 1310 #define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a << 22) 1311 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39 << 22) 1312 #define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38 << 22) 1313 #define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f << 22) 1314 #define FDI_TX_ENHANCE_FRAME_ENABLE (1 << 18) 1315 #define FDI_TX_PLL_ENABLED (1 << 14) 1316 1317 #define FDI_DP_PORT_WIDTH_SHIFT 19 1318 #define FDI_DP_PORT_WIDTH_MASK (7 << FDI_DP_PORT_WIDTH_SHIFT) 1319 #define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT) 1320 1321 #define FDI_PLL_BIOS_0 0x46000 1322 #define FDI_PLL_FB_CLOCK_MASK 0xff 1323 #define FDI_PLL_BIOS_1 0x46004 1324 #define FDI_PLL_BIOS_2 0x46008 1325 1326 #define FDI_AUTO_TRAINING (1 << 10) 1327 #define FDI_AUTO_TRAIN_DONE (1 << 1) 1328 1329 #define FDI_LINK_TRAIN_PATTERN_1_CPT (0 << 8) 1330 #define FDI_LINK_TRAIN_PATTERN_2_CPT (1 << 8) 1331 #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2 << 8) 1332 #define FDI_LINK_TRAIN_NORMAL_CPT (3 << 8) 1333 #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3 << 8) 1334 1335 // IvyBridge changes it up because... they hate developers? 1336 #define FDI_LINK_TRAIN_PATTERN_1_IVB (0 << 8) 1337 #define FDI_LINK_TRAIN_PATTERN_2_IVB (1 << 8) 1338 #define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2 << 8) 1339 #define FDI_LINK_TRAIN_NONE_IVB (3 << 8) 1340 1341 #define PCH_FDI_RXA_CHICKEN (0x200c | REGS_SOUTH_SHARED) 1342 #define PCH_FDI_RXB_CHICKEN (0x2010 | REGS_SOUTH_SHARED) 1343 #define FDI_RX_PHASE_SYNC_POINTER_EN (1 << 0) 1344 #define FDI_RX_PHASE_SYNC_POINTER_OVR (1 << 1) 1345 1346 // CPU Panel Fitters - These are for IronLake and up and are the CPU internal 1347 // panel fitters. 1348 #define PCH_PANEL_FITTER_BASE_REGISTER 0x68000 1349 #define PCH_PANEL_FITTER_PIPE_OFFSET 0x00800 1350 1351 #define PCH_PANEL_FITTER_WINDOW_POS 0x70 1352 #define PCH_PANEL_FITTER_WINDOW_SIZE 0x74 1353 #define PCH_PANEL_FITTER_CONTROL 0x80 1354 //not on IvyBridge: 1355 #define PCH_PANEL_FITTER_V_SCALE 0x84 1356 #define PCH_PANEL_FITTER_H_SCALE 0x90 1357 1358 #define PANEL_FITTER_ENABLED (1 << 31) 1359 //pipes are hardcoded according to offset on SkyLake and later 1360 #define PANEL_FITTER_PIPE_MASK (3 << 29) 1361 #define PANEL_FITTER_PIPE_A (0 << 29) 1362 #define PANEL_FITTER_PIPE_B (1 << 29) 1363 #define PANEL_FITTER_PIPE_C (2 << 29) 1364 #define PANEL_FITTER_SCALING_MODE_MASK (7 << 26) 1365 #define PANEL_FITTER_FILTER_MASK (3 << 24) 1366 1367 struct overlay_scale { 1368 uint32 _reserved0 : 3; 1369 uint32 horizontal_scale_fraction : 12; 1370 uint32 _reserved1 : 1; 1371 uint32 horizontal_downscale_factor : 3; 1372 uint32 _reserved2 : 1; 1373 uint32 vertical_scale_fraction : 12; 1374 }; 1375 1376 #define OVERLAY_FORMAT_RGB15 0x2 1377 #define OVERLAY_FORMAT_RGB16 0x3 1378 #define OVERLAY_FORMAT_RGB32 0x1 1379 #define OVERLAY_FORMAT_YCbCr422 0x8 1380 #define OVERLAY_FORMAT_YCbCr411 0x9 1381 #define OVERLAY_FORMAT_YCbCr420 0xc 1382 1383 #define OVERLAY_MIRROR_NORMAL 0x0 1384 #define OVERLAY_MIRROR_HORIZONTAL 0x1 1385 #define OVERLAY_MIRROR_VERTICAL 0x2 1386 1387 // The real overlay registers are written to using an update buffer 1388 1389 struct overlay_registers { 1390 uint32 buffer_rgb0; 1391 uint32 buffer_rgb1; 1392 uint32 buffer_u0; 1393 uint32 buffer_v0; 1394 uint32 buffer_u1; 1395 uint32 buffer_v1; 1396 // (0x18) OSTRIDE - overlay stride 1397 uint16 stride_rgb; 1398 uint16 stride_uv; 1399 // (0x1c) YRGB_VPH - Y/RGB vertical phase 1400 uint16 vertical_phase0_rgb; 1401 uint16 vertical_phase1_rgb; 1402 // (0x20) UV_VPH - UV vertical phase 1403 uint16 vertical_phase0_uv; 1404 uint16 vertical_phase1_uv; 1405 // (0x24) HORZ_PH - horizontal phase 1406 uint16 horizontal_phase_rgb; 1407 uint16 horizontal_phase_uv; 1408 // (0x28) INIT_PHS - initial phase shift 1409 uint32 initial_vertical_phase0_shift_rgb0 : 4; 1410 uint32 initial_vertical_phase1_shift_rgb0 : 4; 1411 uint32 initial_horizontal_phase_shift_rgb0 : 4; 1412 uint32 initial_vertical_phase0_shift_uv : 4; 1413 uint32 initial_vertical_phase1_shift_uv : 4; 1414 uint32 initial_horizontal_phase_shift_uv : 4; 1415 uint32 _reserved0 : 8; 1416 // (0x2c) DWINPOS - destination window position 1417 uint16 window_left; 1418 uint16 window_top; 1419 // (0x30) DWINSZ - destination window size 1420 uint16 window_width; 1421 uint16 window_height; 1422 // (0x34) SWIDTH - source width 1423 uint16 source_width_rgb; 1424 uint16 source_width_uv; 1425 // (0x38) SWITDHSW - source width in 8 byte steps 1426 uint16 source_bytes_per_row_rgb; 1427 uint16 source_bytes_per_row_uv; 1428 uint16 source_height_rgb; 1429 uint16 source_height_uv; 1430 overlay_scale scale_rgb; 1431 overlay_scale scale_uv; 1432 // (0x48) OCLRC0 - overlay color correction 0 1433 uint32 brightness_correction : 8; // signed, -128 to 127 1434 uint32 _reserved1 : 10; 1435 uint32 contrast_correction : 9; // fixed point: 3.6 bits 1436 uint32 _reserved2 : 5; 1437 // (0x4c) OCLRC1 - overlay color correction 1 1438 uint32 saturation_cos_correction : 10; // fixed point: 3.7 bits 1439 uint32 _reserved3 : 6; 1440 uint32 saturation_sin_correction : 11; // signed fixed point: 3.7 bits 1441 uint32 _reserved4 : 5; 1442 // (0x50) DCLRKV - destination color key value 1443 uint32 color_key_blue : 8; 1444 uint32 color_key_green : 8; 1445 uint32 color_key_red : 8; 1446 uint32 _reserved5 : 8; 1447 // (0x54) DCLRKM - destination color key mask 1448 uint32 color_key_mask_blue : 8; 1449 uint32 color_key_mask_green : 8; 1450 uint32 color_key_mask_red : 8; 1451 uint32 _reserved6 : 7; 1452 uint32 color_key_enabled : 1; 1453 // (0x58) SCHRKVH - source chroma key high value 1454 uint32 source_chroma_key_high_red : 8; 1455 uint32 source_chroma_key_high_blue : 8; 1456 uint32 source_chroma_key_high_green : 8; 1457 uint32 _reserved7 : 8; 1458 // (0x5c) SCHRKVL - source chroma key low value 1459 uint32 source_chroma_key_low_red : 8; 1460 uint32 source_chroma_key_low_blue : 8; 1461 uint32 source_chroma_key_low_green : 8; 1462 uint32 _reserved8 : 8; 1463 // (0x60) SCHRKEN - source chroma key enable 1464 uint32 _reserved9 : 24; 1465 uint32 source_chroma_key_red_enabled : 1; 1466 uint32 source_chroma_key_blue_enabled : 1; 1467 uint32 source_chroma_key_green_enabled : 1; 1468 uint32 _reserved10 : 5; 1469 // (0x64) OCONFIG - overlay configuration 1470 uint32 _reserved11 : 3; 1471 uint32 color_control_output_mode : 1; 1472 uint32 yuv_to_rgb_bypass : 1; 1473 uint32 _reserved12 : 11; 1474 uint32 gamma2_enabled : 1; 1475 uint32 _reserved13 : 1; 1476 uint32 select_pipe : 1; 1477 uint32 slot_time : 8; 1478 uint32 _reserved14 : 5; 1479 // (0x68) OCOMD - overlay command 1480 uint32 overlay_enabled : 1; 1481 uint32 active_field : 1; 1482 uint32 active_buffer : 2; 1483 uint32 test_mode : 1; 1484 uint32 buffer_field_mode : 1; 1485 uint32 _reserved15 : 1; 1486 uint32 tv_flip_field_enabled : 1; 1487 uint32 _reserved16 : 1; 1488 uint32 tv_flip_field_parity : 1; 1489 uint32 source_format : 4; 1490 uint32 ycbcr422_order : 2; 1491 uint32 _reserved18 : 1; 1492 uint32 mirroring_mode : 2; 1493 uint32 _reserved19 : 13; 1494 1495 uint32 _reserved20; 1496 1497 uint32 start_0y; 1498 uint32 start_1y; 1499 uint32 start_0u; 1500 uint32 start_0v; 1501 uint32 start_1u; 1502 uint32 start_1v; 1503 uint32 _reserved21[6]; 1504 #if 0 1505 // (0x70) AWINPOS - alpha blend window position 1506 uint32 awinpos; 1507 // (0x74) AWINSZ - alpha blend window size 1508 uint32 awinsz; 1509 1510 uint32 _reserved21[10]; 1511 #endif 1512 1513 // (0xa0) FASTHSCALE - fast horizontal downscale (strangely enough, 1514 // the next two registers switch the usual Y/RGB vs. UV order) 1515 uint16 horizontal_scale_uv; 1516 uint16 horizontal_scale_rgb; 1517 // (0xa4) UVSCALEV - vertical downscale 1518 uint16 vertical_scale_uv; 1519 uint16 vertical_scale_rgb; 1520 1521 uint32 _reserved22[86]; 1522 1523 // (0x200) polyphase filter coefficients 1524 uint16 vertical_coefficients_rgb[128]; 1525 uint16 horizontal_coefficients_rgb[128]; 1526 1527 uint32 _reserved23[64]; 1528 1529 // (0x500) 1530 uint16 vertical_coefficients_uv[128]; 1531 uint16 horizontal_coefficients_uv[128]; 1532 }; 1533 1534 // i965 overlay support is currently realized using its 3D hardware 1535 #define INTEL_i965_OVERLAY_STATE_SIZE 36864 1536 #define INTEL_i965_3D_CONTEXT_SIZE 32768 1537 1538 inline bool 1539 intel_uses_physical_overlay(intel_shared_info &info) 1540 { 1541 return !info.device_type.InGroup(INTEL_GROUP_Gxx); 1542 } 1543 1544 1545 struct hardware_status { 1546 uint32 interrupt_status_register; 1547 uint32 _reserved0[3]; 1548 void* primary_ring_head_storage; 1549 uint32 _reserved1[3]; 1550 void* secondary_ring_0_head_storage; 1551 void* secondary_ring_1_head_storage; 1552 uint32 _reserved2[2]; 1553 void* binning_head_storage; 1554 uint32 _reserved3[3]; 1555 uint32 store[1008]; 1556 }; 1557 1558 #endif /* INTEL_EXTREME_H */ 1559