1 /* 2 * Copyright 2006-2016, Haiku, Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Axel Dörfler, axeld@pinc-software.de 7 * Alexander von Gluck, kallisti5@unixzen.com 8 */ 9 #ifndef INTEL_EXTREME_H 10 #define INTEL_EXTREME_H 11 12 13 #include "lock.h" 14 15 #include <Accelerant.h> 16 #include <Drivers.h> 17 #include <PCI.h> 18 19 #include <edid.h> 20 21 22 #define VENDOR_ID_INTEL 0x8086 23 24 #define INTEL_FAMILY_MASK 0x00ff0000 25 #define INTEL_GROUP_MASK 0x00fffff0 26 #define INTEL_MODEL_MASK 0x00ffffff 27 #define INTEL_TYPE_MASK 0x0000000f 28 29 // families 30 #define INTEL_FAMILY_8xx 0x00020000 // Second Gen 31 #define INTEL_FAMILY_9xx 0x00040000 // Third Gen + 32 #define INTEL_FAMILY_SER5 0x00080000 // Intel5 Series 33 #define INTEL_FAMILY_SOC0 0x00200000 // Atom SOC 34 #define INTEL_FAMILY_LAKE 0x00400000 // Intel Lakes 35 36 // groups 37 #define INTEL_GROUP_83x (INTEL_FAMILY_8xx | 0x0010) 38 #define INTEL_GROUP_85x (INTEL_FAMILY_8xx | 0x0020) 39 #define INTEL_GROUP_91x (INTEL_FAMILY_9xx | 0x0010) 40 #define INTEL_GROUP_94x (INTEL_FAMILY_9xx | 0x0020) 41 #define INTEL_GROUP_96x (INTEL_FAMILY_9xx | 0x0040) 42 #define INTEL_GROUP_Gxx (INTEL_FAMILY_9xx | 0x0080) 43 #define INTEL_GROUP_G4x (INTEL_FAMILY_9xx | 0x0100) 44 #define INTEL_GROUP_PIN (INTEL_FAMILY_9xx | 0x0200) // PineView 45 #define INTEL_GROUP_ILK (INTEL_FAMILY_SER5 | 0x0010) // IronLake 46 #define INTEL_GROUP_SNB (INTEL_FAMILY_SER5 | 0x0020) // SandyBridge 47 #define INTEL_GROUP_IVB (INTEL_FAMILY_SER5 | 0x0040) // IvyBridge 48 #define INTEL_GROUP_HAS (INTEL_FAMILY_SER5 | 0x0080) // Haswell 49 #define INTEL_GROUP_VLV (INTEL_FAMILY_SOC0 | 0x0010) // ValleyView 50 #define INTEL_GROUP_CHV (INTEL_FAMILY_SOC0 | 0x0020) // CherryView 51 #define INTEL_GROUP_BDW (INTEL_FAMILY_SOC0 | 0x0040) // Broadwell 52 #define INTEL_GROUP_SKY (INTEL_FAMILY_LAKE | 0x0010) // SkyLake 53 #define INTEL_GROUP_KBY (INTEL_FAMILY_LAKE | 0x0020) // KabyLake 54 #define INTEL_GROUP_CFL (INTEL_FAMILY_LAKE | 0x0040) // CoffeeLake 55 #define INTEL_GROUP_CML (INTEL_FAMILY_LAKE | 0x0080) // CometLake 56 #define INTEL_GROUP_JSL (INTEL_FAMILY_LAKE | 0x0100) // JasperLake 57 #define INTEL_GROUP_TGL (INTEL_FAMILY_LAKE | 0x0200) // TigerLake 58 // models 59 #define INTEL_TYPE_SERVER 0x0004 60 #define INTEL_TYPE_MOBILE 0x0008 61 #define INTEL_MODEL_915 (INTEL_GROUP_91x) 62 #define INTEL_MODEL_915M (INTEL_GROUP_91x | INTEL_TYPE_MOBILE) 63 #define INTEL_MODEL_945 (INTEL_GROUP_94x) 64 #define INTEL_MODEL_945M (INTEL_GROUP_94x | INTEL_TYPE_MOBILE) 65 #define INTEL_MODEL_965 (INTEL_GROUP_96x) 66 #define INTEL_MODEL_965M (INTEL_GROUP_96x | INTEL_TYPE_MOBILE) 67 #define INTEL_MODEL_G33 (INTEL_GROUP_Gxx) 68 #define INTEL_MODEL_G45 (INTEL_GROUP_G4x) 69 #define INTEL_MODEL_GM45 (INTEL_GROUP_G4x | INTEL_TYPE_MOBILE) 70 #define INTEL_MODEL_PINE (INTEL_GROUP_PIN) 71 #define INTEL_MODEL_PINEM (INTEL_GROUP_PIN | INTEL_TYPE_MOBILE) 72 #define INTEL_MODEL_ILKG (INTEL_GROUP_ILK) 73 #define INTEL_MODEL_ILKGM (INTEL_GROUP_ILK | INTEL_TYPE_MOBILE) 74 #define INTEL_MODEL_SNBG (INTEL_GROUP_SNB) 75 #define INTEL_MODEL_SNBGM (INTEL_GROUP_SNB | INTEL_TYPE_MOBILE) 76 #define INTEL_MODEL_SNBGS (INTEL_GROUP_SNB | INTEL_TYPE_SERVER) 77 #define INTEL_MODEL_IVBG (INTEL_GROUP_IVB) 78 #define INTEL_MODEL_IVBGM (INTEL_GROUP_IVB | INTEL_TYPE_MOBILE) 79 #define INTEL_MODEL_IVBGS (INTEL_GROUP_IVB | INTEL_TYPE_SERVER) 80 #define INTEL_MODEL_HAS (INTEL_GROUP_HAS) 81 #define INTEL_MODEL_HASM (INTEL_GROUP_HAS | INTEL_TYPE_MOBILE) 82 #define INTEL_MODEL_VLV (INTEL_GROUP_VLV) 83 #define INTEL_MODEL_VLVM (INTEL_GROUP_VLV | INTEL_TYPE_MOBILE) 84 #define INTEL_MODEL_BDW (INTEL_GROUP_BDW) 85 #define INTEL_MODEL_BDWM (INTEL_GROUP_BDW | INTEL_TYPE_MOBILE) 86 #define INTEL_MODEL_BDWS (INTEL_GROUP_BDW | INTEL_TYPE_SERVER) 87 #define INTEL_MODEL_SKY (INTEL_GROUP_SKY) 88 #define INTEL_MODEL_SKYM (INTEL_GROUP_SKY | INTEL_TYPE_MOBILE) 89 #define INTEL_MODEL_SKYS (INTEL_GROUP_SKY | INTEL_TYPE_SERVER) 90 #define INTEL_MODEL_KBY (INTEL_GROUP_KBY) 91 #define INTEL_MODEL_KBYM (INTEL_GROUP_KBY | INTEL_TYPE_MOBILE) 92 #define INTEL_MODEL_CFL (INTEL_GROUP_CFL) 93 #define INTEL_MODEL_CFLM (INTEL_GROUP_CFL | INTEL_TYPE_MOBILE) 94 #define INTEL_MODEL_CML (INTEL_GROUP_CML) 95 #define INTEL_MODEL_CMLM (INTEL_GROUP_CML | INTEL_TYPE_MOBILE) 96 #define INTEL_MODEL_JSL (INTEL_GROUP_JSL) 97 #define INTEL_MODEL_JSLM (INTEL_GROUP_JSL | INTEL_TYPE_MOBILE) 98 #define INTEL_MODEL_TGLM (INTEL_GROUP_TGL | INTEL_TYPE_MOBILE) 99 100 #define INTEL_PCH_DEVICE_ID_MASK 0xff80 101 #define INTEL_PCH_IBX_DEVICE_ID 0x3b00 102 #define INTEL_PCH_CPT_DEVICE_ID 0x1c00 103 #define INTEL_PCH_PPT_DEVICE_ID 0x1e00 104 #define INTEL_PCH_LPT_DEVICE_ID 0x8c00 105 #define INTEL_PCH_LPT_LP_DEVICE_ID 0x9c00 106 #define INTEL_PCH_WPT_DEVICE_ID 0x8c80 107 #define INTEL_PCH_WPT_LP_DEVICE_ID 0x9c80 108 #define INTEL_PCH_SPT_DEVICE_ID 0xa100 109 #define INTEL_PCH_SPT_LP_DEVICE_ID 0x9d00 110 #define INTEL_PCH_KBP_DEVICE_ID 0xa280 111 #define INTEL_PCH_CNP_DEVICE_ID 0xa300 112 #define INTEL_PCH_CNP_LP_DEVICE_ID 0x9d80 113 #define INTEL_PCH_CMP_DEVICE_ID 0x0280 114 #define INTEL_PCH_CMP2_DEVICE_ID 0x0680 115 #define INTEL_PCH_CMP_V_DEVICE_ID 0xa380 116 #define INTEL_PCH_ICP_DEVICE_ID 0x3480 117 #define INTEL_PCH_ICP2_DEVICE_ID 0x3880 118 #define INTEL_PCH_MCC_DEVICE_ID 0x4b00 119 #define INTEL_PCH_TGP_DEVICE_ID 0xa080 120 #define INTEL_PCH_TGP2_DEVICE_ID 0x4380 121 #define INTEL_PCH_JSP_DEVICE_ID 0x4d80 122 #define INTEL_PCH_ADP_DEVICE_ID 0x7a80 123 #define INTEL_PCH_ADP2_DEVICE_ID 0x5180 124 #define INTEL_PCH_ADP3_DEVICE_ID 0x7a00 125 #define INTEL_PCH_ADP4_DEVICE_ID 0x5480 126 #define INTEL_PCH_P2X_DEVICE_ID 0x7100 127 #define INTEL_PCH_P3X_DEVICE_ID 0x7000 128 129 // ValleyView MMIO offset 130 #define VLV_DISPLAY_BASE 0x180000 131 132 #define DEVICE_NAME "intel_extreme" 133 #define INTEL_ACCELERANT_NAME "intel_extreme.accelerant" 134 135 // We encode the register block into the value and extract/translate it when 136 // actually accessing. 137 #define REGISTER_BLOCK_COUNT 6 138 #define REGISTER_BLOCK_SHIFT 24 139 #define REGISTER_BLOCK_MASK 0xff000000 140 #define REGISTER_REGISTER_MASK 0x00ffffff 141 #define REGISTER_BLOCK(x) ((x & REGISTER_BLOCK_MASK) >> REGISTER_BLOCK_SHIFT) 142 #define REGISTER_REGISTER(x) (x & REGISTER_REGISTER_MASK) 143 144 #define REGS_FLAT (0 << REGISTER_BLOCK_SHIFT) 145 #define REGS_NORTH_SHARED (1 << REGISTER_BLOCK_SHIFT) 146 #define REGS_NORTH_PIPE_AND_PORT (2 << REGISTER_BLOCK_SHIFT) 147 #define REGS_NORTH_PLANE_CONTROL (3 << REGISTER_BLOCK_SHIFT) 148 #define REGS_SOUTH_SHARED (4 << REGISTER_BLOCK_SHIFT) 149 #define REGS_SOUTH_TRANSCODER_PORT (5 << REGISTER_BLOCK_SHIFT) 150 151 // register blocks for (G)MCH/ICH based platforms 152 #define MCH_SHARED_REGISTER_BASE 0x00000 153 #define MCH_PIPE_AND_PORT_REGISTER_BASE 0x60000 154 #define MCH_PLANE_CONTROL_REGISTER_BASE 0x70000 155 156 #define ICH_SHARED_REGISTER_BASE 0x00000 157 #define ICH_PORT_REGISTER_BASE 0x60000 158 159 // PCH - Platform Control Hub - Some hardware moves from a MCH/ICH based 160 // setup to a PCH based one, that means anything that used to communicate via 161 // (G)MCH registers needs to use different ones on PCH based platforms 162 // (Ironlake, SandyBridge, IvyBridge, Some Haswell). 163 #define PCH_NORTH_SHARED_REGISTER_BASE 0x40000 164 #define PCH_NORTH_PIPE_AND_PORT_REGISTER_BASE 0x60000 165 #define PCH_NORTH_PLANE_CONTROL_REGISTER_BASE 0x70000 166 #define PCH_SOUTH_SHARED_REGISTER_BASE 0xc0000 167 #define PCH_SOUTH_TRANSCODER_AND_PORT_REGISTER_BASE 0xe0000 168 169 170 struct DeviceType { 171 uint32 type; 172 173 DeviceType(int t) 174 { 175 type = t; 176 } 177 178 DeviceType& operator=(int t) 179 { 180 type = t; 181 return *this; 182 } 183 184 bool InFamily(uint32 family) const 185 { 186 return (type & INTEL_FAMILY_MASK) == family; 187 } 188 189 bool InGroup(uint32 group) const 190 { 191 return (type & INTEL_GROUP_MASK) == group; 192 } 193 194 bool IsModel(uint32 model) const 195 { 196 return (type & INTEL_MODEL_MASK) == model; 197 } 198 199 bool IsMobile() const 200 { 201 return (type & INTEL_TYPE_MASK) == INTEL_TYPE_MOBILE; 202 } 203 204 bool SupportsHDMI() const 205 { 206 return InGroup(INTEL_GROUP_G4x) || InFamily(INTEL_FAMILY_SER5) 207 || InFamily(INTEL_FAMILY_SOC0); 208 } 209 210 bool HasDDI() const 211 { 212 // Intel Digital Display Interface 213 return InGroup(INTEL_GROUP_HAS) || (Generation() >= 8); 214 } 215 216 int Generation() const 217 { 218 if (InFamily(INTEL_FAMILY_8xx)) 219 return 2; 220 if (InGroup(INTEL_GROUP_91x) || InGroup(INTEL_GROUP_94x) 221 || IsModel(INTEL_MODEL_G33) || InGroup(INTEL_GROUP_PIN)) 222 return 3; 223 if (InFamily(INTEL_FAMILY_9xx)) 224 return 4; 225 if (InGroup(INTEL_GROUP_ILK)) 226 return 5; 227 if (InGroup(INTEL_GROUP_SNB)) 228 return 6; 229 if (InFamily(INTEL_FAMILY_SER5) || InGroup(INTEL_GROUP_VLV)) 230 return 7; 231 if (InGroup(INTEL_GROUP_CHV) || InGroup(INTEL_GROUP_BDW)) 232 return 8; 233 if (InGroup(INTEL_GROUP_JSL)) 234 return 11; 235 if (InGroup(INTEL_GROUP_TGL)) 236 return 12; 237 if (InFamily(INTEL_FAMILY_LAKE)) 238 return 9; 239 240 // Generation 0 means something is wrong :-) 241 return 0; 242 } 243 }; 244 245 enum port_index { 246 INTEL_PORT_ANY, // wildcard for lookup functions 247 INTEL_PORT_A, 248 INTEL_PORT_B, 249 INTEL_PORT_C, 250 INTEL_PORT_D, 251 INTEL_PORT_E, 252 INTEL_PORT_F 253 }; 254 255 enum pch_info { 256 INTEL_PCH_NONE = 0, // No PCH present 257 INTEL_PCH_IBX, // Ibexpeak 258 INTEL_PCH_CPT, // Cougarpoint 259 INTEL_PCH_LPT, // Lynxpoint 260 INTEL_PCH_SPT, // SunrisePoint 261 INTEL_PCH_CNP, // CannonLake 262 INTEL_PCH_ICP, // IceLake 263 INTEL_PCH_JSP, // JasperLake 264 INTEL_PCH_MCC, // Mule Creek Canyon 265 INTEL_PCH_TGP, // TigerLake 266 INTEL_PCH_ADP, // AlderLake 267 INTEL_PCH_NOP 268 }; 269 270 // info about PLL on graphics card 271 struct pll_info { 272 uint32 reference_frequency; 273 uint32 max_frequency; 274 uint32 min_frequency; 275 uint32 divisor_register; 276 }; 277 278 struct ring_buffer { 279 struct lock lock; 280 uint32 register_base; 281 uint32 offset; 282 uint32 size; 283 uint32 position; 284 uint32 space_left; 285 uint8* base; 286 }; 287 288 289 struct child_device_config { 290 uint16 handle; 291 uint16 device_type; 292 #define DEVICE_TYPE_ANALOG_OUTPUT (1 << 0) 293 #define DEVICE_TYPE_DIGITAL_OUTPUT (1 << 1) 294 #define DEVICE_TYPE_DISPLAYPORT_OUTPUT (1 << 2) 295 #define DEVICE_TYPE_VIDEO_SIGNALING (1 << 3) 296 #define DEVICE_TYPE_TMDS_DVI_SIGNALING (1 << 4) 297 #define DEVICE_TYPE_LVDS_SIGNALING (1 << 5) 298 #define DEVICE_TYPE_HIGH_SPEED_LINK (1 << 6) 299 #define DEVICE_TYPE_DUAL_CHANNEL (1 << 8) 300 #define DEVICE_TYPE_COMPOSITE_OUTPUT (1 << 9) 301 #define DEVICE_TYPE_MIPI_OUTPUT (1 << 10) 302 #define DEVICE_TYPE_NOT_HDMI_OUTPUT (1 << 11) 303 #define DEVICE_TYPE_INTERNAL_CONNECTOR (1 << 12) 304 #define DEVICE_TYPE_HOTPLUG_SIGNALING (1 << 13) 305 #define DEVICE_TYPE_POWER_MANAGEMENT (1 << 14) 306 #define DEVICE_TYPE_CLASS_EXTENSION (1 << 15) 307 308 uint8 device_id[10]; 309 uint16 addin_offset; 310 uint8 dvo_port; 311 uint8 i2c_pin; 312 uint8 slave_addr; 313 uint8 ddc_pin; 314 uint16 edid_ptr; 315 uint8 dvo_cfg; 316 317 struct { 318 bool efp_routed:1; 319 bool lane_reversal:1; 320 bool lspcon:1; 321 bool iboost:1; 322 bool hpd_invert:1; 323 bool use_vbt_vswing:1; 324 uint8 reserved:2; 325 bool hdmi_support:1; 326 bool dp_support:1; 327 bool tmds_support:1; 328 uint8 reserved2:5; 329 uint8 aux_channel; 330 uint8 dongle_detect; 331 } __attribute__((packed)); 332 333 uint8 caps; 334 uint8 dvo_wiring; 335 uint8 dvo2_wiring; 336 uint16 extended_type; 337 uint8 dvo_function; 338 339 bool dp_usb_type_c:1; 340 bool tbt:1; 341 uint8 reserved3:2; 342 uint8 dp_port_trace_length:4; 343 uint8 dp_gpio_index; 344 uint8 dp_gpio_pin_num; 345 uint8 dp_iboost_level:4; 346 uint8 hdmi_iboost_level:4; 347 uint8 dp_max_link_rate:3; 348 uint8 dp_max_link_rate_reserved:5; 349 } __attribute__((packed)); 350 351 352 enum dvo_port { 353 DVO_PORT_HDMIA, 354 DVO_PORT_HDMIB, 355 DVO_PORT_HDMIC, 356 DVO_PORT_HDMID, 357 DVO_PORT_LVDS, 358 DVO_PORT_TV, 359 DVO_PORT_CRT, 360 DVO_PORT_DPB, 361 DVO_PORT_DPC, 362 DVO_PORT_DPD, 363 DVO_PORT_DPA, 364 DVO_PORT_DPE, 365 DVO_PORT_HDMIE, 366 DVO_PORT_DPF, 367 DVO_PORT_HDMIF, 368 DVO_PORT_DPG, 369 DVO_PORT_HDMIG, 370 DVO_PORT_DPH, 371 DVO_PORT_HDMIH, 372 DVO_PORT_DPI, 373 DVO_PORT_HDMII, 374 }; 375 376 377 enum dp_aux_channel { 378 DP_AUX_A = 0x40, 379 DP_AUX_B = 0x10, 380 DP_AUX_C = 0x20, 381 DP_AUX_D = 0x30, 382 DP_AUX_E = 0x50, 383 DP_AUX_F = 0x60, 384 DP_AUX_G = 0x70, 385 DP_AUX_H = 0x80, 386 DP_AUX_I = 0x90 387 }; 388 389 390 enum aux_channel { 391 AUX_CH_A, 392 AUX_CH_B, 393 AUX_CH_C, 394 AUX_CH_D, 395 AUX_CH_E, 396 AUX_CH_F, 397 AUX_CH_G, 398 AUX_CH_H, 399 AUX_CH_I, 400 }; 401 402 403 enum hpd_pin { 404 HPD_PORT_A, 405 HPD_PORT_B, 406 HPD_PORT_C, 407 HPD_PORT_D, 408 HPD_PORT_E, 409 HPD_PORT_TC1, 410 HPD_PORT_TC2, 411 HPD_PORT_TC3, 412 HPD_PORT_TC4, 413 HPD_PORT_TC5, 414 HPD_PORT_TC6, 415 }; 416 417 418 struct intel_shared_info { 419 area_id mode_list_area; // area containing display mode list 420 uint32 mode_count; 421 422 display_mode current_mode; // pretty much a hack until per-display modes 423 display_timing panel_timing; // Hardware timings of the LVDS panel, extracted from BIOS 424 uint32 bytes_per_row; 425 uint32 bits_per_pixel; 426 uint32 dpms_mode; 427 uint16 min_brightness; 428 429 area_id registers_area; // area of memory mapped registers 430 uint32 register_blocks[REGISTER_BLOCK_COUNT]; 431 432 uint8* status_page; 433 phys_addr_t physical_status_page; 434 uint8* graphics_memory; 435 phys_addr_t physical_graphics_memory; 436 uint32 graphics_memory_size; 437 438 addr_t frame_buffer; 439 uint32 frame_buffer_offset; 440 441 uint32 fdi_link_frequency; // In Mhz 442 uint32 hraw_clock; 443 uint32 hw_cdclk; 444 445 bool got_vbt; 446 bool single_head_locked; 447 448 struct lock accelerant_lock; 449 struct lock engine_lock; 450 451 ring_buffer primary_ring_buffer; 452 453 int32 overlay_channel_used; 454 bool overlay_active; 455 uintptr_t overlay_token; 456 phys_addr_t physical_overlay_registers; 457 uint32 overlay_offset; 458 459 bool hardware_cursor_enabled; 460 sem_id vblank_sem; 461 462 uint8* cursor_memory; 463 phys_addr_t physical_cursor_memory; 464 uint32 cursor_buffer_offset; 465 uint32 cursor_format; 466 bool cursor_visible; 467 uint16 cursor_hot_x; 468 uint16 cursor_hot_y; 469 470 DeviceType device_type; 471 char device_identifier[32]; 472 struct pll_info pll_info; 473 474 enum pch_info pch_info; 475 476 edid1_info vesa_edid_info; 477 bool has_vesa_edid_info; 478 479 bool internal_crt_support; 480 uint32 device_config_count; 481 child_device_config device_configs[10]; 482 }; 483 484 enum pipe_index { 485 INTEL_PIPE_ANY, 486 INTEL_PIPE_A, 487 INTEL_PIPE_B, 488 INTEL_PIPE_C, 489 INTEL_PIPE_D 490 }; 491 492 class pipes { 493 public: 494 pipes() : bitmask(0) {} 495 496 bool HasPipe(pipe_index pipe) 497 { 498 if (pipe == INTEL_PIPE_ANY) 499 return bitmask != 0; 500 501 return (bitmask & (1 << pipe)) != 0; 502 } 503 504 void SetPipe(pipe_index pipe) 505 { 506 if (pipe == INTEL_PIPE_ANY) { 507 bitmask = ~1; 508 // first bit corresponds to INTEL_PIPE_ANY but it's never used, 509 // so it should be 0 510 } 511 bitmask |= (1 << pipe); 512 } 513 514 void ClearPipe(pipe_index pipe) 515 { 516 if (pipe == INTEL_PIPE_ANY) 517 bitmask = 0; 518 519 bitmask &= ~(1 << pipe); 520 } 521 522 private: 523 uint8 bitmask; 524 }; 525 526 //----------------- ioctl() interface ---------------- 527 528 // magic code for ioctls 529 #define INTEL_PRIVATE_DATA_MAGIC 'itic' 530 531 // list ioctls 532 enum { 533 INTEL_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1, 534 535 INTEL_GET_DEVICE_NAME, 536 INTEL_ALLOCATE_GRAPHICS_MEMORY, 537 INTEL_FREE_GRAPHICS_MEMORY, 538 INTEL_GET_BRIGHTNESS_LEGACY, 539 INTEL_SET_BRIGHTNESS_LEGACY 540 }; 541 542 // retrieve the area_id of the kernel/accelerant shared info 543 struct intel_get_private_data { 544 uint32 magic; // magic number 545 area_id shared_info_area; 546 }; 547 548 // allocate graphics memory 549 struct intel_allocate_graphics_memory { 550 uint32 magic; 551 uint32 size; 552 uint32 alignment; 553 uint32 flags; 554 addr_t buffer_base; 555 }; 556 557 // free graphics memory 558 struct intel_free_graphics_memory { 559 uint32 magic; 560 addr_t buffer_base; 561 }; 562 563 // brightness legacy 564 struct intel_brightness_legacy { 565 uint32 magic; 566 uint8 lpc; 567 }; 568 569 //---------------------------------------------------------- 570 // Register definitions, taken from X driver 571 572 // PCI bridge memory management 573 #define INTEL_GRAPHICS_MEMORY_CONTROL 0x52 // i830+ 574 575 // GGC - (G)MCH Graphics Control Register 576 #define MEMORY_CONTROL_ENABLED 0x0004 577 #define MEMORY_MASK 0x0001 578 #define STOLEN_MEMORY_MASK 0x00f0 579 #define i965_GTT_MASK 0x000e 580 #define G33_GTT_MASK 0x0300 581 #define G4X_GTT_MASK 0x0f00 // GGMS (GSM Memory Size) mask 582 583 // models i830 and up 584 #define i830_LOCAL_MEMORY_ONLY 0x10 585 #define i830_STOLEN_512K 0x20 586 #define i830_STOLEN_1M 0x30 587 #define i830_STOLEN_8M 0x40 588 #define i830_FRAME_BUFFER_64M 0x01 589 #define i830_FRAME_BUFFER_128M 0x00 590 591 // models i855 and up 592 #define i855_STOLEN_MEMORY_1M 0x10 593 #define i855_STOLEN_MEMORY_4M 0x20 594 #define i855_STOLEN_MEMORY_8M 0x30 595 #define i855_STOLEN_MEMORY_16M 0x40 596 #define i855_STOLEN_MEMORY_32M 0x50 597 #define i855_STOLEN_MEMORY_48M 0x60 598 #define i855_STOLEN_MEMORY_64M 0x70 599 #define i855_STOLEN_MEMORY_128M 0x80 600 #define i855_STOLEN_MEMORY_256M 0x90 601 602 #define G4X_STOLEN_MEMORY_96MB 0xa0 // GMS - Graphics Mode Select 603 #define G4X_STOLEN_MEMORY_160MB 0xb0 604 #define G4X_STOLEN_MEMORY_224MB 0xc0 605 #define G4X_STOLEN_MEMORY_352MB 0xd0 606 607 // SandyBridge (SNB) 608 609 #define SNB_GRAPHICS_MEMORY_CONTROL 0x50 610 611 #define SNB_STOLEN_MEMORY_MASK 0xf8 612 #define SNB_STOLEN_MEMORY_32MB (1 << 3) 613 #define SNB_STOLEN_MEMORY_64MB (2 << 3) 614 #define SNB_STOLEN_MEMORY_96MB (3 << 3) 615 #define SNB_STOLEN_MEMORY_128MB (4 << 3) 616 #define SNB_STOLEN_MEMORY_160MB (5 << 3) 617 #define SNB_STOLEN_MEMORY_192MB (6 << 3) 618 #define SNB_STOLEN_MEMORY_224MB (7 << 3) 619 #define SNB_STOLEN_MEMORY_256MB (8 << 3) 620 #define SNB_STOLEN_MEMORY_288MB (9 << 3) 621 #define SNB_STOLEN_MEMORY_320MB (10 << 3) 622 #define SNB_STOLEN_MEMORY_352MB (11 << 3) 623 #define SNB_STOLEN_MEMORY_384MB (12 << 3) 624 #define SNB_STOLEN_MEMORY_416MB (13 << 3) 625 #define SNB_STOLEN_MEMORY_448MB (14 << 3) 626 #define SNB_STOLEN_MEMORY_480MB (15 << 3) 627 #define SNB_STOLEN_MEMORY_512MB (16 << 3) 628 629 #define SNB_GTT_SIZE_MASK (3 << 8) 630 #define SNB_GTT_SIZE_NONE (0 << 8) 631 #define SNB_GTT_SIZE_1MB (1 << 8) 632 #define SNB_GTT_SIZE_2MB (2 << 8) 633 634 // BDW+ (GGC_0_0_0_PCI) 635 636 #define BDW_GRAPHICS_MEMORY_CONTROL 0x50 637 638 #define BDW_STOLEN_MEMORY_MASK 0xff00 639 #define BDW_STOLEN_MEMORY_32MB (1 << 8) 640 #define BDW_STOLEN_MEMORY_64MB (2 << 8) 641 #define BDW_STOLEN_MEMORY_96MB (3 << 8) 642 #define BDW_STOLEN_MEMORY_128MB (4 << 8) 643 #define BDW_STOLEN_MEMORY_160MB (5 << 8) 644 #define BDW_STOLEN_MEMORY_192MB (6 << 8) 645 #define BDW_STOLEN_MEMORY_224MB (7 << 8) 646 #define BDW_STOLEN_MEMORY_256MB (8 << 8) 647 #define BDW_STOLEN_MEMORY_288MB (9 << 8) 648 #define BDW_STOLEN_MEMORY_320MB (10 << 8) 649 #define BDW_STOLEN_MEMORY_352MB (11 << 8) 650 #define BDW_STOLEN_MEMORY_384MB (12 << 8) 651 #define BDW_STOLEN_MEMORY_416MB (13 << 8) 652 #define BDW_STOLEN_MEMORY_448MB (14 << 8) 653 #define BDW_STOLEN_MEMORY_480MB (15 << 8) 654 #define BDW_STOLEN_MEMORY_512MB (16 << 8) 655 #define BDW_STOLEN_MEMORY_1024MB (32 << 8) 656 #define BDW_STOLEN_MEMORY_1536MB (48 << 8) 657 #define BDW_STOLEN_MEMORY_2016MB (63 << 8) 658 #define SKL_STOLEN_MEMORY_2048MB (64 << 8) 659 #define SKL_STOLEN_MEMORY_4MB (240 << 8) 660 #define SKL_STOLEN_MEMORY_8MB (241 << 8) 661 #define SKL_STOLEN_MEMORY_12MB (242 << 8) 662 #define SKL_STOLEN_MEMORY_16MB (243 << 8) 663 #define SKL_STOLEN_MEMORY_20MB (244 << 8) 664 #define SKL_STOLEN_MEMORY_24MB (245 << 8) 665 #define SKL_STOLEN_MEMORY_28MB (246 << 8) 666 #define SKL_STOLEN_MEMORY_32MB (247 << 8) 667 #define SKL_STOLEN_MEMORY_36MB (248 << 8) 668 #define SKL_STOLEN_MEMORY_40MB (249 << 8) 669 #define SKL_STOLEN_MEMORY_44MB (250 << 8) 670 #define SKL_STOLEN_MEMORY_48MB (251 << 8) 671 #define SKL_STOLEN_MEMORY_52MB (252 << 8) 672 #define SKL_STOLEN_MEMORY_56MB (253 << 8) 673 #define SKL_STOLEN_MEMORY_60MB (254 << 8) 674 675 676 #define BDW_GTT_SIZE_MASK (3 << 6) 677 #define BDW_GTT_SIZE_NONE (0 << 6) 678 #define BDW_GTT_SIZE_2MB (1 << 6) 679 #define BDW_GTT_SIZE_4MB (2 << 6) 680 #define BDW_GTT_SIZE_8MB (3 << 6) 681 682 // Gen2, i915GM, i945GM 683 #define LEGACY_BACKLIGHT_BRIGHTNESS 0xf4 684 685 // graphics page translation table 686 #define INTEL_PAGE_TABLE_CONTROL 0x02020 687 #define PAGE_TABLE_ENABLED 0x00000001 688 #define INTEL_PAGE_TABLE_ERROR 0x02024 689 #define INTEL_HARDWARE_STATUS_PAGE 0x02080 690 #define i915_GTT_BASE 0x1c 691 #define i830_GTT_BASE 0x10000 // (- 0x2ffff) 692 #define i830_GTT_SIZE 0x20000 693 #define i965_GTT_BASE 0x80000 // (- 0xfffff) 694 #define i965_GTT_SIZE 0x80000 695 #define i965_GTT_128K (2 << 1) 696 #define i965_GTT_256K (1 << 1) 697 #define i965_GTT_512K (0 << 1) 698 #define G33_GTT_1M (1 << 8) 699 #define G33_GTT_2M (2 << 8) 700 #define G4X_GTT_NONE 0x000 // GGMS - GSM Memory Size 701 #define G4X_GTT_1M_NO_IVT 0x100 // no Intel Virtualization Tech. 702 #define G4X_GTT_2M_NO_IVT 0x300 703 #define G4X_GTT_2M_IVT 0x900 // with Intel Virt. Tech. 704 #define G4X_GTT_3M_IVT 0xa00 705 #define G4X_GTT_4M_IVT 0xb00 706 707 708 #define GTT_ENTRY_VALID 0x01 709 #define GTT_ENTRY_LOCAL_MEMORY 0x02 710 #define GTT_PAGE_SHIFT 12 711 712 713 // ring buffer 714 #define INTEL_PRIMARY_RING_BUFFER 0x02030 715 #define INTEL_SECONDARY_RING_BUFFER_0 0x02100 716 #define INTEL_SECONDARY_RING_BUFFER_1 0x02110 717 // offsets for the ring buffer base registers above 718 #define RING_BUFFER_TAIL 0x0 719 #define RING_BUFFER_HEAD 0x4 720 #define RING_BUFFER_START 0x8 721 #define RING_BUFFER_CONTROL 0xc 722 #define INTEL_RING_BUFFER_SIZE_MASK 0x001ff000 723 #define INTEL_RING_BUFFER_HEAD_MASK 0x001ffffc 724 #define INTEL_RING_BUFFER_ENABLED 1 725 726 // interrupts 727 #define INTEL_INTERRUPT_ENABLED 0x020a0 728 #define INTEL_INTERRUPT_IDENTITY 0x020a4 729 #define INTEL_INTERRUPT_MASK 0x020a8 730 #define INTEL_INTERRUPT_STATUS 0x020ac 731 #define INTERRUPT_VBLANK_PIPEA (1 << 7) 732 #define INTERRUPT_VBLANK_PIPEB (1 << 5) 733 734 // PCH interrupts 735 #define PCH_INTERRUPT_STATUS 0x44000 736 #define PCH_INTERRUPT_MASK 0x44004 737 #define PCH_INTERRUPT_IDENTITY 0x44008 738 #define PCH_INTERRUPT_ENABLED 0x4400c 739 740 #define PCH_INTERRUPT_VBLANK_PIPEA (1 << 0) 741 #define PCH_INTERRUPT_VBLANK_PIPEB (1 << 5) 742 #define PCH_INTERRUPT_VBLANK_PIPEC (1 << 10) 743 744 // SandyBridge had only two pipes, and things were shuffled aroud again with 745 // the introduction of pipe C. 746 #define PCH_INTERRUPT_VBLANK_PIPEA_SNB (1 << 7) 747 #define PCH_INTERRUPT_VBLANK_PIPEB_SNB (1 << 15) 748 #define PCH_INTERRUPT_GLOBAL_SNB (1 << 31) 749 750 #define PCH_MASTER_INT_CTL_BDW 0x44200 751 752 #define PCH_MASTER_INT_CTL_PIPE_PENDING_BDW(pipe) (1 << (15 + pipe)) 753 #define GEN8_DE_PCH_IRQ (1 << 23) 754 #define GEN8_DE_PORT_IRQ (1 << 20) 755 #define PCH_MASTER_INT_CTL_GLOBAL_BDW (1 << 31) 756 757 #define PCH_INTERRUPT_PIPE_STATUS_BDW(pipe) (0x44400 + (pipe - 1) * 0x10) // GEN8_DE_PIPE_ISR 758 #define PCH_INTERRUPT_PIPE_MASK_BDW(pipe) (0x44404 + (pipe - 1) * 0x10) // GEN8_DE_PIPE_IMR 759 #define PCH_INTERRUPT_PIPE_IDENTITY_BDW(pipe) (0x44408 + (pipe - 1) * 0x10) // GEN8_DE_PIPE_IIR 760 #define PCH_INTERRUPT_PIPE_ENABLED_BDW(pipe) (0x4440c + (pipe - 1) * 0x10) // GEN8_DE_PIPE_IER 761 762 #define GEN8_DE_PORT_ISR 0x44440 763 #define GEN8_DE_PORT_IMR 0x44444 764 #define GEN8_DE_PORT_IIR 0x44448 765 #define GEN8_DE_PORT_IER 0x4444c 766 #define GEN8_AUX_CHANNEL_A (1 << 0) 767 #define GEN9_AUX_CHANNEL_B (1 << 25) 768 #define GEN9_AUX_CHANNEL_C (1 << 26) 769 #define GEN9_AUX_CHANNEL_D (1 << 27) 770 #define CNL_AUX_CHANNEL_F (1 << 28) 771 #define ICL_AUX_CHANNEL_E (1 << 29) 772 773 #define GEN8_DE_MISC_ISR 0x44460 774 #define GEN8_DE_MISC_IMR 0x44464 775 #define GEN8_DE_MISC_IIR 0x44468 776 #define GEN8_DE_MISC_IER 0x4446c 777 #define GEN8_DE_EDP_PSR (1 << 19) 778 779 #define GEN11_DE_HPD_ISR 0x44470 780 #define GEN11_DE_HPD_IMR 0x44474 781 #define GEN11_DE_HPD_IIR 0x44478 782 #define GEN11_DE_HPD_IER 0x4447c 783 #define GEN11_DE_TC_HOTPLUG_MASK (0x3f << 16) 784 #define GEN11_DE_TBT_HOTPLUG_MASK (0x3f) 785 786 #define GEN11_TBT_HOTPLUG_CTL 0x44030 787 #define GEN11_TC_HOTPLUG_CTL 0x44038 788 789 #define SHPD_FILTER_CNT 0xc4038 790 #define SHPD_FILTER_CNT_500_ADJ 0x1d9 791 792 #define SDEISR 0xc4000 793 #define SDEIMR 0xc4004 794 #define SDEIIR 0xc4008 795 #define SDEIER 0xc400c 796 #define SDE_GMBUS_ICP (1 << 23) 797 798 #define SHOTPLUG_CTL_DDI 0xc4030 799 #define SHOTPLUG_CTL_DDI_HPD_ENABLE(hpd_pin) (0x8 << (4 * ((hpd_pin) - HPD_PORT_A))) 800 #define SHOTPLUG_CTL_TC 0xc4034 801 #define SHOTPLUG_CTL_TC_HPD_ENABLE(hpd_pin) (0x8 << (4 * ((hpd_pin) - HPD_PORT_TC1))) 802 803 #define PCH_PORT_HOTPLUG SHOTPLUG_CTL_DDI 804 #define PCH_PORT_HOTPLUG2 0xc403c 805 806 #define PCH_INTERRUPT_VBLANK_BDW (1 << 0) // GEN8_PIPE_VBLANK 807 #define GEN8_PIPE_VSYNC (1 << 1) 808 #define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2) 809 810 #define GEN11_GFX_MSTR_IRQ 0x190010 811 #define GEN11_MASTER_IRQ (1 << 31) 812 #define GEN11_DISPLAY_IRQ (1 << 16) 813 #define GEN11_GT_DW1_IRQ (1 << 1) 814 #define GEN11_GT_DW0_IRQ (1 << 0) 815 816 #define GEN11_DISPLAY_INT_CTL 0x44200 // same as PCH_MASTER_INT_CTL_BDW 817 #define GEN11_DE_HPD_IRQ (1 << 21) 818 819 #define GEN11_GT_INTR_DW0 0x190018 820 #define GEN11_GT_INTR_DW1 0x19001c 821 822 #define GEN11_GU_MISC_IMR 0x444f4 823 #define GEN11_GU_MISC_IIR 0x444f8 824 #define GEN11_GU_MISC_IER 0x444fc 825 #define GEN11_GU_MISC_GSE (1 << 27) 826 827 828 // graphics port control (i.e. G45) 829 #define DISPLAY_MONITOR_PORT_ENABLED (1UL << 31) 830 #define DISPLAY_MONITOR_PIPE_B (1UL << 30) 831 #define DISPLAY_MONITOR_VGA_POLARITY (1UL << 15) 832 #define DISPLAY_MONITOR_MODE_MASK (3UL << 10) 833 #define DISPLAY_MONITOR_ON 0 834 #define DISPLAY_MONITOR_SUSPEND (1UL << 10) 835 #define DISPLAY_MONITOR_STAND_BY (2UL << 10) 836 #define DISPLAY_MONITOR_OFF (3UL << 10) 837 #define DISPLAY_MONITOR_POLARITY_MASK (3UL << 3) 838 #define DISPLAY_MONITOR_POSITIVE_HSYNC (1UL << 3) 839 #define DISPLAY_MONITOR_POSITIVE_VSYNC (2UL << 3) 840 #define DISPLAY_MONITOR_PORT_DETECTED (1UL << 2) // TMDS/DisplayPort only 841 842 // Cougar Point transcoder pipe selection 843 // (replaces DISPLAY_MONITOR_PIPE_B) 844 #define PORT_TRANS_A_SEL_CPT 0 845 #define PORT_TRANS_B_SEL_CPT (1<<29) 846 #define PORT_TRANS_C_SEL_CPT (2<<29) 847 #define PORT_TRANS_SEL_MASK (3<<29) 848 849 #define LVDS_POST2_RATE_SLOW 14 // PLL Divisors 850 #define LVDS_POST2_RATE_FAST 7 851 #define LVDS_B0B3_POWER_MASK (3UL << 2) 852 #define LVDS_B0B3_POWER_UP (3UL << 2) 853 #define LVDS_CLKB_POWER_MASK (3UL << 4) 854 #define LVDS_CLKB_POWER_UP (3UL << 4) 855 #define LVDS_A3_POWER_MASK (3UL << 6) 856 #define LVDS_A3_POWER_UP (3UL << 6) 857 #define LVDS_A0A2_CLKA_POWER_UP (3UL << 8) 858 #define LVDS_BORDER_ENABLE (1UL << 15) 859 #define LVDS_HSYNC_POLARITY (1UL << 20) 860 #define LVDS_VSYNC_POLARITY (1UL << 21) 861 #define LVDS_18BIT_DITHER (1UL << 25) 862 #define LVDS_PORT_EN (1UL << 31) 863 864 // PLL flags (pre-DDI) 865 #define DISPLAY_PLL_ENABLED (1UL << 31) 866 #define DISPLAY_PLL_2X_CLOCK (1UL << 30) 867 #define DISPLAY_PLL_SYNC_LOCK_ENABLED (1UL << 29) 868 #define DISPLAY_PLL_NO_VGA_CONTROL (1UL << 28) 869 #define DISPLAY_PLL_MODE_NORMAL (1UL << 26) 870 #define DISPLAY_PLL_MODE_LVDS (2UL << 26) 871 #define DISPLAY_PLL_DIVIDE_HIGH (1UL << 24) 872 #define DISPLAY_PLL_DIVIDE_4X (1UL << 23) 873 #define DISPLAY_PLL_POST1_DIVIDE_2 (1UL << 21) 874 #define DISPLAY_PLL_POST1_DIVISOR_MASK 0x001f0000 875 #define DISPLAY_PLL_9xx_POST1_DIVISOR_MASK 0x00ff0000 876 #define DISPLAY_PLL_SNB_FP0_POST1_DIVISOR_MASK 0x000000ff 877 #define DISPLAY_PLL_IGD_POST1_DIVISOR_MASK 0x00ff8000 878 #define DISPLAY_PLL_POST1_DIVISOR_SHIFT 16 879 #define DISPLAY_PLL_SNB_FP0_POST1_DIVISOR_SHIFT 0 880 #define DISPLAY_PLL_IGD_POST1_DIVISOR_SHIFT 15 881 #define DISPLAY_PLL_DIVISOR_1 (1UL << 8) 882 #define DISPLAY_PLL_N_DIVISOR_MASK 0x001f0000 883 #define DISPLAY_PLL_IGD_N_DIVISOR_MASK 0x00ff0000 884 #define DISPLAY_PLL_M1_DIVISOR_MASK 0x00001f00 885 #define DISPLAY_PLL_M2_DIVISOR_MASK 0x0000001f 886 #define DISPLAY_PLL_IGD_M2_DIVISOR_MASK 0x000000ff 887 #define DISPLAY_PLL_N_DIVISOR_SHIFT 16 888 #define DISPLAY_PLL_M1_DIVISOR_SHIFT 8 889 #define DISPLAY_PLL_M2_DIVISOR_SHIFT 0 890 #define DISPLAY_PLL_PULSE_PHASE_SHIFT 9 891 892 // Skylake PLLs 893 #define SKL_DPLL1_CFGCR1 (0xc040 | REGS_NORTH_PIPE_AND_PORT) 894 #define SKL_DPLL1_CFGCR2 (0xc044 | REGS_NORTH_PIPE_AND_PORT) 895 #define SKL_DPLL2_CFGCR1 (0xc048 | REGS_NORTH_PIPE_AND_PORT) 896 #define SKL_DPLL2_CFGCR2 (0xc04c | REGS_NORTH_PIPE_AND_PORT) 897 #define SKL_DPLL3_CFGCR1 (0xc050 | REGS_NORTH_PIPE_AND_PORT) 898 #define SKL_DPLL3_CFGCR2 (0xc054 | REGS_NORTH_PIPE_AND_PORT) 899 // These exist also still in CoffeeLake (confirmed): 900 #define SKL_DPLL_CTRL1 (0xc058 | REGS_NORTH_PIPE_AND_PORT) 901 #define SKL_DPLL_CTRL2 (0xc05c | REGS_NORTH_PIPE_AND_PORT) 902 #define SKL_DPLL_STATUS (0xc060 | REGS_NORTH_PIPE_AND_PORT) 903 #define SKL_DPLL0_DP_LINKRATE_SHIFT 1 904 #define SKL_DPLL1_DP_LINKRATE_SHIFT 7 905 #define SKL_DPLL2_DP_LINKRATE_SHIFT 13 906 #define SKL_DPLL3_DP_LINKRATE_SHIFT 19 907 #define SKL_DPLL_DP_LINKRATE_MASK 7 908 #define SKL_DPLL_CTRL1_2700 0 909 #define SKL_DPLL_CTRL1_1350 1 910 #define SKL_DPLL_CTRL1_810 2 911 #define SKL_DPLL_CTRL1_1620 3 912 #define SKL_DPLL_CTRL1_1080 4 913 #define SKL_DPLL_CTRL1_2160 5 914 915 // Icelake PLLs 916 #define ICL_DSSM 0x51004 917 #define ICL_DSSM_REF_FREQ_SHIFT 29 918 #define ICL_DSSM_REF_FREQ_MASK (7 << ICL_DSSM_REF_FREQ_SHIFT) 919 #define ICL_DSSM_24000 0 920 #define ICL_DSSM_19200 1 921 #define ICL_DSSM_38400 2 922 923 #define LCPLL_CTL 0x130040 924 #define LCPLL_CLK_FREQ_MASK (3 << 26) 925 #define LCPLL_CLK_FREQ_450 (0 << 26) 926 #define LCPLL_CLK_FREQ_54O_BDW (1 << 26) 927 #define LCPLL_CLK_FREQ_337_5_BDW (2 << 26) 928 #define LCPLL_CD_SOURCE_FCLK (1 << 21) 929 930 #define FUSE_STRAP 0x42014 931 #define HSW_CDCLK_LIMIT (1 << 24) 932 933 // display 934 935 #define INTEL_DISPLAY_OFFSET 0x1000 936 937 // Note: on Skylake below registers are part of the transcoder 938 #define INTEL_DISPLAY_A_HTOTAL (0x0000 | REGS_NORTH_PIPE_AND_PORT) 939 #define INTEL_DISPLAY_A_HBLANK (0x0004 | REGS_NORTH_PIPE_AND_PORT) 940 #define INTEL_DISPLAY_A_HSYNC (0x0008 | REGS_NORTH_PIPE_AND_PORT) 941 #define INTEL_DISPLAY_A_VTOTAL (0x000c | REGS_NORTH_PIPE_AND_PORT) 942 #define INTEL_DISPLAY_A_VBLANK (0x0010 | REGS_NORTH_PIPE_AND_PORT) 943 #define INTEL_DISPLAY_A_VSYNC (0x0014 | REGS_NORTH_PIPE_AND_PORT) 944 #define INTEL_DISPLAY_B_HTOTAL (0x1000 | REGS_NORTH_PIPE_AND_PORT) 945 #define INTEL_DISPLAY_B_HBLANK (0x1004 | REGS_NORTH_PIPE_AND_PORT) 946 #define INTEL_DISPLAY_B_HSYNC (0x1008 | REGS_NORTH_PIPE_AND_PORT) 947 #define INTEL_DISPLAY_B_VTOTAL (0x100c | REGS_NORTH_PIPE_AND_PORT) 948 #define INTEL_DISPLAY_B_VBLANK (0x1010 | REGS_NORTH_PIPE_AND_PORT) 949 #define INTEL_DISPLAY_B_VSYNC (0x1014 | REGS_NORTH_PIPE_AND_PORT) 950 951 #define INTEL_DISPLAY_A_PIPE_SIZE (0x001c | REGS_NORTH_PIPE_AND_PORT) 952 #define INTEL_DISPLAY_B_PIPE_SIZE (0x101c | REGS_NORTH_PIPE_AND_PORT) 953 954 //G45 displayport link 955 #define INTEL_PIPE_A_DATA_M (0x0050 | REGS_NORTH_PLANE_CONTROL) 956 #define INTEL_PIPE_B_DATA_M (0x1050 | REGS_NORTH_PLANE_CONTROL) 957 #define INTEL_PIPE_A_DATA_N (0x0054 | REGS_NORTH_PLANE_CONTROL) 958 #define INTEL_PIPE_B_DATA_N (0x1054 | REGS_NORTH_PLANE_CONTROL) 959 #define INTEL_PIPE_A_LINK_M (0x0060 | REGS_NORTH_PLANE_CONTROL) 960 #define INTEL_PIPE_B_LINK_M (0x1060 | REGS_NORTH_PLANE_CONTROL) 961 #define INTEL_PIPE_A_LINK_N (0x0064 | REGS_NORTH_PLANE_CONTROL) 962 #define INTEL_PIPE_B_LINK_N (0x1064 | REGS_NORTH_PLANE_CONTROL) 963 964 //DDI port link 965 #define INTEL_DDI_PIPE_A_DATA_M (0x0030 | REGS_NORTH_PIPE_AND_PORT) 966 #define INTEL_DDI_PIPE_B_DATA_M (0x1030 | REGS_NORTH_PIPE_AND_PORT) 967 #define INTEL_DDI_PIPE_A_DATA_N (0x0034 | REGS_NORTH_PIPE_AND_PORT) 968 #define INTEL_DDI_PIPE_B_DATA_N (0x1034 | REGS_NORTH_PIPE_AND_PORT) 969 #define INTEL_DDI_PIPE_A_LINK_M (0x0040 | REGS_NORTH_PIPE_AND_PORT) 970 #define INTEL_DDI_PIPE_B_LINK_M (0x1040 | REGS_NORTH_PIPE_AND_PORT) 971 #define INTEL_DDI_PIPE_A_LINK_N (0x0044 | REGS_NORTH_PIPE_AND_PORT) 972 #define INTEL_DDI_PIPE_B_LINK_N (0x1044 | REGS_NORTH_PIPE_AND_PORT) 973 974 // on PCH we also have to set the transcoder 975 #define INTEL_TRANSCODER_A_HTOTAL (0x0000 | REGS_SOUTH_TRANSCODER_PORT) 976 #define INTEL_TRANSCODER_A_HBLANK (0x0004 | REGS_SOUTH_TRANSCODER_PORT) 977 #define INTEL_TRANSCODER_A_HSYNC (0x0008 | REGS_SOUTH_TRANSCODER_PORT) 978 #define INTEL_TRANSCODER_A_VTOTAL (0x000c | REGS_SOUTH_TRANSCODER_PORT) 979 #define INTEL_TRANSCODER_A_VBLANK (0x0010 | REGS_SOUTH_TRANSCODER_PORT) 980 #define INTEL_TRANSCODER_A_VSYNC (0x0014 | REGS_SOUTH_TRANSCODER_PORT) 981 #define INTEL_TRANSCODER_B_HTOTAL (0x1000 | REGS_SOUTH_TRANSCODER_PORT) 982 #define INTEL_TRANSCODER_B_HBLANK (0x1004 | REGS_SOUTH_TRANSCODER_PORT) 983 #define INTEL_TRANSCODER_B_HSYNC (0x1008 | REGS_SOUTH_TRANSCODER_PORT) 984 #define INTEL_TRANSCODER_B_VTOTAL (0x100c | REGS_SOUTH_TRANSCODER_PORT) 985 #define INTEL_TRANSCODER_B_VBLANK (0x1010 | REGS_SOUTH_TRANSCODER_PORT) 986 #define INTEL_TRANSCODER_B_VSYNC (0x1014 | REGS_SOUTH_TRANSCODER_PORT) 987 988 // transcoder M/N DATA AND LINK VALUES (refreshrate) 989 #define INTEL_TRANSCODER_A_DATA_M1 (0x0030 | REGS_SOUTH_TRANSCODER_PORT) 990 #define INTEL_TRANSCODER_A_DATA_M2 (0x0038 | REGS_SOUTH_TRANSCODER_PORT) 991 #define INTEL_TRANSCODER_B_DATA_M1 (0x1030 | REGS_SOUTH_TRANSCODER_PORT) 992 #define INTEL_TRANSCODER_B_DATA_M2 (0x1038 | REGS_SOUTH_TRANSCODER_PORT) 993 #define INTEL_TRANSCODER_C_DATA_M1 (0x2030 | REGS_SOUTH_TRANSCODER_PORT) 994 #define INTEL_TRANSCODER_C_DATA_M2 (0x2038 | REGS_SOUTH_TRANSCODER_PORT) 995 #define INTEL_TRANSCODER_A_DATA_N1 (0x0034 | REGS_SOUTH_TRANSCODER_PORT) 996 #define INTEL_TRANSCODER_A_DATA_N2 (0x003c | REGS_SOUTH_TRANSCODER_PORT) 997 #define INTEL_TRANSCODER_B_DATA_N1 (0x1034 | REGS_SOUTH_TRANSCODER_PORT) 998 #define INTEL_TRANSCODER_B_DATA_N2 (0x103c | REGS_SOUTH_TRANSCODER_PORT) 999 #define INTEL_TRANSCODER_C_DATA_N1 (0x2034 | REGS_SOUTH_TRANSCODER_PORT) 1000 #define INTEL_TRANSCODER_C_DATA_N2 (0x203c | REGS_SOUTH_TRANSCODER_PORT) 1001 #define INTEL_TRANSCODER_A_LINK_M1 (0x0040 | REGS_SOUTH_TRANSCODER_PORT) 1002 #define INTEL_TRANSCODER_A_LINK_M2 (0x0048 | REGS_SOUTH_TRANSCODER_PORT) 1003 #define INTEL_TRANSCODER_B_LINK_M1 (0x1040 | REGS_SOUTH_TRANSCODER_PORT) 1004 #define INTEL_TRANSCODER_B_LINK_M2 (0x1048 | REGS_SOUTH_TRANSCODER_PORT) 1005 #define INTEL_TRANSCODER_C_LINK_M1 (0x2040 | REGS_SOUTH_TRANSCODER_PORT) 1006 #define INTEL_TRANSCODER_C_LINK_M2 (0x2048 | REGS_SOUTH_TRANSCODER_PORT) 1007 #define INTEL_TRANSCODER_A_LINK_N1 (0x0044 | REGS_SOUTH_TRANSCODER_PORT) 1008 #define INTEL_TRANSCODER_A_LINK_N2 (0x004c | REGS_SOUTH_TRANSCODER_PORT) 1009 #define INTEL_TRANSCODER_B_LINK_N1 (0x1044 | REGS_SOUTH_TRANSCODER_PORT) 1010 #define INTEL_TRANSCODER_B_LINK_N2 (0x104c | REGS_SOUTH_TRANSCODER_PORT) 1011 #define INTEL_TRANSCODER_C_LINK_N1 (0x2044 | REGS_SOUTH_TRANSCODER_PORT) 1012 #define INTEL_TRANSCODER_C_LINK_N2 (0x204c | REGS_SOUTH_TRANSCODER_PORT) 1013 #define INTEL_TRANSCODER_MN_TU_SIZE_MASK (0x3f << 25) 1014 #define INTEL_TRANSCODER_MN_VALUE_MASK (0xffffff << 0) 1015 1016 #define INTEL_TRANSCODER_A_IMAGE_SIZE (0x001c | REGS_SOUTH_TRANSCODER_PORT) 1017 #define INTEL_TRANSCODER_B_IMAGE_SIZE (0x101c | REGS_SOUTH_TRANSCODER_PORT) 1018 1019 // TODO: Is there consolidation that could happen here with digital ports? 1020 1021 #define INTEL_ANALOG_PORT (0x1100 | REGS_SOUTH_TRANSCODER_PORT) 1022 #define INTEL_DIGITAL_PORT_A (0x1120 | REGS_SOUTH_TRANSCODER_PORT) 1023 #define INTEL_DIGITAL_PORT_B (0x1140 | REGS_SOUTH_TRANSCODER_PORT) 1024 #define INTEL_DIGITAL_PORT_C (0x1160 | REGS_SOUTH_TRANSCODER_PORT) 1025 #define INTEL_DIGITAL_LVDS_PORT (0x1180 | REGS_SOUTH_TRANSCODER_PORT) 1026 1027 #define INTEL_HDMI_PORT_B (0x1140 | REGS_SOUTH_TRANSCODER_PORT) 1028 #define INTEL_HDMI_PORT_C (0x1160 | REGS_SOUTH_TRANSCODER_PORT) 1029 1030 #define PCH_HDMI_PORT_B (0x1140 | REGS_SOUTH_TRANSCODER_PORT) 1031 #define PCH_HDMI_PORT_C (0x1150 | REGS_SOUTH_TRANSCODER_PORT) 1032 #define PCH_HDMI_PORT_D (0x1160 | REGS_SOUTH_TRANSCODER_PORT) 1033 1034 #define GEN4_HDMI_PORT_B (0x1140 | REGS_SOUTH_TRANSCODER_PORT) 1035 #define GEN4_HDMI_PORT_C (0x1160 | REGS_SOUTH_TRANSCODER_PORT) 1036 #define CHV_HDMI_PORT_D (0x116C | REGS_SOUTH_TRANSCODER_PORT) 1037 1038 // DDI Buffer Control (This replaces DP on Haswell+) 1039 #define DDI_BUF_CTL_A (0x4000 | REGS_NORTH_PIPE_AND_PORT) 1040 #define DDI_BUF_CTL_B (0x4100 | REGS_NORTH_PIPE_AND_PORT) 1041 #define DDI_BUF_CTL_C (0x4200 | REGS_NORTH_PIPE_AND_PORT) 1042 #define DDI_BUF_CTL_D (0x4300 | REGS_NORTH_PIPE_AND_PORT) 1043 #define DDI_BUF_CTL_E (0x4400 | REGS_NORTH_PIPE_AND_PORT) 1044 #define DDI_BUF_CTL_F (0x4500 | REGS_NORTH_PIPE_AND_PORT) 1045 #define DDI_BUF_CTL_ENABLE (1 << 31) 1046 #define DDI_BUF_TRANS_SELECT(n) ((n) << 24) 1047 #define DDI_BUF_EMP_MASK (0xf << 24) 1048 #define DDI_BUF_PORT_REVERSAL (1 << 16) 1049 #define DDI_BUF_IS_IDLE (1 << 7) 1050 #define DDI_A_4_LANES (1 << 4) 1051 #define DDI_PORT_WIDTH(width) (((width) - 1) << 1) 1052 #define DDI_INIT_DISPLAY_DETECTED (1 << 0) 1053 1054 #define PIPE_DDI_FUNC_CTL_A (0x0400 | REGS_NORTH_PIPE_AND_PORT) 1055 #define PIPE_DDI_FUNC_CTL_B (0x1400 | REGS_NORTH_PIPE_AND_PORT) 1056 #define PIPE_DDI_FUNC_CTL_C (0x2400 | REGS_NORTH_PIPE_AND_PORT) 1057 #define PIPE_DDI_FUNC_CTL_EDP (0xF400 | REGS_NORTH_PIPE_AND_PORT) 1058 #define PIPE_DDI_FUNC_CTL_ENABLE (1 << 31) 1059 #define PIPE_DDI_SELECT_SHIFT 28 1060 #define PIPE_DDI_SELECT_PORT(x) ((x) << PIPE_DDI_SELECT_SHIFT) 1061 #define PIPE_DDI_SELECT_MASK (7 << PIPE_DDI_SELECT_SHIFT) 1062 #define PIPE_DDI_PORT_NONE 0 1063 #define PIPE_DDI_PORT_B 1 1064 #define PIPE_DDI_PORT_C 2 1065 #define PIPE_DDI_PORT_D 3 1066 #define PIPE_DDI_PORT_E 4 1067 #define PIPE_DDI_PORT_F 5 1068 #define PIPE_DDI_MODESEL_SHIFT 24 1069 #define PIPE_DDI_MODESEL_MODE(x) ((x) << PIPE_DDI_MODESEL_SHIFT) 1070 #define PIPE_DDI_MODESEL_MASK (7 << PIPE_DDI_MODESEL_SHIFT) 1071 #define PIPE_DDI_MODE_HDMI 0 1072 #define PIPE_DDI_MODE_DVI 1 1073 #define PIPE_DDI_MODE_DP_SST 2 1074 #define PIPE_DDI_MODE_DP_MST 3 1075 #define PIPE_DDI_COLOR_SHIFT 20 1076 #define PIPE_DDI_BPC(x) ((x) << PIPE_DDI_COLOR_SHIFT) 1077 #define PIPE_DDI_BPC_MASK (7 << PIPE_DDI_COLOR_SHIFT) 1078 #define PIPE_DDI_8BPC 0 1079 #define PIPE_DDI_10BPC 1 1080 #define PIPE_DDI_6BPC 2 1081 #define PIPE_DDI_12BPC 3 1082 #define PIPE_DDI_DP_WIDTH_SHIFT 1 1083 #define PIPE_DDI_DP_WIDTH_SEL(x) ((x) << PIPE_DDI_DP_WIDTH_SHIFT) 1084 #define PIPE_DDI_DP_WIDTH_MASK (7 << PIPE_DDI_DP_WIDTH_SHIFT) 1085 #define PIPE_DDI_DP_WIDTH_1 0 1086 #define PIPE_DDI_DP_WIDTH_2 1 1087 #define PIPE_DDI_DP_WIDTH_4 2 1088 1089 // DP_A always @ 6xxxx, DP_B-DP_D move with PCH 1090 #define INTEL_DISPLAY_PORT_A (0x4000 | REGS_NORTH_PIPE_AND_PORT) 1091 #define INTEL_DISPLAY_PORT_B (0x4100 | REGS_SOUTH_TRANSCODER_PORT) 1092 #define INTEL_DISPLAY_PORT_C (0x4200 | REGS_SOUTH_TRANSCODER_PORT) 1093 #define INTEL_DISPLAY_PORT_D (0x4300 | REGS_SOUTH_TRANSCODER_PORT) 1094 1095 #define INTEL_DISP_PORTA_SNB_PIPE_SHIFT 30 1096 #define INTEL_DISP_PORTA_SNB_PIPE_MASK (1 << INTEL_DISP_PORTA_SNB_PIPE_SHIFT) 1097 #define INTEL_DISP_PORTA_SNB_PIPE_A 0 1098 #define INTEL_DISP_PORTA_SNB_PIPE_B 1 1099 #define INTEL_DISP_PORTA_IVB_PIPE_SHIFT 29 1100 #define INTEL_DISP_PORTA_IVB_PIPE_MASK (3 << INTEL_DISP_PORTA_IVB_PIPE_SHIFT) 1101 #define INTEL_DISP_PORTA_IVB_PIPE_A 0 1102 #define INTEL_DISP_PORTA_IVB_PIPE_B 1 1103 #define INTEL_DISP_PORTA_IVB_PIPE_C 2 1104 1105 #define INTEL_DISP_PORT_WIDTH_SHIFT 19 1106 #define INTEL_DISP_PORT_WIDTH_MASK (7 << INTEL_DISP_PORT_WIDTH_SHIFT) 1107 #define INTEL_DISP_PORT_WIDTH_1 0 1108 #define INTEL_DISP_PORT_WIDTH_2 1 1109 #define INTEL_DISP_PORT_WIDTH_4 3 1110 #define INTEL_DISP_EDP_PLL_FREQ_SHIFT 16 1111 #define INTEL_DISP_EDP_PLL_FREQ_MASK (3 << INTEL_DISP_EDP_PLL_FREQ_SHIFT) 1112 #define INTEL_DISP_EDP_PLL_FREQ_270 0 1113 #define INTEL_DISP_EDP_PLL_FREQ_162 1 1114 1115 #define INTEL_TRANSCODER_A_DP_CTL (0x0300 | REGS_SOUTH_TRANSCODER_PORT) 1116 #define INTEL_TRANSCODER_B_DP_CTL (0x1300 | REGS_SOUTH_TRANSCODER_PORT) 1117 #define INTEL_TRANSCODER_C_DP_CTL (0x2300 | REGS_SOUTH_TRANSCODER_PORT) 1118 1119 #define INTEL_TRANS_DP_COLOR_SHIFT 9 1120 #define INTEL_TRANS_DP_BPC(x) ((x) << INTEL_TRANS_DP_COLOR_SHIFT) 1121 #define INTEL_TRANS_DP_BPC_MASK (7 << INTEL_TRANS_DP_COLOR_SHIFT) 1122 #define INTEL_TRANS_DP_PORT_SHIFT 29 1123 #define INTEL_TRANS_DP_PORT(x) ((x) << INTEL_TRANS_DP_PORT_SHIFT) 1124 #define INTEL_TRANS_DP_PORT_MASK (3 << INTEL_TRANS_DP_PORT_SHIFT) 1125 #define INTEL_TRANS_DP_PORT_B 0 1126 #define INTEL_TRANS_DP_PORT_C 1 1127 #define INTEL_TRANS_DP_PORT_D 2 1128 #define INTEL_TRANS_DP_PORT_NONE 3 1129 1130 // Unless you're a damn Valley/CherryView unicorn :-( 1131 #define VLV_DISPLAY_PORT_B (VLV_DISPLAY_BASE + 0x64100) 1132 #define VLV_DISPLAY_PORT_C (VLV_DISPLAY_BASE + 0x64200) 1133 #define CHV_DISPLAY_PORT_D (VLV_DISPLAY_BASE + 0x64300) 1134 1135 // DP AUX channels 1136 #define _DPA_AUX_CH_CTL (0x4010 | REGS_NORTH_PIPE_AND_PORT) 1137 #define _DPA_AUX_CH_DATA1 (0x4014 | REGS_NORTH_PIPE_AND_PORT) 1138 #define _DPB_AUX_CH_CTL (0x4110 | REGS_NORTH_PIPE_AND_PORT) 1139 #define _DPB_AUX_CH_DATA1 (0x4114 | REGS_NORTH_PIPE_AND_PORT) 1140 #define DP_AUX_CH_CTL(aux) \ 1141 (_DPA_AUX_CH_CTL + (_DPB_AUX_CH_CTL - _DPA_AUX_CH_CTL) * aux) 1142 #define DP_AUX_CH_DATA(aux, i) \ 1143 (_DPA_AUX_CH_DATA1 + (_DPB_AUX_CH_DATA1 - _DPA_AUX_CH_DATA1) * aux + i * 4) 1144 #define _PCH_DPB_AUX_CH_CTL (0x4110 | REGS_SOUTH_TRANSCODER_PORT) 1145 #define _PCH_DPB_AUX_CH_DATA1 (0x4114 | REGS_SOUTH_TRANSCODER_PORT) 1146 #define _PCH_DPC_AUX_CH_CTL (0x4210 | REGS_SOUTH_TRANSCODER_PORT) 1147 #define _PCH_DPC_AUX_CH_DATA1 (0x4214 | REGS_SOUTH_TRANSCODER_PORT) 1148 #define PCH_DP_AUX_CH_CTL(aux) \ 1149 (_PCH_DPB_AUX_CH_CTL + (_PCH_DPC_AUX_CH_CTL - _PCH_DPB_AUX_CH_CTL) * (aux - AUX_CH_B)) 1150 #define PCH_DP_AUX_CH_DATA(aux, i) \ 1151 (_PCH_DPB_AUX_CH_DATA1 + (_PCH_DPC_AUX_CH_DATA1 - _PCH_DPB_AUX_CH_DATA1) * (aux - AUX_CH_B) \ 1152 + i * 4) 1153 1154 #define INTEL_DP_AUX_CTL_BUSY (1 << 31) 1155 #define INTEL_DP_AUX_CTL_DONE (1 << 30) 1156 #define INTEL_DP_AUX_CTL_INTERRUPT (1 << 29) 1157 #define INTEL_DP_AUX_CTL_TIMEOUT_ERROR (1 << 28) 1158 #define INTEL_DP_AUX_CTL_TIMEOUT_400us (0 << 26) 1159 #define INTEL_DP_AUX_CTL_TIMEOUT_600us (1 << 26) 1160 #define INTEL_DP_AUX_CTL_TIMEOUT_800us (2 << 26) 1161 #define INTEL_DP_AUX_CTL_TIMEOUT_1600us (3 << 26) 1162 #define INTEL_DP_AUX_CTL_TIMEOUT_MASK (3 << 26) 1163 #define INTEL_DP_AUX_CTL_RECEIVE_ERROR (1 << 25) 1164 #define INTEL_DP_AUX_CTL_MSG_SIZE_MASK (0x1f << 20) 1165 #define INTEL_DP_AUX_CTL_MSG_SIZE_SHIFT 20 1166 #define INTEL_DP_AUX_CTL_PRECHARGE_2US_MASK (0xf << 16) 1167 #define INTEL_DP_AUX_CTL_PRECHARGE_2US_SHIFT 16 1168 #define INTEL_DP_AUX_CTL_BIT_CLOCK_2X_MASK (0x7ff) 1169 #define INTEL_DP_AUX_CTL_BIT_CLOCK_2X_SHIFT 0 1170 #define INTEL_DP_AUX_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5) 1171 #define INTEL_DP_AUX_CTL_SYNC_PULSE_SKL(c) ((c) - 1) 1172 1173 // planes 1174 #define INTEL_PIPE_ENABLED (1UL << 31) 1175 #define INTEL_PIPE_STATE (1UL << 30) 1176 1177 #define INTEL_PLANE_OFFSET 0x1000 1178 1179 #define INTEL_DISPLAY_A_PIPE_CONTROL (0x0008 | REGS_NORTH_PLANE_CONTROL) 1180 #define INTEL_DISPLAY_B_PIPE_CONTROL (0x1008 | REGS_NORTH_PLANE_CONTROL) 1181 #define INTEL_DISPLAY_C_PIPE_CONTROL (0x2008 | REGS_NORTH_PLANE_CONTROL) 1182 #define INTEL_DISPLAY_A_PIPE_STATUS (0x0024 | REGS_NORTH_PLANE_CONTROL) 1183 #define INTEL_DISPLAY_B_PIPE_STATUS (0x1024 | REGS_NORTH_PLANE_CONTROL) 1184 1185 #define INTEL_DISPLAY_A_PIPE_WATERMARK (0x5100 | REGS_NORTH_PLANE_CONTROL) 1186 #define INTEL_DISPLAY_B_PIPE_WATERMARK (0x5104 | REGS_NORTH_PLANE_CONTROL) 1187 #define INTEL_DISPLAY_C_PIPE_WATERMARK (0x5200 | REGS_NORTH_PLANE_CONTROL) 1188 1189 #define DISPLAY_PIPE_VBLANK_ENABLED (1UL << 17) 1190 #define DISPLAY_PIPE_VBLANK_STATUS (1UL << 1) 1191 1192 #define INTEL_DISPLAY_A_CONTROL (0x0180 | REGS_NORTH_PLANE_CONTROL) 1193 #define INTEL_DISPLAY_A_BASE (0x0184 | REGS_NORTH_PLANE_CONTROL) 1194 #define INTEL_DISPLAY_A_BYTES_PER_ROW (0x0188 | REGS_NORTH_PLANE_CONTROL) 1195 #define INTEL_DISPLAY_A_POS (0x018c | REGS_NORTH_PLANE_CONTROL) 1196 // reserved on A 1197 #define INTEL_DISPLAY_A_IMAGE_SIZE (0x0190 | REGS_NORTH_PLANE_CONTROL) 1198 #define INTEL_DISPLAY_A_SURFACE (0x019c | REGS_NORTH_PLANE_CONTROL) 1199 #define INTEL_DISPLAY_A_OFFSET_HAS (0x01a4 | REGS_NORTH_PLANE_CONTROL) 1200 // i965 and up only 1201 1202 #define INTEL_DISPLAY_B_CONTROL (0x1180 | REGS_NORTH_PLANE_CONTROL) 1203 #define INTEL_DISPLAY_B_BASE (0x1184 | REGS_NORTH_PLANE_CONTROL) 1204 #define INTEL_DISPLAY_B_BYTES_PER_ROW (0x1188 | REGS_NORTH_PLANE_CONTROL) 1205 #define INTEL_DISPLAY_B_POS (0x118c | REGS_NORTH_PLANE_CONTROL) 1206 #define INTEL_DISPLAY_B_IMAGE_SIZE (0x1190 | REGS_NORTH_PLANE_CONTROL) 1207 #define INTEL_DISPLAY_B_SURFACE (0x119c | REGS_NORTH_PLANE_CONTROL) 1208 #define INTEL_DISPLAY_B_OFFSET_HAS (0x11a4 | REGS_NORTH_PLANE_CONTROL) 1209 // i965 and up only 1210 1211 // INTEL_DISPLAY_A_CONTROL source pixel format 1212 #define DISPLAY_CONTROL_ENABLED (1UL << 31) 1213 #define DISPLAY_CONTROL_GAMMA (1UL << 30) 1214 #define DISPLAY_CONTROL_COLOR_MASK (0x0fUL << 26) 1215 #define DISPLAY_CONTROL_CMAP8 (2UL << 26) 1216 #define DISPLAY_CONTROL_RGB15 (4UL << 26) 1217 #define DISPLAY_CONTROL_RGB16 (5UL << 26) 1218 #define DISPLAY_CONTROL_RGB32 (6UL << 26) 1219 #define DISPLAY_CONTROL_RGB64 (0x0cUL << 26) 1220 // Skylake 1221 #define DISPLAY_CONTROL_COLOR_MASK_SKY (0x0fUL << 24) 1222 #define DISPLAY_CONTROL_CMAP8_SKY (0x0cUL << 24) 1223 #define DISPLAY_CONTROL_RGB15_SKY (0x0eUL << 24) 1224 #define DISPLAY_CONTROL_RGB16_SKY (0x0eUL << 24) 1225 #define DISPLAY_CONTROL_RGB32_SKY (0x04UL << 24) 1226 #define DISPLAY_CONTROL_RGB64_SKY (0x06UL << 24) 1227 1228 // INTEL_DISPLAY_A_PIPE_CONTROL ILK+ 1229 #define INTEL_PIPE_DITHER_TYPE_MASK (0x0000000c) 1230 #define INTEL_PIPE_DITHER_TYPE_SP (0 << 2) 1231 #define INTEL_PIPE_DITHER_TYPE_ST1 (1 << 2) 1232 #define INTEL_PIPE_DITHER_TYPE_ST2 (2 << 2) 1233 #define INTEL_PIPE_DITHER_TYPE_TEMP (3 << 2) 1234 #define INTEL_PIPE_DITHER_EN (1 << 4) 1235 #define INTEL_PIPE_COLOR_SHIFT 5 1236 #define INTEL_PIPE_BPC(x) ((x) << INTEL_PIPE_COLOR_SHIFT) 1237 #define INTEL_PIPE_BPC_MASK (7 << INTEL_PIPE_COLOR_SHIFT) 1238 #define INTEL_PIPE_8BPC 0 1239 #define INTEL_PIPE_10BPC 1 1240 #define INTEL_PIPE_6BPC 2 1241 #define INTEL_PIPE_12BPC 3 1242 #define INTEL_PIPE_PROGRESSIVE (0 << 21) 1243 1244 // cursors 1245 #define INTEL_CURSOR_CONTROL (0x0080 | REGS_NORTH_PLANE_CONTROL) 1246 #define INTEL_CURSOR_BASE (0x0084 | REGS_NORTH_PLANE_CONTROL) 1247 #define INTEL_CURSOR_POSITION (0x0088 | REGS_NORTH_PLANE_CONTROL) 1248 #define INTEL_CURSOR_PALETTE (0x0090 | REGS_NORTH_PLANE_CONTROL) 1249 // (- 0x009f) 1250 #define INTEL_CURSOR_SIZE (0x00a0 | REGS_NORTH_PLANE_CONTROL) 1251 #define CURSOR_ENABLED (1UL << 31) 1252 #define CURSOR_FORMAT_2_COLORS (0UL << 24) 1253 #define CURSOR_FORMAT_3_COLORS (1UL << 24) 1254 #define CURSOR_FORMAT_4_COLORS (2UL << 24) 1255 #define CURSOR_FORMAT_ARGB (4UL << 24) 1256 #define CURSOR_FORMAT_XRGB (5UL << 24) 1257 #define CURSOR_POSITION_NEGATIVE 0x8000 1258 #define CURSOR_POSITION_MASK 0x3fff 1259 1260 // palette registers 1261 #define INTEL_DISPLAY_A_PALETTE (0xa000 | REGS_NORTH_SHARED) 1262 #define INTEL_DISPLAY_B_PALETTE (0xa800 | REGS_NORTH_SHARED) 1263 1264 // Ironlake PCH reference clk control 1265 #define PCH_DREF_CONTROL (0x6200 | REGS_SOUTH_SHARED) 1266 #define DREF_CONTROL_MASK 0x7fc3 1267 #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0 << 13) 1268 #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2 << 13) 1269 #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3 << 13) 1270 #define DREF_CPU_SOURCE_OUTPUT_MASK (3 << 13) 1271 #define DREF_SSC_SOURCE_DISABLE (0 << 11) 1272 #define DREF_SSC_SOURCE_ENABLE (2 << 11) 1273 #define DREF_SSC_SOURCE_MASK (3 << 11) 1274 #define DREF_NONSPREAD_SOURCE_DISABLE (0 << 9) 1275 #define DREF_NONSPREAD_CK505_ENABLE (1 << 9) 1276 #define DREF_NONSPREAD_SOURCE_ENABLE (2 << 9) 1277 #define DREF_NONSPREAD_SOURCE_MASK (3 << 9) 1278 #define DREF_SUPERSPREAD_SOURCE_DISABLE (0 << 7) 1279 #define DREF_SUPERSPREAD_SOURCE_ENABLE (2 << 7) 1280 #define DREF_SUPERSPREAD_SOURCE_MASK (3 << 7) 1281 #define DREF_SSC4_DOWNSPREAD (0 << 6) 1282 #define DREF_SSC4_CENTERSPREAD (1 << 6) 1283 #define DREF_SSC1_DISABLE (0 << 1) 1284 #define DREF_SSC1_ENABLE (1 << 1) 1285 #define DREF_SSC4_DISABLE (0 << 0) 1286 #define DREF_SSC4_ENABLE (1 << 0) 1287 1288 #define PCH_RAWCLK_FREQ (0x6204 | REGS_SOUTH_SHARED) 1289 #define RAWCLK_FREQ_MASK 0x3ff 1290 1291 // PLL registers 1292 // Multiplier Divisor 1293 #define INTEL_DISPLAY_A_PLL (0x6014 | REGS_SOUTH_SHARED) 1294 #define INTEL_DISPLAY_B_PLL (0x6018 | REGS_SOUTH_SHARED) 1295 #define INTEL_DISPLAY_A_PLL_MD (0x601C | REGS_SOUTH_SHARED) 1296 #define INTEL_DISPLAY_B_PLL_MD (0x6020 | REGS_SOUTH_SHARED) 1297 #define CHV_DISPLAY_C_PLL (0x6030 | REGS_SOUTH_SHARED) 1298 #define CHV_DISPLAY_B_PLL_MD (0x603C | REGS_SOUTH_SHARED) 1299 1300 #define INTEL_DISPLAY_A_PLL_DIVISOR_0 (0x6040 | REGS_SOUTH_SHARED) 1301 #define INTEL_DISPLAY_A_PLL_DIVISOR_1 (0x6044 | REGS_SOUTH_SHARED) 1302 #define INTEL_DISPLAY_B_PLL_DIVISOR_0 (0x6048 | REGS_SOUTH_SHARED) 1303 #define INTEL_DISPLAY_B_PLL_DIVISOR_1 (0x604c | REGS_SOUTH_SHARED) 1304 1305 #define SNB_DPLL_SEL (0x7000 | REGS_SOUTH_SHARED) 1306 1307 // i2c bit banging interface 1308 #define INTEL_I2C_IO_A (0x5010 | REGS_SOUTH_SHARED) 1309 #define INTEL_I2C_IO_B (0x5014 | REGS_SOUTH_SHARED) 1310 #define INTEL_I2C_IO_C (0x5018 | REGS_SOUTH_SHARED) 1311 #define INTEL_I2C_IO_D (0x501c | REGS_SOUTH_SHARED) 1312 #define INTEL_I2C_IO_E (0x5020 | REGS_SOUTH_SHARED) 1313 #define INTEL_I2C_IO_F (0x5024 | REGS_SOUTH_SHARED) 1314 #define INTEL_I2C_IO_G (0x5028 | REGS_SOUTH_SHARED) 1315 #define INTEL_I2C_IO_H (0x502c | REGS_SOUTH_SHARED) 1316 // i2c hardware controller 1317 #define INTEL_GMBUS0 (0x5100 | REGS_SOUTH_SHARED) 1318 #define INTEL_GMBUS4 (0x5110 | REGS_SOUTH_SHARED) 1319 1320 #define I2C_CLOCK_DIRECTION_MASK (1 << 0) 1321 #define I2C_CLOCK_DIRECTION_OUT (1 << 1) 1322 #define I2C_CLOCK_VALUE_MASK (1 << 2) 1323 #define I2C_CLOCK_VALUE_OUT (1 << 3) 1324 #define I2C_CLOCK_VALUE_IN (1 << 4) 1325 #define I2C_DATA_DIRECTION_MASK (1 << 8) 1326 #define I2C_DATA_DIRECTION_OUT (1 << 9) 1327 #define I2C_DATA_VALUE_MASK (1 << 10) 1328 #define I2C_DATA_VALUE_OUT (1 << 11) 1329 #define I2C_DATA_VALUE_IN (1 << 12) 1330 #define I2C_RESERVED ((1 << 13) | (1 << 5)) 1331 1332 // gpu block clock gating disable bits 1333 #define INTEL_DSPCLK_GATE_D (0x2020 | REGS_SOUTH_SHARED) 1334 #define PCH_GMBUSUNIT_CLK_GATE_DIS (1UL << 31) 1335 #define INTEL_GEN9_CLKGATE_DIS_4 (0x653c | REGS_NORTH_SHARED) 1336 #define BXT_GMBUSUNIT_CLK_GATE_DIS (1 << 14) 1337 1338 // gpu power wells (confirmed skylake) 1339 #define INTEL_PWR_WELL_CTL_1_BIOS (0x5400 | REGS_NORTH_SHARED) 1340 #define INTEL_PWR_WELL_CTL_2_DRIVER (0x5404 | REGS_NORTH_SHARED) 1341 1342 #define HSW_PWR_WELL_CTL_REQ(i) (0x2 << ((2 * i))) 1343 #define HSW_PWR_WELL_CTL_STATE(i) (0x1 << ((2 * i))) 1344 1345 #define HSW_PWR_WELL_CTL1 INTEL_PWR_WELL_CTL_1_BIOS 1346 #define HSW_PWR_WELL_CTL2 INTEL_PWR_WELL_CTL_2_DRIVER 1347 #define HSW_PWR_WELL_CTL3 (0x5408 | REGS_NORTH_SHARED) 1348 #define HSW_PWR_WELL_CTL4 (0x540c | REGS_NORTH_SHARED) 1349 1350 #define ICL_PWR_WELL_CTL_AUX1 (0x5440 | REGS_NORTH_SHARED) 1351 #define ICL_PWR_WELL_CTL_AUX2 (0x5444 | REGS_NORTH_SHARED) 1352 #define ICL_PWR_WELL_CTL_AUX4 (0x544c | REGS_NORTH_SHARED) 1353 1354 #define ICL_PWR_WELL_CTL_DDI1 (0x5450 | REGS_NORTH_SHARED) 1355 #define ICL_PWR_WELL_CTL_DDI2 (0x5454 | REGS_NORTH_SHARED) 1356 #define ICL_PWR_WELL_CTL_DDI4 (0x545c | REGS_NORTH_SHARED) 1357 1358 // gpu pll enable registers (confirmed skylake) 1359 #define INTEL_WRPLL_CTL_1_DPLL2 (0x6040 | REGS_NORTH_SHARED) 1360 #define INTEL_WRPLL_CTL_2_DPLL3 (0x6060 | REGS_NORTH_SHARED) 1361 #define WRPLL_PLL_ENABLE (1 << 31) 1362 1363 // TODO: on IronLake this is in the north shared block at 0x41000 1364 #define INTEL_VGA_DISPLAY_CONTROL (0x1400 | REGS_NORTH_PLANE_CONTROL) 1365 #define VGA_DISPLAY_DISABLED (1UL << 31) 1366 1367 // LVDS panel 1368 #define INTEL_PANEL_STATUS (0x1200 | REGS_NORTH_PIPE_AND_PORT) 1369 #define INTEL_PANEL_CONTROL (0x1204 | REGS_NORTH_PIPE_AND_PORT) 1370 #define INTEL_PANEL_FIT_CONTROL (0x1230 | REGS_NORTH_PIPE_AND_PORT) 1371 #define INTEL_PANEL_FIT_RATIOS (0x1234 | REGS_NORTH_PIPE_AND_PORT) 1372 1373 // LVDS on IronLake and up 1374 #define PCH_PANEL_STATUS (0x7200 | REGS_SOUTH_SHARED) 1375 #define PCH_PANEL_CONTROL (0x7204 | REGS_SOUTH_SHARED) 1376 #define PCH_PANEL_ON_DELAYS (0x7208 | REGS_SOUTH_SHARED) 1377 #define PCH_PANEL_OFF_DELAYS (0x720c | REGS_SOUTH_SHARED) 1378 #define PCH_PANEL_DIVISOR (0x7210 | REGS_SOUTH_SHARED) 1379 #define PCH_LVDS_DETECTED (1 << 1) 1380 1381 #define PANEL_STATUS_POWER_ON (1UL << 31) 1382 #define PANEL_CONTROL_POWER_TARGET_OFF (0UL << 0) 1383 #define PANEL_CONTROL_POWER_TARGET_ON (1UL << 0) 1384 #define PANEL_CONTROL_POWER_TARGET_RST (1UL << 1) 1385 #define PANEL_REGISTER_UNLOCK (0xabcd << 16) 1386 1387 // PCH_PANEL_ON_DELAYS 1388 #define PANEL_DELAY_PORT_SELECT_MASK (3 << 30) 1389 #define PANEL_DELAY_PORT_SELECT_LVDS (0 << 30) 1390 #define PANEL_DELAY_PORT_SELECT_DPA (1 << 30) 1391 #define PANEL_DELAY_PORT_SELECT_DPC (2 << 30) 1392 #define PANEL_DELAY_PORT_SELECT_DPD (3 << 30) 1393 1394 // PCH_PANEL_DIVISOR 1395 #define PANEL_DIVISOR_REFERENCE_DIV_MASK 0xffffff00 1396 #define PANEL_DIVISOR_REFERENCE_DIV_SHIFT 8 1397 #define PANEL_DIVISOR_POW_CYCLE_DLY_MASK 0x1f 1398 #define PANEL_DIVISOR_POW_CYCLE_DLY_SHIFT 0x1f 1399 1400 // Backlight control registers 1401 // These have moved around, initially they were per pipe, then they were moved in the "north" part 1402 // of the PCH with a single backlight control (independant of pipes), and then moved again to the 1403 // "south" part of the PCH, with a simplified register layout. 1404 #define PCH_BLC_PWM_CTL2 (0x8250 | REGS_NORTH_SHARED) // Linux BLC_PWM_CPU_CTL2 1405 #define PCH_BLC_PWM_CTL (0x8254 | REGS_NORTH_SHARED) // Linux BLC_PWM_CPU_CTL 1406 1407 // Kaby Lake/Sunrisepoint 1408 #define BLC_PWM_PCH_CTL1 (0x8250 | REGS_SOUTH_SHARED) // Enable with bit 31 1409 #define BLC_PWM_PCH_CTL2 (0x8254 | REGS_SOUTH_SHARED) // Duty Cycle and Period 1410 1411 // Devices after Cannonlake have a new register layout, with separate registers for the period 1412 // and duty cycle instead of having two 16bit values in a 32bit register 1413 #define PCH_SOUTH_BLC_PWM_CONTROL (0x8250 | REGS_SOUTH_SHARED) // Linux _BXT_BLC_PWM_CTL1 1414 #define PCH_SOUTH_BLC_PWM_PERIOD (0x8254 | REGS_SOUTH_SHARED) // Linux _BXT_BLC_PWM_FREQ1 1415 #define PCH_SOUTH_BLC_PWM_DUTY_CYCLE (0x8258 | REGS_SOUTH_SHARED) // Linux _BXT_BLC_PWM_DUTY1 1416 1417 #define MCH_BLC_PWM_CTL (0x1254 | REGS_NORTH_PIPE_AND_PORT) 1418 // Linux VLV_BLC_PWM_CTL (one register per pipe) or BLC_PWM_CTL (a single register that can be 1419 // programmed for use on either pipe) 1420 #define BLM_LEGACY_MODE (1 << 16) 1421 1422 // ring buffer commands 1423 1424 #define COMMAND_NOOP 0x00 1425 #define COMMAND_WAIT_FOR_EVENT (0x03 << 23) 1426 #define COMMAND_WAIT_FOR_OVERLAY_FLIP (1 << 16) 1427 1428 #define COMMAND_FLUSH (0x04 << 23) 1429 1430 // overlay flip 1431 #define COMMAND_OVERLAY_FLIP (0x11 << 23) 1432 #define COMMAND_OVERLAY_CONTINUE (0 << 21) 1433 #define COMMAND_OVERLAY_ON (1 << 21) 1434 #define COMMAND_OVERLAY_OFF (2 << 21) 1435 #define OVERLAY_UPDATE_COEFFICIENTS 0x1 1436 1437 // 2D acceleration 1438 #define XY_COMMAND_SOURCE_BLIT 0x54c00006 1439 #define XY_COMMAND_COLOR_BLIT 0x54000004 1440 #define XY_COMMAND_SETUP_MONO_PATTERN 0x44400007 1441 #define XY_COMMAND_SCANLINE_BLIT 0x49400001 1442 #define COMMAND_COLOR_BLIT 0x50000003 1443 #define COMMAND_BLIT_RGBA 0x00300000 1444 1445 #define COMMAND_MODE_SOLID_PATTERN 0x80 1446 #define COMMAND_MODE_CMAP8 0x00 1447 #define COMMAND_MODE_RGB15 0x02 1448 #define COMMAND_MODE_RGB16 0x01 1449 #define COMMAND_MODE_RGB32 0x03 1450 1451 // overlay 1452 #define INTEL_OVERLAY_UPDATE 0x30000 1453 #define INTEL_OVERLAY_TEST 0x30004 1454 #define INTEL_OVERLAY_STATUS 0x30008 1455 #define INTEL_OVERLAY_EXTENDED_STATUS 0x3000c 1456 #define INTEL_OVERLAY_GAMMA_5 0x30010 1457 #define INTEL_OVERLAY_GAMMA_4 0x30014 1458 #define INTEL_OVERLAY_GAMMA_3 0x30018 1459 #define INTEL_OVERLAY_GAMMA_2 0x3001c 1460 #define INTEL_OVERLAY_GAMMA_1 0x30020 1461 #define INTEL_OVERLAY_GAMMA_0 0x30024 1462 1463 // FDI - Flexible Display Interface, the interface between the (CPU-internal) 1464 // GPU and the PCH display outputs. Proprietary interface, based on DisplayPort 1465 // though, so similar link training and all... 1466 // There's an FDI transmitter (TX) on the CPU and an FDI receiver (RX) on the 1467 // PCH for each display pipe. 1468 // FDI receiver A is hooked up to transcoder A, FDI receiver B is hooked up to 1469 // transcoder B, so we have the same mapping as with the display pipes. 1470 #define _FDI_RXA_CTL 0xf000c 1471 #define _FDI_RXB_CTL 0xf100c 1472 #define FDI_RX_CTL(pipe) (_FDI_RXA_CTL + (_FDI_RXB_CTL - _FDI_RXA_CTL) * (pipe - INTEL_PIPE_A)) 1473 #define _FDI_RXA_MISC 0xf0010 1474 #define _FDI_RXB_MISC 0xf1010 1475 #define FDI_RX_MISC(pipe) (_FDI_RXA_MISC + (_FDI_RXB_MISC - _FDI_RXA_MISC) * (pipe - INTEL_PIPE_A)) 1476 #define _FDI_RXA_IIR 0xf0014 1477 #define _FDI_RXB_IIR 0xf1014 1478 #define FDI_RX_IIR(pipe) (_FDI_RXA_IIR + (_FDI_RXB_IIR - _FDI_RXA_IIR) * (pipe - INTEL_PIPE_A)) 1479 #define _FDI_RXA_IMR 0xf0018 1480 #define _FDI_RXB_IMR 0xf1018 1481 #define FDI_RX_IMR(pipe) (_FDI_RXA_IMR + (_FDI_RXB_IMR - _FDI_RXA_IMR) * (pipe - INTEL_PIPE_A)) 1482 1483 #define FDI_RX_ENABLE (1 << 31) 1484 #define FDI_RX_PLL_ENABLED (1 << 13) 1485 1486 #define FDI_RX_LINK_COLOR_SHIFT 16 1487 #define FDI_RX_LINK_BPC(x) ((x) << FDI_RX_LINK_COLOR_SHIFT) 1488 #define FDI_RX_LINK_BPC_MASK (7 << FDI_RX_LINK_COLOR_SHIFT) 1489 1490 // Transcoder - same base as FDI_RX 1491 #define PCH_TRANS_CONF_A 0x0008 1492 #define PCH_TRANS_CONF_B 0x1008 1493 #define PCH_TRANS_CONF_C 0x2008 1494 1495 // Transcoder - skylake DDI 1496 #define DDI_SKL_TRANS_CONF_A (0x0008 | REGS_NORTH_PLANE_CONTROL) 1497 #define DDI_SKL_TRANS_CONF_B (0x1008 | REGS_NORTH_PLANE_CONTROL) 1498 #define DDI_SKL_TRANS_CONF_C (0x2008 | REGS_NORTH_PLANE_CONTROL) 1499 #define DDI_SKL_TRANS_CONF_EDP (0xf008 | REGS_NORTH_PLANE_CONTROL) 1500 1501 #define TRANS_ENABLE (1 << 31) 1502 #define TRANS_ENABLED (1 << 30) 1503 1504 // FDI_tX interrupt register 1505 #define FDI_RX_INTER_LANE_ALIGN (1 << 10) 1506 #define FDI_RX_SYMBOL_LOCK (1 << 9) 1507 #define FDI_RX_BIT_LOCK (1 << 8) 1508 #define FDI_RX_TRAIN_PATTERN_2_FAIL (1 << 7) 1509 #define FDI_RX_FS_CODE_ERR (1 << 6) 1510 #define FDI_RX_FE_CODE_ERR (1 << 5) 1511 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1 << 4) 1512 #define FDI_RX_HDCP_LINK_FAIL (1 << 3) 1513 #define FDI_RX_PIXEL_FIFO_OVERFLOW (1 << 2) 1514 #define FDI_RX_CROSS_CLOCK_OVERFLOW (1 << 1) 1515 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1 << 0) 1516 1517 #define FDI_FS_ERRC_ENABLE (1 << 27) 1518 #define FDI_FE_ERRC_ENABLE (1 << 26) 1519 1520 #define _FDI_RXA_TUSIZE1 0xf0030 1521 #define _FDI_RXA_TUSIZE2 0xf0038 1522 #define _FDI_RXB_TUSIZE1 0xf1030 1523 #define _FDI_RXB_TUSIZE2 0xf1038 1524 #define FDI_RX_TUSIZE1(pipe) (_FDI_RXA_TUSIZE1 + (_FDI_RXB_TUSIZE1 - _FDI_RXA_TUSIZE1) * (pipe - INTEL_PIPE_A)) 1525 #define FDI_RX_TUSIZE2(pipe) (_FDI_RXA_TUSIZE2 + (_FDI_RXB_TUSIZE2 - _FDI_RXA_TUSIZE2) * (pipe - INTEL_PIPE_A)) 1526 #define FDI_RX_TRANS_UNIT_SIZE(x) ((x - 1) << 25) 1527 #define FDI_RX_TRANS_UNIT_MASK 0x7e000000 1528 1529 #define FDI_RX_ENHANCE_FRAME_ENABLE (1 << 6) 1530 #define FDI_RX_CLOCK_MASK (1 << 4) 1531 #define FDI_RX_CLOCK_RAW (0 << 4) 1532 #define FDI_RX_CLOCK_PCD (1 << 4) 1533 1534 // FDI RX MISC 1535 #define FDI_RX_PWRDN_LANE1_MASK (3 << 26) 1536 #define FDI_RX_PWRDN_LANE1_VAL(x) ((x) << 26) 1537 #define FDI_RX_PWRDN_LANE0_MASK (3 << 24) 1538 #define FDI_RX_PWRDN_LANE0_VAL(x) ((x) << 24) 1539 #define FDI_RX_TP1_TO_TP2_48 (2 << 20) 1540 #define FDI_RX_TP1_TO_TP2_64 (3 << 20) 1541 #define FDI_RX_FDI_DELAY_90 (0x90 << 0) 1542 1543 #define _FDI_TXA_CTL (0x0100 | REGS_NORTH_PIPE_AND_PORT) 1544 #define _FDI_TXB_CTL (0x1100 | REGS_NORTH_PIPE_AND_PORT) 1545 #define FDI_TX_CTL(pipe) (_FDI_TXA_CTL + (_FDI_TXB_CTL - _FDI_TXA_CTL) * (pipe - INTEL_PIPE_A)) 1546 #define FDI_TX_ENABLE (1 << 31) 1547 #define FDI_LINK_TRAIN_PATTERN_1 (0 << 28) 1548 #define FDI_LINK_TRAIN_PATTERN_2 (1 << 28) 1549 #define FDI_LINK_TRAIN_PATTERN_IDLE (2 << 28) 1550 #define FDI_LINK_TRAIN_NONE (3 << 28) 1551 #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0 << 25) 1552 #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1 << 25) 1553 #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2 << 25) 1554 #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3 << 25) 1555 #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0 << 22) 1556 #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1 << 22) 1557 #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2 << 22) 1558 #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3 << 22) 1559 1560 // FDI/PIPE M/N DATA AND LINK VALUES (refreshrate) 1561 #define PCH_FDI_PIPE_A_DATA_M1 (0x0030 | REGS_NORTH_PIPE_AND_PORT) 1562 #define PCH_FDI_PIPE_A_DATA_M2 (0x0038 | REGS_NORTH_PIPE_AND_PORT) 1563 #define PCH_FDI_PIPE_B_DATA_M1 (0x1030 | REGS_NORTH_PIPE_AND_PORT) 1564 #define PCH_FDI_PIPE_B_DATA_M2 (0x1038 | REGS_NORTH_PIPE_AND_PORT) 1565 #define PCH_FDI_PIPE_C_DATA_M1 (0x2030 | REGS_NORTH_PIPE_AND_PORT) 1566 #define PCH_FDI_PIPE_C_DATA_M2 (0x2038 | REGS_NORTH_PIPE_AND_PORT) 1567 #define PCH_FDI_PIPE_A_DATA_N1 (0x0034 | REGS_NORTH_PIPE_AND_PORT) 1568 #define PCH_FDI_PIPE_A_DATA_N2 (0x003c | REGS_NORTH_PIPE_AND_PORT) 1569 #define PCH_FDI_PIPE_B_DATA_N1 (0x1034 | REGS_NORTH_PIPE_AND_PORT) 1570 #define PCH_FDI_PIPE_B_DATA_N2 (0x103c | REGS_NORTH_PIPE_AND_PORT) 1571 #define PCH_FDI_PIPE_C_DATA_N1 (0x2034 | REGS_NORTH_PIPE_AND_PORT) 1572 #define PCH_FDI_PIPE_C_DATA_N2 (0x203c | REGS_NORTH_PIPE_AND_PORT) 1573 #define PCH_FDI_PIPE_A_LINK_M1 (0x0040 | REGS_NORTH_PIPE_AND_PORT) 1574 #define PCH_FDI_PIPE_A_LINK_M2 (0x0048 | REGS_NORTH_PIPE_AND_PORT) 1575 #define PCH_FDI_PIPE_B_LINK_M1 (0x1040 | REGS_NORTH_PIPE_AND_PORT) 1576 #define PCH_FDI_PIPE_B_LINK_M2 (0x1048 | REGS_NORTH_PIPE_AND_PORT) 1577 #define PCH_FDI_PIPE_C_LINK_M1 (0x2040 | REGS_NORTH_PIPE_AND_PORT) 1578 #define PCH_FDI_PIPE_C_LINK_M2 (0x2048 | REGS_NORTH_PIPE_AND_PORT) 1579 #define PCH_FDI_PIPE_A_LINK_N1 (0x0044 | REGS_NORTH_PIPE_AND_PORT) 1580 #define PCH_FDI_PIPE_A_LINK_N2 (0x004c | REGS_NORTH_PIPE_AND_PORT) 1581 #define PCH_FDI_PIPE_B_LINK_N1 (0x1044 | REGS_NORTH_PIPE_AND_PORT) 1582 #define PCH_FDI_PIPE_B_LINK_N2 (0x104c | REGS_NORTH_PIPE_AND_PORT) 1583 #define PCH_FDI_PIPE_C_LINK_N1 (0x2044 | REGS_NORTH_PIPE_AND_PORT) 1584 #define PCH_FDI_PIPE_C_LINK_N2 (0x204c | REGS_NORTH_PIPE_AND_PORT) 1585 #define FDI_PIPE_MN_TU_SIZE_MASK (0x3f << 25) 1586 #define FDI_PIPE_MN_VALUE_MASK (0xffffff << 0) 1587 1588 // SNB A stepping 1589 #define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22) 1590 #define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22) 1591 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22) 1592 #define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x00 << 22) 1593 1594 // SNB B stepping 1595 #define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x00 << 22) 1596 #define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a << 22) 1597 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39 << 22) 1598 #define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38 << 22) 1599 #define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f << 22) 1600 #define FDI_TX_ENHANCE_FRAME_ENABLE (1 << 18) 1601 #define FDI_TX_PLL_ENABLED (1 << 14) 1602 1603 #define FDI_DP_PORT_WIDTH_SHIFT 19 1604 #define FDI_DP_PORT_WIDTH_MASK (7 << FDI_DP_PORT_WIDTH_SHIFT) 1605 #define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT) 1606 1607 #define FDI_PLL_BIOS_0 0x46000 1608 #define FDI_PLL_FB_CLOCK_MASK 0xff 1609 #define FDI_PLL_BIOS_1 0x46004 1610 #define FDI_PLL_BIOS_2 0x46008 1611 1612 #define FDI_AUTO_TRAINING (1 << 10) 1613 #define FDI_AUTO_TRAIN_DONE (1 << 1) 1614 1615 #define FDI_LINK_TRAIN_PATTERN_1_CPT (0 << 8) 1616 #define FDI_LINK_TRAIN_PATTERN_2_CPT (1 << 8) 1617 #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2 << 8) 1618 #define FDI_LINK_TRAIN_NORMAL_CPT (3 << 8) 1619 #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3 << 8) 1620 1621 // IvyBridge changes it up because... they hate developers? 1622 #define FDI_LINK_TRAIN_PATTERN_1_IVB (0 << 8) 1623 #define FDI_LINK_TRAIN_PATTERN_2_IVB (1 << 8) 1624 #define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2 << 8) 1625 #define FDI_LINK_TRAIN_NONE_IVB (3 << 8) 1626 1627 #define PCH_FDI_RXA_CHICKEN (0x200c | REGS_SOUTH_SHARED) 1628 #define PCH_FDI_RXB_CHICKEN (0x2010 | REGS_SOUTH_SHARED) 1629 #define FDI_RX_PHASE_SYNC_POINTER_EN (1 << 0) 1630 #define FDI_RX_PHASE_SYNC_POINTER_OVR (1 << 1) 1631 1632 #define SFUSE_STRAP (0x2014 | REGS_SOUTH_SHARED) 1633 #define SFUSE_STRAP_RAW_FREQUENCY (1 << 8) 1634 1635 // CPU Panel Fitters - These are for IronLake and up and are the CPU internal 1636 // panel fitters. 1637 #define PCH_PANEL_FITTER_BASE_REGISTER 0x68000 1638 #define PCH_PANEL_FITTER_PIPE_OFFSET 0x00800 1639 1640 #define PCH_PANEL_FITTER_WINDOW_POS 0x70 1641 #define PCH_PANEL_FITTER_WINDOW_SIZE 0x74 1642 #define PCH_PANEL_FITTER_CONTROL 0x80 1643 //not on IvyBridge: 1644 #define PCH_PANEL_FITTER_V_SCALE 0x84 1645 #define PCH_PANEL_FITTER_H_SCALE 0x90 1646 1647 #define PANEL_FITTER_ENABLED (1 << 31) 1648 //pipes are hardcoded according to offset on SkyLake and later 1649 #define PANEL_FITTER_PIPE_MASK (3 << 29) 1650 #define PANEL_FITTER_PIPE_A (0 << 29) 1651 #define PANEL_FITTER_PIPE_B (1 << 29) 1652 #define PANEL_FITTER_PIPE_C (2 << 29) 1653 #define PANEL_FITTER_SCALING_MODE_MASK (7 << 26) 1654 #define PANEL_FITTER_FILTER_MASK (3 << 24) 1655 1656 struct overlay_scale { 1657 uint32 _reserved0 : 3; 1658 uint32 horizontal_scale_fraction : 12; 1659 uint32 _reserved1 : 1; 1660 uint32 horizontal_downscale_factor : 3; 1661 uint32 _reserved2 : 1; 1662 uint32 vertical_scale_fraction : 12; 1663 }; 1664 1665 #define OVERLAY_FORMAT_RGB15 0x2 1666 #define OVERLAY_FORMAT_RGB16 0x3 1667 #define OVERLAY_FORMAT_RGB32 0x1 1668 #define OVERLAY_FORMAT_YCbCr422 0x8 1669 #define OVERLAY_FORMAT_YCbCr411 0x9 1670 #define OVERLAY_FORMAT_YCbCr420 0xc 1671 1672 #define OVERLAY_MIRROR_NORMAL 0x0 1673 #define OVERLAY_MIRROR_HORIZONTAL 0x1 1674 #define OVERLAY_MIRROR_VERTICAL 0x2 1675 1676 // The real overlay registers are written to using an update buffer 1677 1678 struct overlay_registers { 1679 uint32 buffer_rgb0; 1680 uint32 buffer_rgb1; 1681 uint32 buffer_u0; 1682 uint32 buffer_v0; 1683 uint32 buffer_u1; 1684 uint32 buffer_v1; 1685 // (0x18) OSTRIDE - overlay stride 1686 uint16 stride_rgb; 1687 uint16 stride_uv; 1688 // (0x1c) YRGB_VPH - Y/RGB vertical phase 1689 uint16 vertical_phase0_rgb; 1690 uint16 vertical_phase1_rgb; 1691 // (0x20) UV_VPH - UV vertical phase 1692 uint16 vertical_phase0_uv; 1693 uint16 vertical_phase1_uv; 1694 // (0x24) HORZ_PH - horizontal phase 1695 uint16 horizontal_phase_rgb; 1696 uint16 horizontal_phase_uv; 1697 // (0x28) INIT_PHS - initial phase shift 1698 uint32 initial_vertical_phase0_shift_rgb0 : 4; 1699 uint32 initial_vertical_phase1_shift_rgb0 : 4; 1700 uint32 initial_horizontal_phase_shift_rgb0 : 4; 1701 uint32 initial_vertical_phase0_shift_uv : 4; 1702 uint32 initial_vertical_phase1_shift_uv : 4; 1703 uint32 initial_horizontal_phase_shift_uv : 4; 1704 uint32 _reserved0 : 8; 1705 // (0x2c) DWINPOS - destination window position 1706 uint16 window_left; 1707 uint16 window_top; 1708 // (0x30) DWINSZ - destination window size 1709 uint16 window_width; 1710 uint16 window_height; 1711 // (0x34) SWIDTH - source width 1712 uint16 source_width_rgb; 1713 uint16 source_width_uv; 1714 // (0x38) SWITDHSW - source width in 8 byte steps 1715 uint16 source_bytes_per_row_rgb; 1716 uint16 source_bytes_per_row_uv; 1717 uint16 source_height_rgb; 1718 uint16 source_height_uv; 1719 overlay_scale scale_rgb; 1720 overlay_scale scale_uv; 1721 // (0x48) OCLRC0 - overlay color correction 0 1722 uint32 brightness_correction : 8; // signed, -128 to 127 1723 uint32 _reserved1 : 10; 1724 uint32 contrast_correction : 9; // fixed point: 3.6 bits 1725 uint32 _reserved2 : 5; 1726 // (0x4c) OCLRC1 - overlay color correction 1 1727 uint32 saturation_cos_correction : 10; // fixed point: 3.7 bits 1728 uint32 _reserved3 : 6; 1729 uint32 saturation_sin_correction : 11; // signed fixed point: 3.7 bits 1730 uint32 _reserved4 : 5; 1731 // (0x50) DCLRKV - destination color key value 1732 uint32 color_key_blue : 8; 1733 uint32 color_key_green : 8; 1734 uint32 color_key_red : 8; 1735 uint32 _reserved5 : 8; 1736 // (0x54) DCLRKM - destination color key mask 1737 uint32 color_key_mask_blue : 8; 1738 uint32 color_key_mask_green : 8; 1739 uint32 color_key_mask_red : 8; 1740 uint32 _reserved6 : 7; 1741 uint32 color_key_enabled : 1; 1742 // (0x58) SCHRKVH - source chroma key high value 1743 uint32 source_chroma_key_high_red : 8; 1744 uint32 source_chroma_key_high_blue : 8; 1745 uint32 source_chroma_key_high_green : 8; 1746 uint32 _reserved7 : 8; 1747 // (0x5c) SCHRKVL - source chroma key low value 1748 uint32 source_chroma_key_low_red : 8; 1749 uint32 source_chroma_key_low_blue : 8; 1750 uint32 source_chroma_key_low_green : 8; 1751 uint32 _reserved8 : 8; 1752 // (0x60) SCHRKEN - source chroma key enable 1753 uint32 _reserved9 : 24; 1754 uint32 source_chroma_key_red_enabled : 1; 1755 uint32 source_chroma_key_blue_enabled : 1; 1756 uint32 source_chroma_key_green_enabled : 1; 1757 uint32 _reserved10 : 5; 1758 // (0x64) OCONFIG - overlay configuration 1759 uint32 _reserved11 : 3; 1760 uint32 color_control_output_mode : 1; 1761 uint32 yuv_to_rgb_bypass : 1; 1762 uint32 _reserved12 : 11; 1763 uint32 gamma2_enabled : 1; 1764 uint32 _reserved13 : 1; 1765 uint32 select_pipe : 1; 1766 uint32 slot_time : 8; 1767 uint32 _reserved14 : 5; 1768 // (0x68) OCOMD - overlay command 1769 uint32 overlay_enabled : 1; 1770 uint32 active_field : 1; 1771 uint32 active_buffer : 2; 1772 uint32 test_mode : 1; 1773 uint32 buffer_field_mode : 1; 1774 uint32 _reserved15 : 1; 1775 uint32 tv_flip_field_enabled : 1; 1776 uint32 _reserved16 : 1; 1777 uint32 tv_flip_field_parity : 1; 1778 uint32 source_format : 4; 1779 uint32 ycbcr422_order : 2; 1780 uint32 _reserved18 : 1; 1781 uint32 mirroring_mode : 2; 1782 uint32 _reserved19 : 13; 1783 1784 uint32 _reserved20; 1785 1786 uint32 start_0y; 1787 uint32 start_1y; 1788 uint32 start_0u; 1789 uint32 start_0v; 1790 uint32 start_1u; 1791 uint32 start_1v; 1792 uint32 _reserved21[6]; 1793 #if 0 1794 // (0x70) AWINPOS - alpha blend window position 1795 uint32 awinpos; 1796 // (0x74) AWINSZ - alpha blend window size 1797 uint32 awinsz; 1798 1799 uint32 _reserved21[10]; 1800 #endif 1801 1802 // (0xa0) FASTHSCALE - fast horizontal downscale (strangely enough, 1803 // the next two registers switch the usual Y/RGB vs. UV order) 1804 uint16 horizontal_scale_uv; 1805 uint16 horizontal_scale_rgb; 1806 // (0xa4) UVSCALEV - vertical downscale 1807 uint16 vertical_scale_uv; 1808 uint16 vertical_scale_rgb; 1809 1810 uint32 _reserved22[86]; 1811 1812 // (0x200) polyphase filter coefficients 1813 uint16 vertical_coefficients_rgb[128]; 1814 uint16 horizontal_coefficients_rgb[128]; 1815 1816 uint32 _reserved23[64]; 1817 1818 // (0x500) 1819 uint16 vertical_coefficients_uv[128]; 1820 uint16 horizontal_coefficients_uv[128]; 1821 }; 1822 1823 // i965 overlay support is currently realized using its 3D hardware 1824 #define INTEL_i965_OVERLAY_STATE_SIZE 36864 1825 #define INTEL_i965_3D_CONTEXT_SIZE 32768 1826 1827 inline bool 1828 intel_uses_physical_overlay(intel_shared_info &info) 1829 { 1830 return !info.device_type.InGroup(INTEL_GROUP_Gxx); 1831 } 1832 1833 1834 struct hardware_status { 1835 uint32 interrupt_status_register; 1836 uint32 _reserved0[3]; 1837 void* primary_ring_head_storage; 1838 uint32 _reserved1[3]; 1839 void* secondary_ring_0_head_storage; 1840 void* secondary_ring_1_head_storage; 1841 uint32 _reserved2[2]; 1842 void* binning_head_storage; 1843 uint32 _reserved3[3]; 1844 uint32 store[1008]; 1845 }; 1846 1847 1848 #endif /* INTEL_EXTREME_H */ 1849