1 /* 2 * Copyright 2006-2016, Haiku, Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Axel Dörfler, axeld@pinc-software.de 7 * Alexander von Gluck, kallisti5@unixzen.com 8 */ 9 #ifndef INTEL_EXTREME_H 10 #define INTEL_EXTREME_H 11 12 13 #include "lock.h" 14 15 #include <Accelerant.h> 16 #include <Drivers.h> 17 #include <PCI.h> 18 19 #include <edid.h> 20 21 22 #define VENDOR_ID_INTEL 0x8086 23 24 #define INTEL_FAMILY_MASK 0x00ff0000 25 #define INTEL_GROUP_MASK 0x00fffff0 26 #define INTEL_MODEL_MASK 0x00ffffff 27 #define INTEL_TYPE_MASK 0x0000000f 28 29 // families 30 #define INTEL_FAMILY_8xx 0x00020000 // Second Gen 31 #define INTEL_FAMILY_9xx 0x00040000 // Third Gen + 32 #define INTEL_FAMILY_SER5 0x00080000 // Intel5 Series 33 #define INTEL_FAMILY_SOC0 0x00200000 // Atom SOC 34 #define INTEL_FAMILY_LAKE 0x00400000 // Intel Lakes 35 36 // groups 37 #define INTEL_GROUP_83x (INTEL_FAMILY_8xx | 0x0010) 38 #define INTEL_GROUP_85x (INTEL_FAMILY_8xx | 0x0020) 39 #define INTEL_GROUP_91x (INTEL_FAMILY_9xx | 0x0010) 40 #define INTEL_GROUP_94x (INTEL_FAMILY_9xx | 0x0020) 41 #define INTEL_GROUP_96x (INTEL_FAMILY_9xx | 0x0040) 42 #define INTEL_GROUP_Gxx (INTEL_FAMILY_9xx | 0x0080) 43 #define INTEL_GROUP_G4x (INTEL_FAMILY_9xx | 0x0100) 44 #define INTEL_GROUP_PIN (INTEL_FAMILY_9xx | 0x0200) // PineView 45 #define INTEL_GROUP_ILK (INTEL_FAMILY_SER5 | 0x0010) // IronLake 46 #define INTEL_GROUP_SNB (INTEL_FAMILY_SER5 | 0x0020) // SandyBridge 47 #define INTEL_GROUP_IVB (INTEL_FAMILY_SER5 | 0x0040) // IvyBridge 48 #define INTEL_GROUP_HAS (INTEL_FAMILY_SER5 | 0x0080) // Haswell 49 #define INTEL_GROUP_VLV (INTEL_FAMILY_SOC0 | 0x0010) // ValleyView 50 #define INTEL_GROUP_CHV (INTEL_FAMILY_SOC0 | 0x0020) // CherryView 51 #define INTEL_GROUP_BDW (INTEL_FAMILY_SOC0 | 0x0040) // Broadwell 52 #define INTEL_GROUP_SKY (INTEL_FAMILY_LAKE | 0x0010) // SkyLake 53 #define INTEL_GROUP_KBY (INTEL_FAMILY_LAKE | 0x0020) // KabyLake 54 #define INTEL_GROUP_CFL (INTEL_FAMILY_LAKE | 0x0040) // CoffeeLake 55 #define INTEL_GROUP_CML (INTEL_FAMILY_LAKE | 0x0080) // CometLake 56 #define INTEL_GROUP_JSL (INTEL_FAMILY_LAKE | 0x0100) // JasperLake 57 #define INTEL_GROUP_TGL (INTEL_FAMILY_LAKE | 0x0200) // TigerLake 58 // models 59 #define INTEL_TYPE_SERVER 0x0004 60 #define INTEL_TYPE_MOBILE 0x0008 61 #define INTEL_MODEL_915 (INTEL_GROUP_91x) 62 #define INTEL_MODEL_915M (INTEL_GROUP_91x | INTEL_TYPE_MOBILE) 63 #define INTEL_MODEL_945 (INTEL_GROUP_94x) 64 #define INTEL_MODEL_945M (INTEL_GROUP_94x | INTEL_TYPE_MOBILE) 65 #define INTEL_MODEL_965 (INTEL_GROUP_96x) 66 #define INTEL_MODEL_965M (INTEL_GROUP_96x | INTEL_TYPE_MOBILE) 67 #define INTEL_MODEL_G33 (INTEL_GROUP_Gxx) 68 #define INTEL_MODEL_G45 (INTEL_GROUP_G4x) 69 #define INTEL_MODEL_GM45 (INTEL_GROUP_G4x | INTEL_TYPE_MOBILE) 70 #define INTEL_MODEL_PINE (INTEL_GROUP_PIN) 71 #define INTEL_MODEL_PINEM (INTEL_GROUP_PIN | INTEL_TYPE_MOBILE) 72 #define INTEL_MODEL_ILKG (INTEL_GROUP_ILK) 73 #define INTEL_MODEL_ILKGM (INTEL_GROUP_ILK | INTEL_TYPE_MOBILE) 74 #define INTEL_MODEL_SNBG (INTEL_GROUP_SNB) 75 #define INTEL_MODEL_SNBGM (INTEL_GROUP_SNB | INTEL_TYPE_MOBILE) 76 #define INTEL_MODEL_SNBGS (INTEL_GROUP_SNB | INTEL_TYPE_SERVER) 77 #define INTEL_MODEL_IVBG (INTEL_GROUP_IVB) 78 #define INTEL_MODEL_IVBGM (INTEL_GROUP_IVB | INTEL_TYPE_MOBILE) 79 #define INTEL_MODEL_IVBGS (INTEL_GROUP_IVB | INTEL_TYPE_SERVER) 80 #define INTEL_MODEL_HAS (INTEL_GROUP_HAS) 81 #define INTEL_MODEL_HASM (INTEL_GROUP_HAS | INTEL_TYPE_MOBILE) 82 #define INTEL_MODEL_VLV (INTEL_GROUP_VLV) 83 #define INTEL_MODEL_VLVM (INTEL_GROUP_VLV | INTEL_TYPE_MOBILE) 84 #define INTEL_MODEL_BDW (INTEL_GROUP_BDW) 85 #define INTEL_MODEL_BDWM (INTEL_GROUP_BDW | INTEL_TYPE_MOBILE) 86 #define INTEL_MODEL_BDWS (INTEL_GROUP_BDW | INTEL_TYPE_SERVER) 87 #define INTEL_MODEL_SKY (INTEL_GROUP_SKY) 88 #define INTEL_MODEL_SKYM (INTEL_GROUP_SKY | INTEL_TYPE_MOBILE) 89 #define INTEL_MODEL_SKYS (INTEL_GROUP_SKY | INTEL_TYPE_SERVER) 90 #define INTEL_MODEL_KBY (INTEL_GROUP_KBY) 91 #define INTEL_MODEL_KBYM (INTEL_GROUP_KBY | INTEL_TYPE_MOBILE) 92 #define INTEL_MODEL_CFL (INTEL_GROUP_CFL) 93 #define INTEL_MODEL_CFLM (INTEL_GROUP_CFL | INTEL_TYPE_MOBILE) 94 #define INTEL_MODEL_CML (INTEL_GROUP_CML) 95 #define INTEL_MODEL_CMLM (INTEL_GROUP_CML | INTEL_TYPE_MOBILE) 96 #define INTEL_MODEL_JSL (INTEL_GROUP_JSL) 97 #define INTEL_MODEL_JSLM (INTEL_GROUP_JSL | INTEL_TYPE_MOBILE) 98 #define INTEL_MODEL_TGLM (INTEL_GROUP_TGL | INTEL_TYPE_MOBILE) 99 100 #define INTEL_PCH_DEVICE_ID_MASK 0xff80 101 #define INTEL_PCH_IBX_DEVICE_ID 0x3b00 102 #define INTEL_PCH_CPT_DEVICE_ID 0x1c00 103 #define INTEL_PCH_PPT_DEVICE_ID 0x1e00 104 #define INTEL_PCH_LPT_DEVICE_ID 0x8c00 105 #define INTEL_PCH_LPT_LP_DEVICE_ID 0x9c00 106 #define INTEL_PCH_WPT_DEVICE_ID 0x8c80 107 #define INTEL_PCH_WPT_LP_DEVICE_ID 0x9c80 108 #define INTEL_PCH_SPT_DEVICE_ID 0xa100 109 #define INTEL_PCH_SPT_LP_DEVICE_ID 0x9d00 110 #define INTEL_PCH_KBP_DEVICE_ID 0xa280 111 #define INTEL_PCH_CNP_DEVICE_ID 0xa300 112 #define INTEL_PCH_CNP_LP_DEVICE_ID 0x9d80 113 #define INTEL_PCH_CMP_DEVICE_ID 0x0280 114 #define INTEL_PCH_CMP2_DEVICE_ID 0x0680 115 #define INTEL_PCH_CMP_V_DEVICE_ID 0xa380 116 #define INTEL_PCH_ICP_DEVICE_ID 0x3480 117 #define INTEL_PCH_ICP2_DEVICE_ID 0x3880 118 #define INTEL_PCH_MCC_DEVICE_ID 0x4b00 119 #define INTEL_PCH_TGP_DEVICE_ID 0xa080 120 #define INTEL_PCH_TGP2_DEVICE_ID 0x4380 121 #define INTEL_PCH_JSP_DEVICE_ID 0x4d80 122 #define INTEL_PCH_ADP_DEVICE_ID 0x7a80 123 #define INTEL_PCH_ADP2_DEVICE_ID 0x5180 124 #define INTEL_PCH_ADP3_DEVICE_ID 0x7a00 125 #define INTEL_PCH_ADP4_DEVICE_ID 0x5480 126 #define INTEL_PCH_P2X_DEVICE_ID 0x7100 127 #define INTEL_PCH_P3X_DEVICE_ID 0x7000 128 129 // ValleyView MMIO offset 130 #define VLV_DISPLAY_BASE 0x180000 131 132 #define DEVICE_NAME "intel_extreme" 133 #define INTEL_ACCELERANT_NAME "intel_extreme.accelerant" 134 135 // We encode the register block into the value and extract/translate it when 136 // actually accessing. 137 #define REGISTER_BLOCK_COUNT 6 138 #define REGISTER_BLOCK_SHIFT 24 139 #define REGISTER_BLOCK_MASK 0xff000000 140 #define REGISTER_REGISTER_MASK 0x00ffffff 141 #define REGISTER_BLOCK(x) ((x & REGISTER_BLOCK_MASK) >> REGISTER_BLOCK_SHIFT) 142 #define REGISTER_REGISTER(x) (x & REGISTER_REGISTER_MASK) 143 144 #define REGS_FLAT (0 << REGISTER_BLOCK_SHIFT) 145 #define REGS_NORTH_SHARED (1 << REGISTER_BLOCK_SHIFT) 146 #define REGS_NORTH_PIPE_AND_PORT (2 << REGISTER_BLOCK_SHIFT) 147 #define REGS_NORTH_PLANE_CONTROL (3 << REGISTER_BLOCK_SHIFT) 148 #define REGS_SOUTH_SHARED (4 << REGISTER_BLOCK_SHIFT) 149 #define REGS_SOUTH_TRANSCODER_PORT (5 << REGISTER_BLOCK_SHIFT) 150 151 // register blocks for (G)MCH/ICH based platforms 152 #define MCH_SHARED_REGISTER_BASE 0x00000 153 #define MCH_PIPE_AND_PORT_REGISTER_BASE 0x60000 154 #define MCH_PLANE_CONTROL_REGISTER_BASE 0x70000 155 156 #define ICH_SHARED_REGISTER_BASE 0x00000 157 #define ICH_PORT_REGISTER_BASE 0x60000 158 159 // PCH - Platform Control Hub - Some hardware moves from a MCH/ICH based 160 // setup to a PCH based one, that means anything that used to communicate via 161 // (G)MCH registers needs to use different ones on PCH based platforms 162 // (Ironlake, SandyBridge, IvyBridge, Some Haswell). 163 #define PCH_NORTH_SHARED_REGISTER_BASE 0x40000 164 #define PCH_NORTH_PIPE_AND_PORT_REGISTER_BASE 0x60000 165 #define PCH_NORTH_PLANE_CONTROL_REGISTER_BASE 0x70000 166 #define PCH_SOUTH_SHARED_REGISTER_BASE 0xc0000 167 #define PCH_SOUTH_TRANSCODER_AND_PORT_REGISTER_BASE 0xe0000 168 169 170 struct DeviceType { 171 uint32 type; 172 173 DeviceType(int t) 174 { 175 type = t; 176 } 177 178 DeviceType& operator=(int t) 179 { 180 type = t; 181 return *this; 182 } 183 184 bool InFamily(uint32 family) const 185 { 186 return (type & INTEL_FAMILY_MASK) == family; 187 } 188 189 bool InGroup(uint32 group) const 190 { 191 return (type & INTEL_GROUP_MASK) == group; 192 } 193 194 bool IsModel(uint32 model) const 195 { 196 return (type & INTEL_MODEL_MASK) == model; 197 } 198 199 bool IsMobile() const 200 { 201 return (type & INTEL_TYPE_MASK) == INTEL_TYPE_MOBILE; 202 } 203 204 bool SupportsHDMI() const 205 { 206 return InGroup(INTEL_GROUP_G4x) || InFamily(INTEL_FAMILY_SER5) 207 || InFamily(INTEL_FAMILY_SOC0); 208 } 209 210 bool HasDDI() const 211 { 212 // Intel Digital Display Interface 213 return InGroup(INTEL_GROUP_HAS) || (Generation() >= 8); 214 } 215 216 int Generation() const 217 { 218 if (InFamily(INTEL_FAMILY_8xx)) 219 return 2; 220 if (InGroup(INTEL_GROUP_91x) || InGroup(INTEL_GROUP_94x) 221 || IsModel(INTEL_MODEL_G33) || InGroup(INTEL_GROUP_PIN)) 222 return 3; 223 if (InFamily(INTEL_FAMILY_9xx)) 224 return 4; 225 if (InGroup(INTEL_GROUP_ILK)) 226 return 5; 227 if (InGroup(INTEL_GROUP_SNB)) 228 return 6; 229 if (InFamily(INTEL_FAMILY_SER5) || InGroup(INTEL_GROUP_VLV)) 230 return 7; 231 if (InGroup(INTEL_GROUP_CHV) || InGroup(INTEL_GROUP_BDW)) 232 return 8; 233 if (InGroup(INTEL_GROUP_JSL)) 234 return 11; 235 if (InGroup(INTEL_GROUP_TGL)) 236 return 12; 237 if (InFamily(INTEL_FAMILY_LAKE)) 238 return 9; 239 240 // Generation 0 means something is wrong :-) 241 return 0; 242 } 243 }; 244 245 enum port_index { 246 INTEL_PORT_ANY, // wildcard for lookup functions 247 INTEL_PORT_A, 248 INTEL_PORT_B, 249 INTEL_PORT_C, 250 INTEL_PORT_D, 251 INTEL_PORT_E, 252 INTEL_PORT_F 253 }; 254 255 enum pch_info { 256 INTEL_PCH_NONE = 0, // No PCH present 257 INTEL_PCH_IBX, // Ibexpeak 258 INTEL_PCH_CPT, // Cougarpoint 259 INTEL_PCH_LPT, // Lynxpoint 260 INTEL_PCH_SPT, // SunrisePoint 261 INTEL_PCH_CNP, // CannonLake 262 INTEL_PCH_ICP, // IceLake 263 INTEL_PCH_JSP, // JasperLake 264 INTEL_PCH_MCC, // Mule Creek Canyon 265 INTEL_PCH_TGP, // TigerLake 266 INTEL_PCH_ADP, // AlderLake 267 INTEL_PCH_NOP 268 }; 269 270 // info about PLL on graphics card 271 struct pll_info { 272 uint32 reference_frequency; 273 uint32 max_frequency; 274 uint32 min_frequency; 275 uint32 divisor_register; 276 }; 277 278 struct ring_buffer { 279 struct lock lock; 280 uint32 register_base; 281 uint32 offset; 282 uint32 size; 283 uint32 position; 284 uint32 space_left; 285 uint8* base; 286 }; 287 288 struct overlay_registers; 289 290 struct intel_shared_info { 291 area_id mode_list_area; // area containing display mode list 292 uint32 mode_count; 293 294 display_mode current_mode; // pretty much a hack until per-display modes 295 display_timing panel_timing; // Hardware timings of the LVDS panel, extracted from BIOS 296 uint32 bytes_per_row; 297 uint32 bits_per_pixel; 298 uint32 dpms_mode; 299 uint16 min_brightness; 300 301 area_id registers_area; // area of memory mapped registers 302 uint32 register_blocks[REGISTER_BLOCK_COUNT]; 303 304 uint8* status_page; 305 phys_addr_t physical_status_page; 306 uint8* graphics_memory; 307 phys_addr_t physical_graphics_memory; 308 uint32 graphics_memory_size; 309 310 addr_t frame_buffer; 311 uint32 frame_buffer_offset; 312 313 uint32 fdi_link_frequency; // In Mhz 314 315 bool got_vbt; 316 bool single_head_locked; 317 318 struct lock accelerant_lock; 319 struct lock engine_lock; 320 321 ring_buffer primary_ring_buffer; 322 323 int32 overlay_channel_used; 324 bool overlay_active; 325 uintptr_t overlay_token; 326 phys_addr_t physical_overlay_registers; 327 uint32 overlay_offset; 328 329 bool hardware_cursor_enabled; 330 sem_id vblank_sem; 331 332 uint8* cursor_memory; 333 phys_addr_t physical_cursor_memory; 334 uint32 cursor_buffer_offset; 335 uint32 cursor_format; 336 bool cursor_visible; 337 uint16 cursor_hot_x; 338 uint16 cursor_hot_y; 339 340 DeviceType device_type; 341 char device_identifier[32]; 342 struct pll_info pll_info; 343 344 enum pch_info pch_info; 345 346 edid1_info vesa_edid_info; 347 bool has_vesa_edid_info; 348 }; 349 350 enum pipe_index { 351 INTEL_PIPE_ANY, 352 INTEL_PIPE_A, 353 INTEL_PIPE_B, 354 INTEL_PIPE_C, 355 INTEL_PIPE_D 356 }; 357 358 class pipes { 359 public: 360 pipes() : bitmask(0) {} 361 362 bool HasPipe(pipe_index pipe) 363 { 364 if (pipe == INTEL_PIPE_ANY) 365 return bitmask != 0; 366 367 return (bitmask & (1 << pipe)) != 0; 368 } 369 370 void SetPipe(pipe_index pipe) 371 { 372 if (pipe == INTEL_PIPE_ANY) { 373 bitmask = ~1; 374 // first bit corresponds to INTEL_PIPE_ANY but it's never used, 375 // so it should be 0 376 } 377 bitmask |= (1 << pipe); 378 } 379 380 void ClearPipe(pipe_index pipe) 381 { 382 if (pipe == INTEL_PIPE_ANY) 383 bitmask = 0; 384 385 bitmask &= ~(1 << pipe); 386 } 387 388 private: 389 uint8 bitmask; 390 }; 391 392 //----------------- ioctl() interface ---------------- 393 394 // magic code for ioctls 395 #define INTEL_PRIVATE_DATA_MAGIC 'itic' 396 397 // list ioctls 398 enum { 399 INTEL_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1, 400 401 INTEL_GET_DEVICE_NAME, 402 INTEL_ALLOCATE_GRAPHICS_MEMORY, 403 INTEL_FREE_GRAPHICS_MEMORY, 404 INTEL_GET_BRIGHTNESS_LEGACY, 405 INTEL_SET_BRIGHTNESS_LEGACY 406 }; 407 408 // retrieve the area_id of the kernel/accelerant shared info 409 struct intel_get_private_data { 410 uint32 magic; // magic number 411 area_id shared_info_area; 412 }; 413 414 // allocate graphics memory 415 struct intel_allocate_graphics_memory { 416 uint32 magic; 417 uint32 size; 418 uint32 alignment; 419 uint32 flags; 420 addr_t buffer_base; 421 }; 422 423 // free graphics memory 424 struct intel_free_graphics_memory { 425 uint32 magic; 426 addr_t buffer_base; 427 }; 428 429 // brightness legacy 430 struct intel_brightness_legacy { 431 uint32 magic; 432 uint8 lpc; 433 }; 434 435 //---------------------------------------------------------- 436 // Register definitions, taken from X driver 437 438 // PCI bridge memory management 439 #define INTEL_GRAPHICS_MEMORY_CONTROL 0x52 // i830+ 440 441 // GGC - (G)MCH Graphics Control Register 442 #define MEMORY_CONTROL_ENABLED 0x0004 443 #define MEMORY_MASK 0x0001 444 #define STOLEN_MEMORY_MASK 0x00f0 445 #define i965_GTT_MASK 0x000e 446 #define G33_GTT_MASK 0x0300 447 #define G4X_GTT_MASK 0x0f00 // GGMS (GSM Memory Size) mask 448 449 // models i830 and up 450 #define i830_LOCAL_MEMORY_ONLY 0x10 451 #define i830_STOLEN_512K 0x20 452 #define i830_STOLEN_1M 0x30 453 #define i830_STOLEN_8M 0x40 454 #define i830_FRAME_BUFFER_64M 0x01 455 #define i830_FRAME_BUFFER_128M 0x00 456 457 // models i855 and up 458 #define i855_STOLEN_MEMORY_1M 0x10 459 #define i855_STOLEN_MEMORY_4M 0x20 460 #define i855_STOLEN_MEMORY_8M 0x30 461 #define i855_STOLEN_MEMORY_16M 0x40 462 #define i855_STOLEN_MEMORY_32M 0x50 463 #define i855_STOLEN_MEMORY_48M 0x60 464 #define i855_STOLEN_MEMORY_64M 0x70 465 #define i855_STOLEN_MEMORY_128M 0x80 466 #define i855_STOLEN_MEMORY_256M 0x90 467 468 #define G4X_STOLEN_MEMORY_96MB 0xa0 // GMS - Graphics Mode Select 469 #define G4X_STOLEN_MEMORY_160MB 0xb0 470 #define G4X_STOLEN_MEMORY_224MB 0xc0 471 #define G4X_STOLEN_MEMORY_352MB 0xd0 472 473 // SandyBridge (SNB) 474 475 #define SNB_GRAPHICS_MEMORY_CONTROL 0x50 476 477 #define SNB_STOLEN_MEMORY_MASK 0xf8 478 #define SNB_STOLEN_MEMORY_32MB (1 << 3) 479 #define SNB_STOLEN_MEMORY_64MB (2 << 3) 480 #define SNB_STOLEN_MEMORY_96MB (3 << 3) 481 #define SNB_STOLEN_MEMORY_128MB (4 << 3) 482 #define SNB_STOLEN_MEMORY_160MB (5 << 3) 483 #define SNB_STOLEN_MEMORY_192MB (6 << 3) 484 #define SNB_STOLEN_MEMORY_224MB (7 << 3) 485 #define SNB_STOLEN_MEMORY_256MB (8 << 3) 486 #define SNB_STOLEN_MEMORY_288MB (9 << 3) 487 #define SNB_STOLEN_MEMORY_320MB (10 << 3) 488 #define SNB_STOLEN_MEMORY_352MB (11 << 3) 489 #define SNB_STOLEN_MEMORY_384MB (12 << 3) 490 #define SNB_STOLEN_MEMORY_416MB (13 << 3) 491 #define SNB_STOLEN_MEMORY_448MB (14 << 3) 492 #define SNB_STOLEN_MEMORY_480MB (15 << 3) 493 #define SNB_STOLEN_MEMORY_512MB (16 << 3) 494 495 #define SNB_GTT_SIZE_MASK (3 << 8) 496 #define SNB_GTT_SIZE_NONE (0 << 8) 497 #define SNB_GTT_SIZE_1MB (1 << 8) 498 #define SNB_GTT_SIZE_2MB (2 << 8) 499 500 // BDW+ (GGC_0_0_0_PCI) 501 502 #define BDW_GRAPHICS_MEMORY_CONTROL 0x50 503 504 #define BDW_STOLEN_MEMORY_MASK 0xff00 505 #define BDW_STOLEN_MEMORY_32MB (1 << 8) 506 #define BDW_STOLEN_MEMORY_64MB (2 << 8) 507 #define BDW_STOLEN_MEMORY_96MB (3 << 8) 508 #define BDW_STOLEN_MEMORY_128MB (4 << 8) 509 #define BDW_STOLEN_MEMORY_160MB (5 << 8) 510 #define BDW_STOLEN_MEMORY_192MB (6 << 8) 511 #define BDW_STOLEN_MEMORY_224MB (7 << 8) 512 #define BDW_STOLEN_MEMORY_256MB (8 << 8) 513 #define BDW_STOLEN_MEMORY_288MB (9 << 8) 514 #define BDW_STOLEN_MEMORY_320MB (10 << 8) 515 #define BDW_STOLEN_MEMORY_352MB (11 << 8) 516 #define BDW_STOLEN_MEMORY_384MB (12 << 8) 517 #define BDW_STOLEN_MEMORY_416MB (13 << 8) 518 #define BDW_STOLEN_MEMORY_448MB (14 << 8) 519 #define BDW_STOLEN_MEMORY_480MB (15 << 8) 520 #define BDW_STOLEN_MEMORY_512MB (16 << 8) 521 #define BDW_STOLEN_MEMORY_1024MB (32 << 8) 522 #define BDW_STOLEN_MEMORY_1536MB (48 << 8) 523 #define BDW_STOLEN_MEMORY_2016MB (63 << 8) 524 #define SKL_STOLEN_MEMORY_2048MB (64 << 8) 525 #define SKL_STOLEN_MEMORY_4MB (240 << 8) 526 #define SKL_STOLEN_MEMORY_8MB (241 << 8) 527 #define SKL_STOLEN_MEMORY_12MB (242 << 8) 528 #define SKL_STOLEN_MEMORY_16MB (243 << 8) 529 #define SKL_STOLEN_MEMORY_20MB (244 << 8) 530 #define SKL_STOLEN_MEMORY_24MB (245 << 8) 531 #define SKL_STOLEN_MEMORY_28MB (246 << 8) 532 #define SKL_STOLEN_MEMORY_32MB (247 << 8) 533 #define SKL_STOLEN_MEMORY_36MB (248 << 8) 534 #define SKL_STOLEN_MEMORY_40MB (249 << 8) 535 #define SKL_STOLEN_MEMORY_44MB (250 << 8) 536 #define SKL_STOLEN_MEMORY_48MB (251 << 8) 537 #define SKL_STOLEN_MEMORY_52MB (252 << 8) 538 #define SKL_STOLEN_MEMORY_56MB (253 << 8) 539 #define SKL_STOLEN_MEMORY_60MB (254 << 8) 540 541 542 #define BDW_GTT_SIZE_MASK (3 << 6) 543 #define BDW_GTT_SIZE_NONE (0 << 6) 544 #define BDW_GTT_SIZE_2MB (1 << 6) 545 #define BDW_GTT_SIZE_4MB (2 << 6) 546 #define BDW_GTT_SIZE_8MB (3 << 6) 547 548 // Gen2, i915GM, i945GM 549 #define LEGACY_BACKLIGHT_BRIGHTNESS 0xf4 550 551 // graphics page translation table 552 #define INTEL_PAGE_TABLE_CONTROL 0x02020 553 #define PAGE_TABLE_ENABLED 0x00000001 554 #define INTEL_PAGE_TABLE_ERROR 0x02024 555 #define INTEL_HARDWARE_STATUS_PAGE 0x02080 556 #define i915_GTT_BASE 0x1c 557 #define i830_GTT_BASE 0x10000 // (- 0x2ffff) 558 #define i830_GTT_SIZE 0x20000 559 #define i965_GTT_BASE 0x80000 // (- 0xfffff) 560 #define i965_GTT_SIZE 0x80000 561 #define i965_GTT_128K (2 << 1) 562 #define i965_GTT_256K (1 << 1) 563 #define i965_GTT_512K (0 << 1) 564 #define G33_GTT_1M (1 << 8) 565 #define G33_GTT_2M (2 << 8) 566 #define G4X_GTT_NONE 0x000 // GGMS - GSM Memory Size 567 #define G4X_GTT_1M_NO_IVT 0x100 // no Intel Virtualization Tech. 568 #define G4X_GTT_2M_NO_IVT 0x300 569 #define G4X_GTT_2M_IVT 0x900 // with Intel Virt. Tech. 570 #define G4X_GTT_3M_IVT 0xa00 571 #define G4X_GTT_4M_IVT 0xb00 572 573 574 #define GTT_ENTRY_VALID 0x01 575 #define GTT_ENTRY_LOCAL_MEMORY 0x02 576 #define GTT_PAGE_SHIFT 12 577 578 579 // ring buffer 580 #define INTEL_PRIMARY_RING_BUFFER 0x02030 581 #define INTEL_SECONDARY_RING_BUFFER_0 0x02100 582 #define INTEL_SECONDARY_RING_BUFFER_1 0x02110 583 // offsets for the ring buffer base registers above 584 #define RING_BUFFER_TAIL 0x0 585 #define RING_BUFFER_HEAD 0x4 586 #define RING_BUFFER_START 0x8 587 #define RING_BUFFER_CONTROL 0xc 588 #define INTEL_RING_BUFFER_SIZE_MASK 0x001ff000 589 #define INTEL_RING_BUFFER_HEAD_MASK 0x001ffffc 590 #define INTEL_RING_BUFFER_ENABLED 1 591 592 // interrupts 593 #define INTEL_INTERRUPT_ENABLED 0x020a0 594 #define INTEL_INTERRUPT_IDENTITY 0x020a4 595 #define INTEL_INTERRUPT_MASK 0x020a8 596 #define INTEL_INTERRUPT_STATUS 0x020ac 597 #define INTERRUPT_VBLANK_PIPEA (1 << 7) 598 #define INTERRUPT_VBLANK_PIPEB (1 << 5) 599 600 // PCH interrupts 601 #define PCH_INTERRUPT_STATUS 0x44000 602 #define PCH_INTERRUPT_MASK 0x44004 603 #define PCH_INTERRUPT_IDENTITY 0x44008 604 #define PCH_INTERRUPT_ENABLED 0x4400c 605 606 #define PCH_INTERRUPT_VBLANK_PIPEA (1 << 0) 607 #define PCH_INTERRUPT_VBLANK_PIPEB (1 << 5) 608 #define PCH_INTERRUPT_VBLANK_PIPEC (1 << 10) 609 610 // SandyBridge had only two pipes, and things were shuffled aroud again with 611 // the introduction of pipe C. 612 #define PCH_INTERRUPT_VBLANK_PIPEA_SNB (1 << 7) 613 #define PCH_INTERRUPT_VBLANK_PIPEB_SNB (1 << 15) 614 #define PCH_INTERRUPT_GLOBAL_SNB (1 << 31) 615 616 #define PCH_MASTER_INT_CTL_BDW 0x44200 617 618 #define PCH_MASTER_INT_CTL_PIPE_PENDING_BDW(pipe) (1 << (15 + pipe)) 619 #define GEN8_DE_PORT_IRQ (1 << 20) 620 #define PCH_MASTER_INT_CTL_GLOBAL_BDW (1 << 31) 621 622 #define PCH_INTERRUPT_PIPE_STATUS_BDW(pipe) (0x44400 + (pipe - 1) * 0x10) // GEN8_DE_PIPE_ISR 623 #define PCH_INTERRUPT_PIPE_MASK_BDW(pipe) (0x44404 + (pipe - 1) * 0x10) // GEN8_DE_PIPE_IMR 624 #define PCH_INTERRUPT_PIPE_IDENTITY_BDW(pipe) (0x44408 + (pipe - 1) * 0x10) // GEN8_DE_PIPE_IIR 625 #define PCH_INTERRUPT_PIPE_ENABLED_BDW(pipe) (0x4440c + (pipe - 1) * 0x10) // GEN8_DE_PIPE_IER 626 627 #define GEN8_DE_PORT_ISR 0x44440 628 #define GEN8_DE_PORT_IMR 0x44444 629 #define GEN8_DE_PORT_IIR 0x44448 630 #define GEN8_DE_PORT_IER 0x4444c 631 #define GEN8_AUX_CHANNEL_A (1 << 0) 632 #define GEN9_AUX_CHANNEL_B (1 << 25) 633 #define GEN9_AUX_CHANNEL_C (1 << 26) 634 #define GEN9_AUX_CHANNEL_D (1 << 27) 635 #define CNL_AUX_CHANNEL_F (1 << 28) 636 #define ICL_AUX_CHANNEL_E (1 << 29) 637 638 #define GEN8_DE_MISC_ISR 0x44460 639 #define GEN8_DE_MISC_IMR 0x44464 640 #define GEN8_DE_MISC_IIR 0x44468 641 #define GEN8_DE_MISC_IER 0x4446c 642 #define GEN8_DE_EDP_PSR (1 << 19) 643 644 #define PCH_INTERRUPT_VBLANK_BDW (1 << 0) // GEN8_PIPE_VBLANK 645 #define GEN8_PIPE_VSYNC (1 << 1) 646 #define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2) 647 648 #define GEN11_DISPLAY_INT_CTL 0x44200 // same as PCH_MASTER_INT_CTL_BDW 649 #define GEN11_GFX_MSTR_IRQ 0x190010 650 #define GEN11_MASTER_IRQ (1 << 31) 651 #define GEN11_DISPLAY_IRQ (1 << 16) 652 #define GEN11_GT_DW1_IRQ (1 << 1) 653 #define GEN11_GT_DW0_IRQ (1 << 0) 654 655 #define GEN11_GT_INTR_DW0 0x190018 656 #define GEN11_GT_INTR_DW1 0x19001c 657 658 #define GEN11_GU_MISC_IMR 0x444f4 659 #define GEN11_GU_MISC_IIR 0x444f8 660 #define GEN11_GU_MISC_IER 0x444fc 661 #define GEN11_GU_MISC_GSE (1 << 27) 662 663 664 // graphics port control (i.e. G45) 665 #define DISPLAY_MONITOR_PORT_ENABLED (1UL << 31) 666 #define DISPLAY_MONITOR_PIPE_B (1UL << 30) 667 #define DISPLAY_MONITOR_VGA_POLARITY (1UL << 15) 668 #define DISPLAY_MONITOR_MODE_MASK (3UL << 10) 669 #define DISPLAY_MONITOR_ON 0 670 #define DISPLAY_MONITOR_SUSPEND (1UL << 10) 671 #define DISPLAY_MONITOR_STAND_BY (2UL << 10) 672 #define DISPLAY_MONITOR_OFF (3UL << 10) 673 #define DISPLAY_MONITOR_POLARITY_MASK (3UL << 3) 674 #define DISPLAY_MONITOR_POSITIVE_HSYNC (1UL << 3) 675 #define DISPLAY_MONITOR_POSITIVE_VSYNC (2UL << 3) 676 #define DISPLAY_MONITOR_PORT_DETECTED (1UL << 2) // TMDS/DisplayPort only 677 678 // Cougar Point transcoder pipe selection 679 // (replaces DISPLAY_MONITOR_PIPE_B) 680 #define PORT_TRANS_A_SEL_CPT 0 681 #define PORT_TRANS_B_SEL_CPT (1<<29) 682 #define PORT_TRANS_C_SEL_CPT (2<<29) 683 #define PORT_TRANS_SEL_MASK (3<<29) 684 685 #define LVDS_POST2_RATE_SLOW 14 // PLL Divisors 686 #define LVDS_POST2_RATE_FAST 7 687 #define LVDS_B0B3_POWER_MASK (3UL << 2) 688 #define LVDS_B0B3_POWER_UP (3UL << 2) 689 #define LVDS_CLKB_POWER_MASK (3UL << 4) 690 #define LVDS_CLKB_POWER_UP (3UL << 4) 691 #define LVDS_A3_POWER_MASK (3UL << 6) 692 #define LVDS_A3_POWER_UP (3UL << 6) 693 #define LVDS_A0A2_CLKA_POWER_UP (3UL << 8) 694 #define LVDS_BORDER_ENABLE (1UL << 15) 695 #define LVDS_HSYNC_POLARITY (1UL << 20) 696 #define LVDS_VSYNC_POLARITY (1UL << 21) 697 #define LVDS_18BIT_DITHER (1UL << 25) 698 #define LVDS_PORT_EN (1UL << 31) 699 700 // PLL flags (pre-DDI) 701 #define DISPLAY_PLL_ENABLED (1UL << 31) 702 #define DISPLAY_PLL_2X_CLOCK (1UL << 30) 703 #define DISPLAY_PLL_SYNC_LOCK_ENABLED (1UL << 29) 704 #define DISPLAY_PLL_NO_VGA_CONTROL (1UL << 28) 705 #define DISPLAY_PLL_MODE_NORMAL (1UL << 26) 706 #define DISPLAY_PLL_MODE_LVDS (2UL << 26) 707 #define DISPLAY_PLL_DIVIDE_HIGH (1UL << 24) 708 #define DISPLAY_PLL_DIVIDE_4X (1UL << 23) 709 #define DISPLAY_PLL_POST1_DIVIDE_2 (1UL << 21) 710 #define DISPLAY_PLL_POST1_DIVISOR_MASK 0x001f0000 711 #define DISPLAY_PLL_9xx_POST1_DIVISOR_MASK 0x00ff0000 712 #define DISPLAY_PLL_SNB_FP0_POST1_DIVISOR_MASK 0x000000ff 713 #define DISPLAY_PLL_IGD_POST1_DIVISOR_MASK 0x00ff8000 714 #define DISPLAY_PLL_POST1_DIVISOR_SHIFT 16 715 #define DISPLAY_PLL_SNB_FP0_POST1_DIVISOR_SHIFT 0 716 #define DISPLAY_PLL_IGD_POST1_DIVISOR_SHIFT 15 717 #define DISPLAY_PLL_DIVISOR_1 (1UL << 8) 718 #define DISPLAY_PLL_N_DIVISOR_MASK 0x001f0000 719 #define DISPLAY_PLL_IGD_N_DIVISOR_MASK 0x00ff0000 720 #define DISPLAY_PLL_M1_DIVISOR_MASK 0x00001f00 721 #define DISPLAY_PLL_M2_DIVISOR_MASK 0x0000001f 722 #define DISPLAY_PLL_IGD_M2_DIVISOR_MASK 0x000000ff 723 #define DISPLAY_PLL_N_DIVISOR_SHIFT 16 724 #define DISPLAY_PLL_M1_DIVISOR_SHIFT 8 725 #define DISPLAY_PLL_M2_DIVISOR_SHIFT 0 726 #define DISPLAY_PLL_PULSE_PHASE_SHIFT 9 727 728 // Skylake PLLs 729 #define SKL_DPLL1_CFGCR1 (0xc040 | REGS_NORTH_PIPE_AND_PORT) 730 #define SKL_DPLL1_CFGCR2 (0xc044 | REGS_NORTH_PIPE_AND_PORT) 731 #define SKL_DPLL2_CFGCR1 (0xc048 | REGS_NORTH_PIPE_AND_PORT) 732 #define SKL_DPLL2_CFGCR2 (0xc04c | REGS_NORTH_PIPE_AND_PORT) 733 #define SKL_DPLL3_CFGCR1 (0xc050 | REGS_NORTH_PIPE_AND_PORT) 734 #define SKL_DPLL3_CFGCR2 (0xc054 | REGS_NORTH_PIPE_AND_PORT) 735 // These exist also still in CoffeeLake (confirmed): 736 #define SKL_DPLL_CTRL1 (0xc058 | REGS_NORTH_PIPE_AND_PORT) 737 #define SKL_DPLL_CTRL2 (0xc05c | REGS_NORTH_PIPE_AND_PORT) 738 #define SKL_DPLL_STATUS (0xc060 | REGS_NORTH_PIPE_AND_PORT) 739 #define SKL_DPLL0_DP_LINKRATE_SHIFT 1 740 #define SKL_DPLL1_DP_LINKRATE_SHIFT 7 741 #define SKL_DPLL2_DP_LINKRATE_SHIFT 13 742 #define SKL_DPLL3_DP_LINKRATE_SHIFT 19 743 #define SKL_DPLL_DP_LINKRATE_MASK 7 744 #define SKL_DPLL_CTRL1_2700 0 745 #define SKL_DPLL_CTRL1_1350 1 746 #define SKL_DPLL_CTRL1_810 2 747 #define SKL_DPLL_CTRL1_1620 3 748 #define SKL_DPLL_CTRL1_1080 4 749 #define SKL_DPLL_CTRL1_2160 5 750 751 // Icelake PLLs 752 #define ICL_DSSM 0x51004 753 #define ICL_DSSM_REF_FREQ_SHIFT 29 754 #define ICL_DSSM_REF_FREQ_MASK (7 << ICL_DSSM_REF_FREQ_SHIFT) 755 #define ICL_DSSM_24000 0 756 #define ICL_DSSM_19200 1 757 #define ICL_DSSM_38400 2 758 759 // display 760 761 #define INTEL_DISPLAY_OFFSET 0x1000 762 763 // Note: on Skylake below registers are part of the transcoder 764 #define INTEL_DISPLAY_A_HTOTAL (0x0000 | REGS_NORTH_PIPE_AND_PORT) 765 #define INTEL_DISPLAY_A_HBLANK (0x0004 | REGS_NORTH_PIPE_AND_PORT) 766 #define INTEL_DISPLAY_A_HSYNC (0x0008 | REGS_NORTH_PIPE_AND_PORT) 767 #define INTEL_DISPLAY_A_VTOTAL (0x000c | REGS_NORTH_PIPE_AND_PORT) 768 #define INTEL_DISPLAY_A_VBLANK (0x0010 | REGS_NORTH_PIPE_AND_PORT) 769 #define INTEL_DISPLAY_A_VSYNC (0x0014 | REGS_NORTH_PIPE_AND_PORT) 770 #define INTEL_DISPLAY_B_HTOTAL (0x1000 | REGS_NORTH_PIPE_AND_PORT) 771 #define INTEL_DISPLAY_B_HBLANK (0x1004 | REGS_NORTH_PIPE_AND_PORT) 772 #define INTEL_DISPLAY_B_HSYNC (0x1008 | REGS_NORTH_PIPE_AND_PORT) 773 #define INTEL_DISPLAY_B_VTOTAL (0x100c | REGS_NORTH_PIPE_AND_PORT) 774 #define INTEL_DISPLAY_B_VBLANK (0x1010 | REGS_NORTH_PIPE_AND_PORT) 775 #define INTEL_DISPLAY_B_VSYNC (0x1014 | REGS_NORTH_PIPE_AND_PORT) 776 777 #define INTEL_DISPLAY_A_PIPE_SIZE (0x001c | REGS_NORTH_PIPE_AND_PORT) 778 #define INTEL_DISPLAY_B_PIPE_SIZE (0x101c | REGS_NORTH_PIPE_AND_PORT) 779 780 //G45 displayport link 781 #define INTEL_PIPE_A_DATA_M (0x0050 | REGS_NORTH_PLANE_CONTROL) 782 #define INTEL_PIPE_B_DATA_M (0x1050 | REGS_NORTH_PLANE_CONTROL) 783 #define INTEL_PIPE_A_DATA_N (0x0054 | REGS_NORTH_PLANE_CONTROL) 784 #define INTEL_PIPE_B_DATA_N (0x1054 | REGS_NORTH_PLANE_CONTROL) 785 #define INTEL_PIPE_A_LINK_M (0x0060 | REGS_NORTH_PLANE_CONTROL) 786 #define INTEL_PIPE_B_LINK_M (0x1060 | REGS_NORTH_PLANE_CONTROL) 787 #define INTEL_PIPE_A_LINK_N (0x0064 | REGS_NORTH_PLANE_CONTROL) 788 #define INTEL_PIPE_B_LINK_N (0x1064 | REGS_NORTH_PLANE_CONTROL) 789 790 //DDI port link 791 #define INTEL_DDI_PIPE_A_DATA_M (0x0030 | REGS_NORTH_PIPE_AND_PORT) 792 #define INTEL_DDI_PIPE_B_DATA_M (0x1030 | REGS_NORTH_PIPE_AND_PORT) 793 #define INTEL_DDI_PIPE_A_DATA_N (0x0034 | REGS_NORTH_PIPE_AND_PORT) 794 #define INTEL_DDI_PIPE_B_DATA_N (0x1034 | REGS_NORTH_PIPE_AND_PORT) 795 #define INTEL_DDI_PIPE_A_LINK_M (0x0040 | REGS_NORTH_PIPE_AND_PORT) 796 #define INTEL_DDI_PIPE_B_LINK_M (0x1040 | REGS_NORTH_PIPE_AND_PORT) 797 #define INTEL_DDI_PIPE_A_LINK_N (0x0044 | REGS_NORTH_PIPE_AND_PORT) 798 #define INTEL_DDI_PIPE_B_LINK_N (0x1044 | REGS_NORTH_PIPE_AND_PORT) 799 800 // on PCH we also have to set the transcoder 801 #define INTEL_TRANSCODER_A_HTOTAL (0x0000 | REGS_SOUTH_TRANSCODER_PORT) 802 #define INTEL_TRANSCODER_A_HBLANK (0x0004 | REGS_SOUTH_TRANSCODER_PORT) 803 #define INTEL_TRANSCODER_A_HSYNC (0x0008 | REGS_SOUTH_TRANSCODER_PORT) 804 #define INTEL_TRANSCODER_A_VTOTAL (0x000c | REGS_SOUTH_TRANSCODER_PORT) 805 #define INTEL_TRANSCODER_A_VBLANK (0x0010 | REGS_SOUTH_TRANSCODER_PORT) 806 #define INTEL_TRANSCODER_A_VSYNC (0x0014 | REGS_SOUTH_TRANSCODER_PORT) 807 #define INTEL_TRANSCODER_B_HTOTAL (0x1000 | REGS_SOUTH_TRANSCODER_PORT) 808 #define INTEL_TRANSCODER_B_HBLANK (0x1004 | REGS_SOUTH_TRANSCODER_PORT) 809 #define INTEL_TRANSCODER_B_HSYNC (0x1008 | REGS_SOUTH_TRANSCODER_PORT) 810 #define INTEL_TRANSCODER_B_VTOTAL (0x100c | REGS_SOUTH_TRANSCODER_PORT) 811 #define INTEL_TRANSCODER_B_VBLANK (0x1010 | REGS_SOUTH_TRANSCODER_PORT) 812 #define INTEL_TRANSCODER_B_VSYNC (0x1014 | REGS_SOUTH_TRANSCODER_PORT) 813 814 // transcoder M/N DATA AND LINK VALUES (refreshrate) 815 #define INTEL_TRANSCODER_A_DATA_M1 (0x0030 | REGS_SOUTH_TRANSCODER_PORT) 816 #define INTEL_TRANSCODER_A_DATA_M2 (0x0038 | REGS_SOUTH_TRANSCODER_PORT) 817 #define INTEL_TRANSCODER_B_DATA_M1 (0x1030 | REGS_SOUTH_TRANSCODER_PORT) 818 #define INTEL_TRANSCODER_B_DATA_M2 (0x1038 | REGS_SOUTH_TRANSCODER_PORT) 819 #define INTEL_TRANSCODER_C_DATA_M1 (0x2030 | REGS_SOUTH_TRANSCODER_PORT) 820 #define INTEL_TRANSCODER_C_DATA_M2 (0x2038 | REGS_SOUTH_TRANSCODER_PORT) 821 #define INTEL_TRANSCODER_A_DATA_N1 (0x0034 | REGS_SOUTH_TRANSCODER_PORT) 822 #define INTEL_TRANSCODER_A_DATA_N2 (0x003c | REGS_SOUTH_TRANSCODER_PORT) 823 #define INTEL_TRANSCODER_B_DATA_N1 (0x1034 | REGS_SOUTH_TRANSCODER_PORT) 824 #define INTEL_TRANSCODER_B_DATA_N2 (0x103c | REGS_SOUTH_TRANSCODER_PORT) 825 #define INTEL_TRANSCODER_C_DATA_N1 (0x2034 | REGS_SOUTH_TRANSCODER_PORT) 826 #define INTEL_TRANSCODER_C_DATA_N2 (0x203c | REGS_SOUTH_TRANSCODER_PORT) 827 #define INTEL_TRANSCODER_A_LINK_M1 (0x0040 | REGS_SOUTH_TRANSCODER_PORT) 828 #define INTEL_TRANSCODER_A_LINK_M2 (0x0048 | REGS_SOUTH_TRANSCODER_PORT) 829 #define INTEL_TRANSCODER_B_LINK_M1 (0x1040 | REGS_SOUTH_TRANSCODER_PORT) 830 #define INTEL_TRANSCODER_B_LINK_M2 (0x1048 | REGS_SOUTH_TRANSCODER_PORT) 831 #define INTEL_TRANSCODER_C_LINK_M1 (0x2040 | REGS_SOUTH_TRANSCODER_PORT) 832 #define INTEL_TRANSCODER_C_LINK_M2 (0x2048 | REGS_SOUTH_TRANSCODER_PORT) 833 #define INTEL_TRANSCODER_A_LINK_N1 (0x0044 | REGS_SOUTH_TRANSCODER_PORT) 834 #define INTEL_TRANSCODER_A_LINK_N2 (0x004c | REGS_SOUTH_TRANSCODER_PORT) 835 #define INTEL_TRANSCODER_B_LINK_N1 (0x1044 | REGS_SOUTH_TRANSCODER_PORT) 836 #define INTEL_TRANSCODER_B_LINK_N2 (0x104c | REGS_SOUTH_TRANSCODER_PORT) 837 #define INTEL_TRANSCODER_C_LINK_N1 (0x2044 | REGS_SOUTH_TRANSCODER_PORT) 838 #define INTEL_TRANSCODER_C_LINK_N2 (0x204c | REGS_SOUTH_TRANSCODER_PORT) 839 #define INTEL_TRANSCODER_MN_TU_SIZE_MASK (0x3f << 25) 840 #define INTEL_TRANSCODER_MN_VALUE_MASK (0xffffff << 0) 841 842 #define INTEL_TRANSCODER_A_IMAGE_SIZE (0x001c | REGS_SOUTH_TRANSCODER_PORT) 843 #define INTEL_TRANSCODER_B_IMAGE_SIZE (0x101c | REGS_SOUTH_TRANSCODER_PORT) 844 845 // TODO: Is there consolidation that could happen here with digital ports? 846 847 #define INTEL_ANALOG_PORT (0x1100 | REGS_SOUTH_TRANSCODER_PORT) 848 #define INTEL_DIGITAL_PORT_A (0x1120 | REGS_SOUTH_TRANSCODER_PORT) 849 #define INTEL_DIGITAL_PORT_B (0x1140 | REGS_SOUTH_TRANSCODER_PORT) 850 #define INTEL_DIGITAL_PORT_C (0x1160 | REGS_SOUTH_TRANSCODER_PORT) 851 #define INTEL_DIGITAL_LVDS_PORT (0x1180 | REGS_SOUTH_TRANSCODER_PORT) 852 853 #define INTEL_HDMI_PORT_B (0x1140 | REGS_SOUTH_TRANSCODER_PORT) 854 #define INTEL_HDMI_PORT_C (0x1160 | REGS_SOUTH_TRANSCODER_PORT) 855 856 #define PCH_HDMI_PORT_B (0x1140 | REGS_SOUTH_TRANSCODER_PORT) 857 #define PCH_HDMI_PORT_C (0x1150 | REGS_SOUTH_TRANSCODER_PORT) 858 #define PCH_HDMI_PORT_D (0x1160 | REGS_SOUTH_TRANSCODER_PORT) 859 860 #define GEN4_HDMI_PORT_B (0x1140 | REGS_SOUTH_TRANSCODER_PORT) 861 #define GEN4_HDMI_PORT_C (0x1160 | REGS_SOUTH_TRANSCODER_PORT) 862 #define CHV_HDMI_PORT_D (0x116C | REGS_SOUTH_TRANSCODER_PORT) 863 864 // DDI Buffer Control (This replaces DP on Haswell+) 865 #define DDI_BUF_CTL_A (0x4000 | REGS_NORTH_PIPE_AND_PORT) 866 #define DDI_BUF_CTL_B (0x4100 | REGS_NORTH_PIPE_AND_PORT) 867 #define DDI_BUF_CTL_C (0x4200 | REGS_NORTH_PIPE_AND_PORT) 868 #define DDI_BUF_CTL_D (0x4300 | REGS_NORTH_PIPE_AND_PORT) 869 #define DDI_BUF_CTL_E (0x4400 | REGS_NORTH_PIPE_AND_PORT) 870 #define DDI_BUF_CTL_F (0x4500 | REGS_NORTH_PIPE_AND_PORT) 871 #define DDI_BUF_CTL_ENABLE (1 << 31) 872 #define DDI_BUF_TRANS_SELECT(n) ((n) << 24) 873 #define DDI_BUF_EMP_MASK (0xf << 24) 874 #define DDI_BUF_PORT_REVERSAL (1 << 16) 875 #define DDI_BUF_IS_IDLE (1 << 7) 876 #define DDI_A_4_LANES (1 << 4) 877 #define DDI_PORT_WIDTH(width) (((width) - 1) << 1) 878 #define DDI_INIT_DISPLAY_DETECTED (1 << 0) 879 880 #define PIPE_DDI_FUNC_CTL_A (0x0400 | REGS_NORTH_PIPE_AND_PORT) 881 #define PIPE_DDI_FUNC_CTL_B (0x1400 | REGS_NORTH_PIPE_AND_PORT) 882 #define PIPE_DDI_FUNC_CTL_C (0x2400 | REGS_NORTH_PIPE_AND_PORT) 883 #define PIPE_DDI_FUNC_CTL_EDP (0xF400 | REGS_NORTH_PIPE_AND_PORT) 884 #define PIPE_DDI_FUNC_CTL_ENABLE (1 << 31) 885 #define PIPE_DDI_SELECT_SHIFT 28 886 #define PIPE_DDI_SELECT_PORT(x) ((x) << PIPE_DDI_SELECT_SHIFT) 887 #define PIPE_DDI_SELECT_MASK (7 << PIPE_DDI_SELECT_SHIFT) 888 #define PIPE_DDI_PORT_NONE 0 889 #define PIPE_DDI_PORT_B 1 890 #define PIPE_DDI_PORT_C 2 891 #define PIPE_DDI_PORT_D 3 892 #define PIPE_DDI_PORT_E 4 893 #define PIPE_DDI_PORT_F 5 894 #define PIPE_DDI_MODESEL_SHIFT 24 895 #define PIPE_DDI_MODESEL_MODE(x) ((x) << PIPE_DDI_MODESEL_SHIFT) 896 #define PIPE_DDI_MODESEL_MASK (7 << PIPE_DDI_MODESEL_SHIFT) 897 #define PIPE_DDI_MODE_HDMI 0 898 #define PIPE_DDI_MODE_DVI 1 899 #define PIPE_DDI_MODE_DP_SST 2 900 #define PIPE_DDI_MODE_DP_MST 3 901 #define PIPE_DDI_COLOR_SHIFT 20 902 #define PIPE_DDI_BPC(x) ((x) << PIPE_DDI_COLOR_SHIFT) 903 #define PIPE_DDI_BPC_MASK (7 << PIPE_DDI_COLOR_SHIFT) 904 #define PIPE_DDI_8BPC 0 905 #define PIPE_DDI_10BPC 1 906 #define PIPE_DDI_6BPC 2 907 #define PIPE_DDI_12BPC 3 908 #define PIPE_DDI_DP_WIDTH_SHIFT 1 909 #define PIPE_DDI_DP_WIDTH_SEL(x) ((x) << PIPE_DDI_DP_WIDTH_SHIFT) 910 #define PIPE_DDI_DP_WIDTH_MASK (7 << PIPE_DDI_DP_WIDTH_SHIFT) 911 #define PIPE_DDI_DP_WIDTH_1 0 912 #define PIPE_DDI_DP_WIDTH_2 1 913 #define PIPE_DDI_DP_WIDTH_4 2 914 915 // DP_A always @ 6xxxx, DP_B-DP_D move with PCH 916 #define INTEL_DISPLAY_PORT_A (0x4000 | REGS_NORTH_PIPE_AND_PORT) 917 #define INTEL_DISPLAY_PORT_B (0x4100 | REGS_SOUTH_TRANSCODER_PORT) 918 #define INTEL_DISPLAY_PORT_C (0x4200 | REGS_SOUTH_TRANSCODER_PORT) 919 #define INTEL_DISPLAY_PORT_D (0x4300 | REGS_SOUTH_TRANSCODER_PORT) 920 921 #define INTEL_DISP_PORTA_SNB_PIPE_SHIFT 30 922 #define INTEL_DISP_PORTA_SNB_PIPE_MASK (1 << INTEL_DISP_PORTA_SNB_PIPE_SHIFT) 923 #define INTEL_DISP_PORTA_SNB_PIPE_A 0 924 #define INTEL_DISP_PORTA_SNB_PIPE_B 1 925 #define INTEL_DISP_PORTA_IVB_PIPE_SHIFT 29 926 #define INTEL_DISP_PORTA_IVB_PIPE_MASK (3 << INTEL_DISP_PORTA_IVB_PIPE_SHIFT) 927 #define INTEL_DISP_PORTA_IVB_PIPE_A 0 928 #define INTEL_DISP_PORTA_IVB_PIPE_B 1 929 #define INTEL_DISP_PORTA_IVB_PIPE_C 2 930 931 #define INTEL_DISP_PORT_WIDTH_SHIFT 19 932 #define INTEL_DISP_PORT_WIDTH_MASK (7 << INTEL_DISP_PORT_WIDTH_SHIFT) 933 #define INTEL_DISP_PORT_WIDTH_1 0 934 #define INTEL_DISP_PORT_WIDTH_2 1 935 #define INTEL_DISP_PORT_WIDTH_4 3 936 #define INTEL_DISP_EDP_PLL_FREQ_SHIFT 16 937 #define INTEL_DISP_EDP_PLL_FREQ_MASK (3 << INTEL_DISP_EDP_PLL_FREQ_SHIFT) 938 #define INTEL_DISP_EDP_PLL_FREQ_270 0 939 #define INTEL_DISP_EDP_PLL_FREQ_162 1 940 941 #define INTEL_TRANSCODER_A_DP_CTL (0x0300 | REGS_SOUTH_TRANSCODER_PORT) 942 #define INTEL_TRANSCODER_B_DP_CTL (0x1300 | REGS_SOUTH_TRANSCODER_PORT) 943 #define INTEL_TRANSCODER_C_DP_CTL (0x2300 | REGS_SOUTH_TRANSCODER_PORT) 944 945 #define INTEL_TRANS_DP_COLOR_SHIFT 9 946 #define INTEL_TRANS_DP_BPC(x) ((x) << INTEL_TRANS_DP_COLOR_SHIFT) 947 #define INTEL_TRANS_DP_BPC_MASK (7 << INTEL_TRANS_DP_COLOR_SHIFT) 948 #define INTEL_TRANS_DP_PORT_SHIFT 29 949 #define INTEL_TRANS_DP_PORT(x) ((x) << INTEL_TRANS_DP_PORT_SHIFT) 950 #define INTEL_TRANS_DP_PORT_MASK (3 << INTEL_TRANS_DP_PORT_SHIFT) 951 #define INTEL_TRANS_DP_PORT_B 0 952 #define INTEL_TRANS_DP_PORT_C 1 953 #define INTEL_TRANS_DP_PORT_D 2 954 #define INTEL_TRANS_DP_PORT_NONE 3 955 956 // Unless you're a damn Valley/CherryView unicorn :-( 957 #define VLV_DISPLAY_PORT_B (VLV_DISPLAY_BASE + 0x64100) 958 #define VLV_DISPLAY_PORT_C (VLV_DISPLAY_BASE + 0x64200) 959 #define CHV_DISPLAY_PORT_D (VLV_DISPLAY_BASE + 0x64300) 960 961 // DP AUX channels 962 #define _DPA_AUX_CH_CTL (0x4010 | REGS_NORTH_PIPE_AND_PORT) 963 #define _DPA_AUX_CH_DATA1 (0x4014 | REGS_NORTH_PIPE_AND_PORT) 964 #define _DPB_AUX_CH_CTL (0x4110 | REGS_NORTH_PIPE_AND_PORT) 965 #define _DPB_AUX_CH_DATA1 (0x4114 | REGS_NORTH_PIPE_AND_PORT) 966 #define DP_AUX_CH_CTL(aux) \ 967 (_DPA_AUX_CH_CTL + (_DPB_AUX_CH_CTL - _DPA_AUX_CH_CTL) * aux) 968 #define DP_AUX_CH_DATA(aux, i) \ 969 (_DPA_AUX_CH_DATA1 + (_DPB_AUX_CH_DATA1 - _DPA_AUX_CH_DATA1) * aux + i * 4) 970 971 #define INTEL_DP_AUX_CTL_BUSY (1 << 31) 972 #define INTEL_DP_AUX_CTL_DONE (1 << 30) 973 #define INTEL_DP_AUX_CTL_INTERRUPT (1 << 29) 974 #define INTEL_DP_AUX_CTL_TIMEOUT_ERROR (1 << 28) 975 #define INTEL_DP_AUX_CTL_TIMEOUT_400us (0 << 26) 976 #define INTEL_DP_AUX_CTL_TIMEOUT_600us (1 << 26) 977 #define INTEL_DP_AUX_CTL_TIMEOUT_800us (2 << 26) 978 #define INTEL_DP_AUX_CTL_TIMEOUT_1600us (3 << 26) 979 #define INTEL_DP_AUX_CTL_TIMEOUT_MASK (3 << 26) 980 #define INTEL_DP_AUX_CTL_RECEIVE_ERROR (1 << 25) 981 #define INTEL_DP_AUX_CTL_MSG_SIZE_MASK (0x1f << 20) 982 #define INTEL_DP_AUX_CTL_MSG_SIZE_SHIFT 20 983 #define INTEL_DP_AUX_CTL_PRECHARGE_2US_MASK (0xf << 16) 984 #define INTEL_DP_AUX_CTL_PRECHARGE_2US_SHIFT 16 985 #define INTEL_DP_AUX_CTL_BIT_CLOCK_2X_MASK (0x7ff) 986 #define INTEL_DP_AUX_CTL_BIT_CLOCK_2X_SHIFT 0 987 #define INTEL_DP_AUX_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5) 988 #define INTEL_DP_AUX_CTL_SYNC_PULSE_SKL(c) ((c) - 1) 989 990 // planes 991 #define INTEL_PIPE_ENABLED (1UL << 31) 992 #define INTEL_PIPE_STATE (1UL << 30) 993 994 #define INTEL_PLANE_OFFSET 0x1000 995 996 #define INTEL_DISPLAY_A_PIPE_CONTROL (0x0008 | REGS_NORTH_PLANE_CONTROL) 997 #define INTEL_DISPLAY_B_PIPE_CONTROL (0x1008 | REGS_NORTH_PLANE_CONTROL) 998 #define INTEL_DISPLAY_C_PIPE_CONTROL (0x2008 | REGS_NORTH_PLANE_CONTROL) 999 #define INTEL_DISPLAY_A_PIPE_STATUS (0x0024 | REGS_NORTH_PLANE_CONTROL) 1000 #define INTEL_DISPLAY_B_PIPE_STATUS (0x1024 | REGS_NORTH_PLANE_CONTROL) 1001 1002 #define INTEL_DISPLAY_A_PIPE_WATERMARK (0x5100 | REGS_NORTH_PLANE_CONTROL) 1003 #define INTEL_DISPLAY_B_PIPE_WATERMARK (0x5104 | REGS_NORTH_PLANE_CONTROL) 1004 #define INTEL_DISPLAY_C_PIPE_WATERMARK (0x5200 | REGS_NORTH_PLANE_CONTROL) 1005 1006 #define DISPLAY_PIPE_VBLANK_ENABLED (1UL << 17) 1007 #define DISPLAY_PIPE_VBLANK_STATUS (1UL << 1) 1008 1009 #define INTEL_DISPLAY_A_CONTROL (0x0180 | REGS_NORTH_PLANE_CONTROL) 1010 #define INTEL_DISPLAY_A_BASE (0x0184 | REGS_NORTH_PLANE_CONTROL) 1011 #define INTEL_DISPLAY_A_BYTES_PER_ROW (0x0188 | REGS_NORTH_PLANE_CONTROL) 1012 #define INTEL_DISPLAY_A_POS (0x018c | REGS_NORTH_PLANE_CONTROL) 1013 // reserved on A 1014 #define INTEL_DISPLAY_A_IMAGE_SIZE (0x0190 | REGS_NORTH_PLANE_CONTROL) 1015 #define INTEL_DISPLAY_A_SURFACE (0x019c | REGS_NORTH_PLANE_CONTROL) 1016 #define INTEL_DISPLAY_A_OFFSET_HAS (0x01a4 | REGS_NORTH_PLANE_CONTROL) 1017 // i965 and up only 1018 1019 #define INTEL_DISPLAY_B_CONTROL (0x1180 | REGS_NORTH_PLANE_CONTROL) 1020 #define INTEL_DISPLAY_B_BASE (0x1184 | REGS_NORTH_PLANE_CONTROL) 1021 #define INTEL_DISPLAY_B_BYTES_PER_ROW (0x1188 | REGS_NORTH_PLANE_CONTROL) 1022 #define INTEL_DISPLAY_B_POS (0x118c | REGS_NORTH_PLANE_CONTROL) 1023 #define INTEL_DISPLAY_B_IMAGE_SIZE (0x1190 | REGS_NORTH_PLANE_CONTROL) 1024 #define INTEL_DISPLAY_B_SURFACE (0x119c | REGS_NORTH_PLANE_CONTROL) 1025 #define INTEL_DISPLAY_B_OFFSET_HAS (0x11a4 | REGS_NORTH_PLANE_CONTROL) 1026 // i965 and up only 1027 1028 // INTEL_DISPLAY_A_CONTROL source pixel format 1029 #define DISPLAY_CONTROL_ENABLED (1UL << 31) 1030 #define DISPLAY_CONTROL_GAMMA (1UL << 30) 1031 #define DISPLAY_CONTROL_COLOR_MASK (0x0fUL << 26) 1032 #define DISPLAY_CONTROL_CMAP8 (2UL << 26) 1033 #define DISPLAY_CONTROL_RGB15 (4UL << 26) 1034 #define DISPLAY_CONTROL_RGB16 (5UL << 26) 1035 #define DISPLAY_CONTROL_RGB32 (6UL << 26) 1036 #define DISPLAY_CONTROL_RGB64 (0x0cUL << 26) 1037 // Skylake 1038 #define DISPLAY_CONTROL_COLOR_MASK_SKY (0x0fUL << 24) 1039 #define DISPLAY_CONTROL_CMAP8_SKY (0x0cUL << 24) 1040 #define DISPLAY_CONTROL_RGB15_SKY (0x0eUL << 24) 1041 #define DISPLAY_CONTROL_RGB16_SKY (0x0eUL << 24) 1042 #define DISPLAY_CONTROL_RGB32_SKY (0x04UL << 24) 1043 #define DISPLAY_CONTROL_RGB64_SKY (0x06UL << 24) 1044 1045 // INTEL_DISPLAY_A_PIPE_CONTROL ILK+ 1046 #define INTEL_PIPE_DITHER_TYPE_MASK (0x0000000c) 1047 #define INTEL_PIPE_DITHER_TYPE_SP (0 << 2) 1048 #define INTEL_PIPE_DITHER_TYPE_ST1 (1 << 2) 1049 #define INTEL_PIPE_DITHER_TYPE_ST2 (2 << 2) 1050 #define INTEL_PIPE_DITHER_TYPE_TEMP (3 << 2) 1051 #define INTEL_PIPE_DITHER_EN (1 << 4) 1052 #define INTEL_PIPE_COLOR_SHIFT 5 1053 #define INTEL_PIPE_BPC(x) ((x) << INTEL_PIPE_COLOR_SHIFT) 1054 #define INTEL_PIPE_BPC_MASK (7 << INTEL_PIPE_COLOR_SHIFT) 1055 #define INTEL_PIPE_8BPC 0 1056 #define INTEL_PIPE_10BPC 1 1057 #define INTEL_PIPE_6BPC 2 1058 #define INTEL_PIPE_12BPC 3 1059 #define INTEL_PIPE_PROGRESSIVE (0 << 21) 1060 1061 // cursors 1062 #define INTEL_CURSOR_CONTROL (0x0080 | REGS_NORTH_PLANE_CONTROL) 1063 #define INTEL_CURSOR_BASE (0x0084 | REGS_NORTH_PLANE_CONTROL) 1064 #define INTEL_CURSOR_POSITION (0x0088 | REGS_NORTH_PLANE_CONTROL) 1065 #define INTEL_CURSOR_PALETTE (0x0090 | REGS_NORTH_PLANE_CONTROL) 1066 // (- 0x009f) 1067 #define INTEL_CURSOR_SIZE (0x00a0 | REGS_NORTH_PLANE_CONTROL) 1068 #define CURSOR_ENABLED (1UL << 31) 1069 #define CURSOR_FORMAT_2_COLORS (0UL << 24) 1070 #define CURSOR_FORMAT_3_COLORS (1UL << 24) 1071 #define CURSOR_FORMAT_4_COLORS (2UL << 24) 1072 #define CURSOR_FORMAT_ARGB (4UL << 24) 1073 #define CURSOR_FORMAT_XRGB (5UL << 24) 1074 #define CURSOR_POSITION_NEGATIVE 0x8000 1075 #define CURSOR_POSITION_MASK 0x3fff 1076 1077 // palette registers 1078 #define INTEL_DISPLAY_A_PALETTE (0xa000 | REGS_NORTH_SHARED) 1079 #define INTEL_DISPLAY_B_PALETTE (0xa800 | REGS_NORTH_SHARED) 1080 1081 // Ironlake PCH reference clk control 1082 #define PCH_DREF_CONTROL (0x6200 | REGS_SOUTH_SHARED) 1083 #define DREF_CONTROL_MASK 0x7fc3 1084 #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0 << 13) 1085 #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2 << 13) 1086 #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3 << 13) 1087 #define DREF_CPU_SOURCE_OUTPUT_MASK (3 << 13) 1088 #define DREF_SSC_SOURCE_DISABLE (0 << 11) 1089 #define DREF_SSC_SOURCE_ENABLE (2 << 11) 1090 #define DREF_SSC_SOURCE_MASK (3 << 11) 1091 #define DREF_NONSPREAD_SOURCE_DISABLE (0 << 9) 1092 #define DREF_NONSPREAD_CK505_ENABLE (1 << 9) 1093 #define DREF_NONSPREAD_SOURCE_ENABLE (2 << 9) 1094 #define DREF_NONSPREAD_SOURCE_MASK (3 << 9) 1095 #define DREF_SUPERSPREAD_SOURCE_DISABLE (0 << 7) 1096 #define DREF_SUPERSPREAD_SOURCE_ENABLE (2 << 7) 1097 #define DREF_SUPERSPREAD_SOURCE_MASK (3 << 7) 1098 #define DREF_SSC4_DOWNSPREAD (0 << 6) 1099 #define DREF_SSC4_CENTERSPREAD (1 << 6) 1100 #define DREF_SSC1_DISABLE (0 << 1) 1101 #define DREF_SSC1_ENABLE (1 << 1) 1102 #define DREF_SSC4_DISABLE (0 << 0) 1103 #define DREF_SSC4_ENABLE (1 << 0) 1104 1105 // PLL registers 1106 // Multiplier Divisor 1107 #define INTEL_DISPLAY_A_PLL (0x6014 | REGS_SOUTH_SHARED) 1108 #define INTEL_DISPLAY_B_PLL (0x6018 | REGS_SOUTH_SHARED) 1109 #define INTEL_DISPLAY_A_PLL_MD (0x601C | REGS_SOUTH_SHARED) 1110 #define INTEL_DISPLAY_B_PLL_MD (0x6020 | REGS_SOUTH_SHARED) 1111 #define CHV_DISPLAY_C_PLL (0x6030 | REGS_SOUTH_SHARED) 1112 #define CHV_DISPLAY_B_PLL_MD (0x603C | REGS_SOUTH_SHARED) 1113 1114 #define INTEL_DISPLAY_A_PLL_DIVISOR_0 (0x6040 | REGS_SOUTH_SHARED) 1115 #define INTEL_DISPLAY_A_PLL_DIVISOR_1 (0x6044 | REGS_SOUTH_SHARED) 1116 #define INTEL_DISPLAY_B_PLL_DIVISOR_0 (0x6048 | REGS_SOUTH_SHARED) 1117 #define INTEL_DISPLAY_B_PLL_DIVISOR_1 (0x604c | REGS_SOUTH_SHARED) 1118 1119 #define SNB_DPLL_SEL (0x7000 | REGS_SOUTH_SHARED) 1120 1121 // i2c bit banging interface 1122 #define INTEL_I2C_IO_A (0x5010 | REGS_SOUTH_SHARED) 1123 #define INTEL_I2C_IO_B (0x5014 | REGS_SOUTH_SHARED) 1124 #define INTEL_I2C_IO_C (0x5018 | REGS_SOUTH_SHARED) 1125 #define INTEL_I2C_IO_D (0x501c | REGS_SOUTH_SHARED) 1126 #define INTEL_I2C_IO_E (0x5020 | REGS_SOUTH_SHARED) 1127 #define INTEL_I2C_IO_F (0x5024 | REGS_SOUTH_SHARED) 1128 #define INTEL_I2C_IO_G (0x5028 | REGS_SOUTH_SHARED) 1129 #define INTEL_I2C_IO_H (0x502c | REGS_SOUTH_SHARED) 1130 // i2c hardware controller 1131 #define INTEL_GMBUS0 (0x5100 | REGS_SOUTH_SHARED) 1132 #define INTEL_GMBUS4 (0x5110 | REGS_SOUTH_SHARED) 1133 1134 #define I2C_CLOCK_DIRECTION_MASK (1 << 0) 1135 #define I2C_CLOCK_DIRECTION_OUT (1 << 1) 1136 #define I2C_CLOCK_VALUE_MASK (1 << 2) 1137 #define I2C_CLOCK_VALUE_OUT (1 << 3) 1138 #define I2C_CLOCK_VALUE_IN (1 << 4) 1139 #define I2C_DATA_DIRECTION_MASK (1 << 8) 1140 #define I2C_DATA_DIRECTION_OUT (1 << 9) 1141 #define I2C_DATA_VALUE_MASK (1 << 10) 1142 #define I2C_DATA_VALUE_OUT (1 << 11) 1143 #define I2C_DATA_VALUE_IN (1 << 12) 1144 #define I2C_RESERVED ((1 << 13) | (1 << 5)) 1145 1146 // gpu block clock gating disable bits 1147 #define INTEL_DSPCLK_GATE_D (0x2020 | REGS_SOUTH_SHARED) 1148 #define PCH_GMBUSUNIT_CLK_GATE_DIS (1UL << 31) 1149 #define INTEL_GEN9_CLKGATE_DIS_4 (0x653c | REGS_NORTH_SHARED) 1150 #define BXT_GMBUSUNIT_CLK_GATE_DIS (1 << 14) 1151 1152 // gpu power wells (confirmed skylake) 1153 #define INTEL_PWR_WELL_CTL_1_BIOS (0x5400 | REGS_NORTH_SHARED) 1154 #define INTEL_PWR_WELL_CTL_2_DRIVER (0x5404 | REGS_NORTH_SHARED) 1155 1156 #define HSW_PWR_WELL_CTL_REQ(i) (0x2 << ((2 * i))) 1157 #define HSW_PWR_WELL_CTL_STATE(i) (0x1 << ((2 * i))) 1158 1159 #define HSW_PWR_WELL_CTL1 INTEL_PWR_WELL_CTL_1_BIOS 1160 #define HSW_PWR_WELL_CTL2 INTEL_PWR_WELL_CTL_2_DRIVER 1161 #define HSW_PWR_WELL_CTL3 (0x5408 | REGS_NORTH_SHARED) 1162 #define HSW_PWR_WELL_CTL4 (0x540c | REGS_NORTH_SHARED) 1163 1164 #define ICL_PWR_WELL_CTL_AUX1 (0x5440 | REGS_NORTH_SHARED) 1165 #define ICL_PWR_WELL_CTL_AUX2 (0x5444 | REGS_NORTH_SHARED) 1166 #define ICL_PWR_WELL_CTL_AUX4 (0x544c | REGS_NORTH_SHARED) 1167 1168 #define ICL_PWR_WELL_CTL_DDI1 (0x5450 | REGS_NORTH_SHARED) 1169 #define ICL_PWR_WELL_CTL_DDI2 (0x5454 | REGS_NORTH_SHARED) 1170 #define ICL_PWR_WELL_CTL_DDI4 (0x545c | REGS_NORTH_SHARED) 1171 1172 // gpu pll enable registers (confirmed skylake) 1173 #define INTEL_WRPLL_CTL_1_DPLL2 (0x6040 | REGS_NORTH_SHARED) 1174 #define INTEL_WRPLL_CTL_2_DPLL3 (0x6060 | REGS_NORTH_SHARED) 1175 #define WRPLL_PLL_ENABLE (1 << 31) 1176 1177 // TODO: on IronLake this is in the north shared block at 0x41000 1178 #define INTEL_VGA_DISPLAY_CONTROL (0x1400 | REGS_NORTH_PLANE_CONTROL) 1179 #define VGA_DISPLAY_DISABLED (1UL << 31) 1180 1181 // LVDS panel 1182 #define INTEL_PANEL_STATUS (0x1200 | REGS_NORTH_PIPE_AND_PORT) 1183 #define INTEL_PANEL_CONTROL (0x1204 | REGS_NORTH_PIPE_AND_PORT) 1184 #define INTEL_PANEL_FIT_CONTROL (0x1230 | REGS_NORTH_PIPE_AND_PORT) 1185 #define INTEL_PANEL_FIT_RATIOS (0x1234 | REGS_NORTH_PIPE_AND_PORT) 1186 1187 // LVDS on IronLake and up 1188 #define PCH_PANEL_STATUS (0x7200 | REGS_SOUTH_SHARED) 1189 #define PCH_PANEL_CONTROL (0x7204 | REGS_SOUTH_SHARED) 1190 #define PCH_PANEL_ON_DELAYS (0x7208 | REGS_SOUTH_SHARED) 1191 #define PCH_PANEL_OFF_DELAYS (0x720c | REGS_SOUTH_SHARED) 1192 #define PCH_PANEL_DIVISOR (0x7210 | REGS_SOUTH_SHARED) 1193 #define PCH_LVDS_DETECTED (1 << 1) 1194 1195 #define PANEL_STATUS_POWER_ON (1UL << 31) 1196 #define PANEL_CONTROL_POWER_TARGET_OFF (0UL << 0) 1197 #define PANEL_CONTROL_POWER_TARGET_ON (1UL << 0) 1198 #define PANEL_CONTROL_POWER_TARGET_RST (1UL << 1) 1199 #define PANEL_REGISTER_UNLOCK (0xabcd << 16) 1200 1201 // PCH_PANEL_ON_DELAYS 1202 #define PANEL_DELAY_PORT_SELECT_MASK (3 << 30) 1203 #define PANEL_DELAY_PORT_SELECT_LVDS (0 << 30) 1204 #define PANEL_DELAY_PORT_SELECT_DPA (1 << 30) 1205 #define PANEL_DELAY_PORT_SELECT_DPC (2 << 30) 1206 #define PANEL_DELAY_PORT_SELECT_DPD (3 << 30) 1207 1208 // PCH_PANEL_DIVISOR 1209 #define PANEL_DIVISOR_REFERENCE_DIV_MASK 0xffffff00 1210 #define PANEL_DIVISOR_REFERENCE_DIV_SHIFT 8 1211 #define PANEL_DIVISOR_POW_CYCLE_DLY_MASK 0x1f 1212 #define PANEL_DIVISOR_POW_CYCLE_DLY_SHIFT 0x1f 1213 1214 // Backlight control registers 1215 // These have moved around, initially they were per pipe, then they were moved in the "north" part 1216 // of the PCH with a single backlight control (independant of pipes), and then moved again to the 1217 // "south" part of the PCH, with a simplified register layout. 1218 #define PCH_BLC_PWM_CTL2 (0x8250 | REGS_NORTH_SHARED) // Linux BLC_PWM_CPU_CTL2 1219 #define PCH_BLC_PWM_CTL (0x8254 | REGS_NORTH_SHARED) // Linux BLC_PWM_CPU_CTL 1220 1221 // Kaby Lake/Sunrisepoint 1222 #define BLC_PWM_PCH_CTL1 (0x8250 | REGS_SOUTH_SHARED) // Enable with bit 31 1223 #define BLC_PWM_PCH_CTL2 (0x8254 | REGS_SOUTH_SHARED) // Duty Cycle and Period 1224 1225 // Devices after Cannonlake have a new register layout, with separate registers for the period 1226 // and duty cycle instead of having two 16bit values in a 32bit register 1227 #define PCH_SOUTH_BLC_PWM_CONTROL (0x8250 | REGS_SOUTH_SHARED) // Linux _BXT_BLC_PWM_CTL1 1228 #define PCH_SOUTH_BLC_PWM_PERIOD (0x8254 | REGS_SOUTH_SHARED) // Linux _BXT_BLC_PWM_FREQ1 1229 #define PCH_SOUTH_BLC_PWM_DUTY_CYCLE (0x8258 | REGS_SOUTH_SHARED) // Linux _BXT_BLC_PWM_DUTY1 1230 1231 #define MCH_BLC_PWM_CTL (0x1254 | REGS_NORTH_PIPE_AND_PORT) 1232 // Linux VLV_BLC_PWM_CTL (one register per pipe) or BLC_PWM_CTL (a single register that can be 1233 // programmed for use on either pipe) 1234 #define BLM_LEGACY_MODE (1 << 16) 1235 1236 // ring buffer commands 1237 1238 #define COMMAND_NOOP 0x00 1239 #define COMMAND_WAIT_FOR_EVENT (0x03 << 23) 1240 #define COMMAND_WAIT_FOR_OVERLAY_FLIP (1 << 16) 1241 1242 #define COMMAND_FLUSH (0x04 << 23) 1243 1244 // overlay flip 1245 #define COMMAND_OVERLAY_FLIP (0x11 << 23) 1246 #define COMMAND_OVERLAY_CONTINUE (0 << 21) 1247 #define COMMAND_OVERLAY_ON (1 << 21) 1248 #define COMMAND_OVERLAY_OFF (2 << 21) 1249 #define OVERLAY_UPDATE_COEFFICIENTS 0x1 1250 1251 // 2D acceleration 1252 #define XY_COMMAND_SOURCE_BLIT 0x54c00006 1253 #define XY_COMMAND_COLOR_BLIT 0x54000004 1254 #define XY_COMMAND_SETUP_MONO_PATTERN 0x44400007 1255 #define XY_COMMAND_SCANLINE_BLIT 0x49400001 1256 #define COMMAND_COLOR_BLIT 0x50000003 1257 #define COMMAND_BLIT_RGBA 0x00300000 1258 1259 #define COMMAND_MODE_SOLID_PATTERN 0x80 1260 #define COMMAND_MODE_CMAP8 0x00 1261 #define COMMAND_MODE_RGB15 0x02 1262 #define COMMAND_MODE_RGB16 0x01 1263 #define COMMAND_MODE_RGB32 0x03 1264 1265 // overlay 1266 #define INTEL_OVERLAY_UPDATE 0x30000 1267 #define INTEL_OVERLAY_TEST 0x30004 1268 #define INTEL_OVERLAY_STATUS 0x30008 1269 #define INTEL_OVERLAY_EXTENDED_STATUS 0x3000c 1270 #define INTEL_OVERLAY_GAMMA_5 0x30010 1271 #define INTEL_OVERLAY_GAMMA_4 0x30014 1272 #define INTEL_OVERLAY_GAMMA_3 0x30018 1273 #define INTEL_OVERLAY_GAMMA_2 0x3001c 1274 #define INTEL_OVERLAY_GAMMA_1 0x30020 1275 #define INTEL_OVERLAY_GAMMA_0 0x30024 1276 1277 // FDI - Flexible Display Interface, the interface between the (CPU-internal) 1278 // GPU and the PCH display outputs. Proprietary interface, based on DisplayPort 1279 // though, so similar link training and all... 1280 // There's an FDI transmitter (TX) on the CPU and an FDI receiver (RX) on the 1281 // PCH for each display pipe. 1282 // FDI receiver A is hooked up to transcoder A, FDI receiver B is hooked up to 1283 // transcoder B, so we have the same mapping as with the display pipes. 1284 #define PCH_FDI_RX_BASE_REGISTER 0xf0000 1285 #define PCH_FDI_RX_PIPE_OFFSET 0x01000 1286 #define PCH_FDI_RX_CONTROL 0x00c 1287 #define PCH_FDI_RX_MISC 0x010 1288 #define PCH_FDI_RX_IIR 0x014 1289 #define PCH_FDI_RX_IMR 0x018 1290 1291 #define FDI_RX_ENABLE (1 << 31) 1292 #define FDI_RX_PLL_ENABLED (1 << 13) 1293 1294 #define FDI_RX_LINK_COLOR_SHIFT 16 1295 #define FDI_RX_LINK_BPC(x) ((x) << FDI_RX_LINK_COLOR_SHIFT) 1296 #define FDI_RX_LINK_BPC_MASK (7 << FDI_RX_LINK_COLOR_SHIFT) 1297 1298 // Transcoder - same base as FDI_RX 1299 #define PCH_TRANS_CONF_A 0x0008 1300 #define PCH_TRANS_CONF_B 0x1008 1301 #define PCH_TRANS_CONF_C 0x2008 1302 1303 // Transcoder - skylake DDI 1304 #define DDI_SKL_TRANS_CONF_A (0x0008 | REGS_NORTH_PLANE_CONTROL) 1305 #define DDI_SKL_TRANS_CONF_B (0x1008 | REGS_NORTH_PLANE_CONTROL) 1306 #define DDI_SKL_TRANS_CONF_C (0x2008 | REGS_NORTH_PLANE_CONTROL) 1307 #define DDI_SKL_TRANS_CONF_EDP (0xf008 | REGS_NORTH_PLANE_CONTROL) 1308 1309 #define TRANS_ENABLE (1 << 31) 1310 #define TRANS_ENABLED (1 << 30) 1311 1312 // FDI_tX interrupt register 1313 #define FDI_RX_INTER_LANE_ALIGN (1 << 10) 1314 #define FDI_RX_SYMBOL_LOCK (1 << 9) 1315 #define FDI_RX_BIT_LOCK (1 << 8) 1316 #define FDI_RX_TRAIN_PATTERN_2_FAIL (1 << 7) 1317 #define FDI_RX_FS_CODE_ERR (1 << 6) 1318 #define FDI_RX_FE_CODE_ERR (1 << 5) 1319 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1 << 4) 1320 #define FDI_RX_HDCP_LINK_FAIL (1 << 3) 1321 #define FDI_RX_PIXEL_FIFO_OVERFLOW (1 << 2) 1322 #define FDI_RX_CROSS_CLOCK_OVERFLOW (1 << 1) 1323 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1 << 0) 1324 1325 #define FDI_FS_ERRC_ENABLE (1 << 27) 1326 #define FDI_FE_ERRC_ENABLE (1 << 26) 1327 1328 #define PCH_FDI_RX_TRANS_UNIT_SIZE_1 0x30 1329 #define PCH_FDI_RX_TRANS_UNIT_SIZE_2 0x38 1330 #define FDI_RX_TRANS_UNIT_SIZE(x) ((x - 1) << 25) 1331 #define FDI_RX_TRANS_UNIT_MASK 0x7e000000 1332 1333 #define FDI_RX_ENHANCE_FRAME_ENABLE (1 << 6) 1334 #define FDI_RX_CLOCK_MASK (1 << 4) 1335 #define FDI_RX_CLOCK_RAW (0 << 4) 1336 #define FDI_RX_CLOCK_PCD (1 << 4) 1337 1338 // FDI RX MISC 1339 #define FDI_RX_PWRDN_LANE1_MASK (3 << 26) 1340 #define FDI_RX_PWRDN_LANE1_VAL(x) ((x) << 26) 1341 #define FDI_RX_PWRDN_LANE0_MASK (3 << 24) 1342 #define FDI_RX_PWRDN_LANE0_VAL(x) ((x) << 24) 1343 #define FDI_RX_TP1_TO_TP2_48 (2 << 20) 1344 #define FDI_RX_TP1_TO_TP2_64 (3 << 20) 1345 #define FDI_RX_FDI_DELAY_90 (0x90 << 0) 1346 1347 #define PCH_FDI_TX_BASE_REGISTER 0x60000 1348 #define PCH_FDI_TX_PIPE_OFFSET 0x01000 1349 #define PCH_FDI_TX_CONTROL 0x100 1350 #define FDI_TX_ENABLE (1 << 31) 1351 #define FDI_LINK_TRAIN_PATTERN_1 (0 << 28) 1352 #define FDI_LINK_TRAIN_PATTERN_2 (1 << 28) 1353 #define FDI_LINK_TRAIN_PATTERN_IDLE (2 << 28) 1354 #define FDI_LINK_TRAIN_NONE (3 << 28) 1355 #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0 << 25) 1356 #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1 << 25) 1357 #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2 << 25) 1358 #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3 << 25) 1359 #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0 << 22) 1360 #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1 << 22) 1361 #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2 << 22) 1362 #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3 << 22) 1363 1364 // FDI/PIPE M/N DATA AND LINK VALUES (refreshrate) 1365 #define PCH_FDI_PIPE_A_DATA_M1 (0x0030 | REGS_NORTH_PIPE_AND_PORT) 1366 #define PCH_FDI_PIPE_A_DATA_M2 (0x0038 | REGS_NORTH_PIPE_AND_PORT) 1367 #define PCH_FDI_PIPE_B_DATA_M1 (0x1030 | REGS_NORTH_PIPE_AND_PORT) 1368 #define PCH_FDI_PIPE_B_DATA_M2 (0x1038 | REGS_NORTH_PIPE_AND_PORT) 1369 #define PCH_FDI_PIPE_C_DATA_M1 (0x2030 | REGS_NORTH_PIPE_AND_PORT) 1370 #define PCH_FDI_PIPE_C_DATA_M2 (0x2038 | REGS_NORTH_PIPE_AND_PORT) 1371 #define PCH_FDI_PIPE_A_DATA_N1 (0x0034 | REGS_NORTH_PIPE_AND_PORT) 1372 #define PCH_FDI_PIPE_A_DATA_N2 (0x003c | REGS_NORTH_PIPE_AND_PORT) 1373 #define PCH_FDI_PIPE_B_DATA_N1 (0x1034 | REGS_NORTH_PIPE_AND_PORT) 1374 #define PCH_FDI_PIPE_B_DATA_N2 (0x103c | REGS_NORTH_PIPE_AND_PORT) 1375 #define PCH_FDI_PIPE_C_DATA_N1 (0x2034 | REGS_NORTH_PIPE_AND_PORT) 1376 #define PCH_FDI_PIPE_C_DATA_N2 (0x203c | REGS_NORTH_PIPE_AND_PORT) 1377 #define PCH_FDI_PIPE_A_LINK_M1 (0x0040 | REGS_NORTH_PIPE_AND_PORT) 1378 #define PCH_FDI_PIPE_A_LINK_M2 (0x0048 | REGS_NORTH_PIPE_AND_PORT) 1379 #define PCH_FDI_PIPE_B_LINK_M1 (0x1040 | REGS_NORTH_PIPE_AND_PORT) 1380 #define PCH_FDI_PIPE_B_LINK_M2 (0x1048 | REGS_NORTH_PIPE_AND_PORT) 1381 #define PCH_FDI_PIPE_C_LINK_M1 (0x2040 | REGS_NORTH_PIPE_AND_PORT) 1382 #define PCH_FDI_PIPE_C_LINK_M2 (0x2048 | REGS_NORTH_PIPE_AND_PORT) 1383 #define PCH_FDI_PIPE_A_LINK_N1 (0x0044 | REGS_NORTH_PIPE_AND_PORT) 1384 #define PCH_FDI_PIPE_A_LINK_N2 (0x004c | REGS_NORTH_PIPE_AND_PORT) 1385 #define PCH_FDI_PIPE_B_LINK_N1 (0x1044 | REGS_NORTH_PIPE_AND_PORT) 1386 #define PCH_FDI_PIPE_B_LINK_N2 (0x104c | REGS_NORTH_PIPE_AND_PORT) 1387 #define PCH_FDI_PIPE_C_LINK_N1 (0x2044 | REGS_NORTH_PIPE_AND_PORT) 1388 #define PCH_FDI_PIPE_C_LINK_N2 (0x204c | REGS_NORTH_PIPE_AND_PORT) 1389 #define FDI_PIPE_MN_TU_SIZE_MASK (0x3f << 25) 1390 #define FDI_PIPE_MN_VALUE_MASK (0xffffff << 0) 1391 1392 // SNB A stepping 1393 #define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22) 1394 #define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22) 1395 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22) 1396 #define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x00 << 22) 1397 1398 // SNB B stepping 1399 #define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x00 << 22) 1400 #define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a << 22) 1401 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39 << 22) 1402 #define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38 << 22) 1403 #define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f << 22) 1404 #define FDI_TX_ENHANCE_FRAME_ENABLE (1 << 18) 1405 #define FDI_TX_PLL_ENABLED (1 << 14) 1406 1407 #define FDI_DP_PORT_WIDTH_SHIFT 19 1408 #define FDI_DP_PORT_WIDTH_MASK (7 << FDI_DP_PORT_WIDTH_SHIFT) 1409 #define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT) 1410 1411 #define FDI_PLL_BIOS_0 0x46000 1412 #define FDI_PLL_FB_CLOCK_MASK 0xff 1413 #define FDI_PLL_BIOS_1 0x46004 1414 #define FDI_PLL_BIOS_2 0x46008 1415 1416 #define FDI_AUTO_TRAINING (1 << 10) 1417 #define FDI_AUTO_TRAIN_DONE (1 << 1) 1418 1419 #define FDI_LINK_TRAIN_PATTERN_1_CPT (0 << 8) 1420 #define FDI_LINK_TRAIN_PATTERN_2_CPT (1 << 8) 1421 #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2 << 8) 1422 #define FDI_LINK_TRAIN_NORMAL_CPT (3 << 8) 1423 #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3 << 8) 1424 1425 // IvyBridge changes it up because... they hate developers? 1426 #define FDI_LINK_TRAIN_PATTERN_1_IVB (0 << 8) 1427 #define FDI_LINK_TRAIN_PATTERN_2_IVB (1 << 8) 1428 #define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2 << 8) 1429 #define FDI_LINK_TRAIN_NONE_IVB (3 << 8) 1430 1431 #define PCH_FDI_RXA_CHICKEN (0x200c | REGS_SOUTH_SHARED) 1432 #define PCH_FDI_RXB_CHICKEN (0x2010 | REGS_SOUTH_SHARED) 1433 #define FDI_RX_PHASE_SYNC_POINTER_EN (1 << 0) 1434 #define FDI_RX_PHASE_SYNC_POINTER_OVR (1 << 1) 1435 1436 // CPU Panel Fitters - These are for IronLake and up and are the CPU internal 1437 // panel fitters. 1438 #define PCH_PANEL_FITTER_BASE_REGISTER 0x68000 1439 #define PCH_PANEL_FITTER_PIPE_OFFSET 0x00800 1440 1441 #define PCH_PANEL_FITTER_WINDOW_POS 0x70 1442 #define PCH_PANEL_FITTER_WINDOW_SIZE 0x74 1443 #define PCH_PANEL_FITTER_CONTROL 0x80 1444 //not on IvyBridge: 1445 #define PCH_PANEL_FITTER_V_SCALE 0x84 1446 #define PCH_PANEL_FITTER_H_SCALE 0x90 1447 1448 #define PANEL_FITTER_ENABLED (1 << 31) 1449 //pipes are hardcoded according to offset on SkyLake and later 1450 #define PANEL_FITTER_PIPE_MASK (3 << 29) 1451 #define PANEL_FITTER_PIPE_A (0 << 29) 1452 #define PANEL_FITTER_PIPE_B (1 << 29) 1453 #define PANEL_FITTER_PIPE_C (2 << 29) 1454 #define PANEL_FITTER_SCALING_MODE_MASK (7 << 26) 1455 #define PANEL_FITTER_FILTER_MASK (3 << 24) 1456 1457 struct overlay_scale { 1458 uint32 _reserved0 : 3; 1459 uint32 horizontal_scale_fraction : 12; 1460 uint32 _reserved1 : 1; 1461 uint32 horizontal_downscale_factor : 3; 1462 uint32 _reserved2 : 1; 1463 uint32 vertical_scale_fraction : 12; 1464 }; 1465 1466 #define OVERLAY_FORMAT_RGB15 0x2 1467 #define OVERLAY_FORMAT_RGB16 0x3 1468 #define OVERLAY_FORMAT_RGB32 0x1 1469 #define OVERLAY_FORMAT_YCbCr422 0x8 1470 #define OVERLAY_FORMAT_YCbCr411 0x9 1471 #define OVERLAY_FORMAT_YCbCr420 0xc 1472 1473 #define OVERLAY_MIRROR_NORMAL 0x0 1474 #define OVERLAY_MIRROR_HORIZONTAL 0x1 1475 #define OVERLAY_MIRROR_VERTICAL 0x2 1476 1477 // The real overlay registers are written to using an update buffer 1478 1479 struct overlay_registers { 1480 uint32 buffer_rgb0; 1481 uint32 buffer_rgb1; 1482 uint32 buffer_u0; 1483 uint32 buffer_v0; 1484 uint32 buffer_u1; 1485 uint32 buffer_v1; 1486 // (0x18) OSTRIDE - overlay stride 1487 uint16 stride_rgb; 1488 uint16 stride_uv; 1489 // (0x1c) YRGB_VPH - Y/RGB vertical phase 1490 uint16 vertical_phase0_rgb; 1491 uint16 vertical_phase1_rgb; 1492 // (0x20) UV_VPH - UV vertical phase 1493 uint16 vertical_phase0_uv; 1494 uint16 vertical_phase1_uv; 1495 // (0x24) HORZ_PH - horizontal phase 1496 uint16 horizontal_phase_rgb; 1497 uint16 horizontal_phase_uv; 1498 // (0x28) INIT_PHS - initial phase shift 1499 uint32 initial_vertical_phase0_shift_rgb0 : 4; 1500 uint32 initial_vertical_phase1_shift_rgb0 : 4; 1501 uint32 initial_horizontal_phase_shift_rgb0 : 4; 1502 uint32 initial_vertical_phase0_shift_uv : 4; 1503 uint32 initial_vertical_phase1_shift_uv : 4; 1504 uint32 initial_horizontal_phase_shift_uv : 4; 1505 uint32 _reserved0 : 8; 1506 // (0x2c) DWINPOS - destination window position 1507 uint16 window_left; 1508 uint16 window_top; 1509 // (0x30) DWINSZ - destination window size 1510 uint16 window_width; 1511 uint16 window_height; 1512 // (0x34) SWIDTH - source width 1513 uint16 source_width_rgb; 1514 uint16 source_width_uv; 1515 // (0x38) SWITDHSW - source width in 8 byte steps 1516 uint16 source_bytes_per_row_rgb; 1517 uint16 source_bytes_per_row_uv; 1518 uint16 source_height_rgb; 1519 uint16 source_height_uv; 1520 overlay_scale scale_rgb; 1521 overlay_scale scale_uv; 1522 // (0x48) OCLRC0 - overlay color correction 0 1523 uint32 brightness_correction : 8; // signed, -128 to 127 1524 uint32 _reserved1 : 10; 1525 uint32 contrast_correction : 9; // fixed point: 3.6 bits 1526 uint32 _reserved2 : 5; 1527 // (0x4c) OCLRC1 - overlay color correction 1 1528 uint32 saturation_cos_correction : 10; // fixed point: 3.7 bits 1529 uint32 _reserved3 : 6; 1530 uint32 saturation_sin_correction : 11; // signed fixed point: 3.7 bits 1531 uint32 _reserved4 : 5; 1532 // (0x50) DCLRKV - destination color key value 1533 uint32 color_key_blue : 8; 1534 uint32 color_key_green : 8; 1535 uint32 color_key_red : 8; 1536 uint32 _reserved5 : 8; 1537 // (0x54) DCLRKM - destination color key mask 1538 uint32 color_key_mask_blue : 8; 1539 uint32 color_key_mask_green : 8; 1540 uint32 color_key_mask_red : 8; 1541 uint32 _reserved6 : 7; 1542 uint32 color_key_enabled : 1; 1543 // (0x58) SCHRKVH - source chroma key high value 1544 uint32 source_chroma_key_high_red : 8; 1545 uint32 source_chroma_key_high_blue : 8; 1546 uint32 source_chroma_key_high_green : 8; 1547 uint32 _reserved7 : 8; 1548 // (0x5c) SCHRKVL - source chroma key low value 1549 uint32 source_chroma_key_low_red : 8; 1550 uint32 source_chroma_key_low_blue : 8; 1551 uint32 source_chroma_key_low_green : 8; 1552 uint32 _reserved8 : 8; 1553 // (0x60) SCHRKEN - source chroma key enable 1554 uint32 _reserved9 : 24; 1555 uint32 source_chroma_key_red_enabled : 1; 1556 uint32 source_chroma_key_blue_enabled : 1; 1557 uint32 source_chroma_key_green_enabled : 1; 1558 uint32 _reserved10 : 5; 1559 // (0x64) OCONFIG - overlay configuration 1560 uint32 _reserved11 : 3; 1561 uint32 color_control_output_mode : 1; 1562 uint32 yuv_to_rgb_bypass : 1; 1563 uint32 _reserved12 : 11; 1564 uint32 gamma2_enabled : 1; 1565 uint32 _reserved13 : 1; 1566 uint32 select_pipe : 1; 1567 uint32 slot_time : 8; 1568 uint32 _reserved14 : 5; 1569 // (0x68) OCOMD - overlay command 1570 uint32 overlay_enabled : 1; 1571 uint32 active_field : 1; 1572 uint32 active_buffer : 2; 1573 uint32 test_mode : 1; 1574 uint32 buffer_field_mode : 1; 1575 uint32 _reserved15 : 1; 1576 uint32 tv_flip_field_enabled : 1; 1577 uint32 _reserved16 : 1; 1578 uint32 tv_flip_field_parity : 1; 1579 uint32 source_format : 4; 1580 uint32 ycbcr422_order : 2; 1581 uint32 _reserved18 : 1; 1582 uint32 mirroring_mode : 2; 1583 uint32 _reserved19 : 13; 1584 1585 uint32 _reserved20; 1586 1587 uint32 start_0y; 1588 uint32 start_1y; 1589 uint32 start_0u; 1590 uint32 start_0v; 1591 uint32 start_1u; 1592 uint32 start_1v; 1593 uint32 _reserved21[6]; 1594 #if 0 1595 // (0x70) AWINPOS - alpha blend window position 1596 uint32 awinpos; 1597 // (0x74) AWINSZ - alpha blend window size 1598 uint32 awinsz; 1599 1600 uint32 _reserved21[10]; 1601 #endif 1602 1603 // (0xa0) FASTHSCALE - fast horizontal downscale (strangely enough, 1604 // the next two registers switch the usual Y/RGB vs. UV order) 1605 uint16 horizontal_scale_uv; 1606 uint16 horizontal_scale_rgb; 1607 // (0xa4) UVSCALEV - vertical downscale 1608 uint16 vertical_scale_uv; 1609 uint16 vertical_scale_rgb; 1610 1611 uint32 _reserved22[86]; 1612 1613 // (0x200) polyphase filter coefficients 1614 uint16 vertical_coefficients_rgb[128]; 1615 uint16 horizontal_coefficients_rgb[128]; 1616 1617 uint32 _reserved23[64]; 1618 1619 // (0x500) 1620 uint16 vertical_coefficients_uv[128]; 1621 uint16 horizontal_coefficients_uv[128]; 1622 }; 1623 1624 // i965 overlay support is currently realized using its 3D hardware 1625 #define INTEL_i965_OVERLAY_STATE_SIZE 36864 1626 #define INTEL_i965_3D_CONTEXT_SIZE 32768 1627 1628 inline bool 1629 intel_uses_physical_overlay(intel_shared_info &info) 1630 { 1631 return !info.device_type.InGroup(INTEL_GROUP_Gxx); 1632 } 1633 1634 1635 struct hardware_status { 1636 uint32 interrupt_status_register; 1637 uint32 _reserved0[3]; 1638 void* primary_ring_head_storage; 1639 uint32 _reserved1[3]; 1640 void* secondary_ring_0_head_storage; 1641 void* secondary_ring_1_head_storage; 1642 uint32 _reserved2[2]; 1643 void* binning_head_storage; 1644 uint32 _reserved3[3]; 1645 uint32 store[1008]; 1646 }; 1647 1648 #endif /* INTEL_EXTREME_H */ 1649