1 /* 2 * Copyright 2006, Haiku, Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Axel Dörfler, axeld@pinc-software.de 7 */ 8 #ifndef INTEL_EXTREME_H 9 #define INTEL_EXTREME_H 10 11 12 #include "lock.h" 13 14 #include <memory_manager.h> 15 16 #include <Accelerant.h> 17 #include <Drivers.h> 18 #include <PCI.h> 19 20 21 #define VENDOR_ID_INTEL 0x8086 22 23 #define INTEL_TYPE_FAMILY_MASK 0x0f 24 #define INTEL_TYPE_GROUP_MASK 0xf0 25 #define INTEL_TYPE_7xx 0x01 26 #define INTEL_TYPE_8xx 0x02 27 #define INTEL_TYPE_9xx 0x03 28 #define INTEL_TYPE_83x 0x10 29 #define INTEL_TYPE_85x 0x20 30 31 #define DEVICE_NAME "intel_extreme" 32 #define INTEL_ACCELERANT_NAME "intel_extreme.accelerant" 33 34 #define INTEL_COOKIE_MAGIC 'intl' 35 #define INTEL_FREE_COOKIE_MAGIC 'itlf' 36 37 // info about PLL on graphics card 38 struct pll_info { 39 uint32 reference_frequency; 40 uint32 max_frequency; 41 uint32 min_frequency; 42 uint32 divisor_register; 43 }; 44 45 struct ring_buffer { 46 struct lock lock; 47 uint32 register_base; 48 uint32 handle; 49 uint32 offset; 50 uint32 size; 51 uint32 position; 52 uint8 *base; 53 }; 54 55 struct overlay_registers; 56 57 struct intel_shared_info { 58 area_id mode_list_area; // area containing display mode list 59 uint32 mode_count; 60 61 display_mode current_mode; 62 uint32 bytes_per_row; 63 uint32 bits_per_pixel; 64 uint32 dpms_mode; 65 66 area_id registers_area; // area of memory mapped registers 67 uint8 *physical_status_page; 68 uint8 *physical_cursor_memory; 69 area_id graphics_memory_area; 70 uint8 *graphics_memory; 71 uint8 *physical_graphics_memory; 72 uint32 graphics_memory_size; 73 74 uint32 frame_buffer_offset; 75 76 struct lock accelerant_lock; 77 struct lock engine_lock; 78 79 ring_buffer primary_ring_buffer; 80 ring_buffer secondary_ring_buffer; 81 82 int32 overlay_channel_used; 83 bool overlay_active; 84 uint32 overlay_token; 85 uint8* physical_overlay_registers; 86 87 bool hardware_cursor_enabled; 88 sem_id vblank_sem; 89 90 uint32 cursor_buffer_offset; 91 uint32 cursor_format; 92 bool cursor_visible; 93 uint16 cursor_hot_x; 94 uint16 cursor_hot_y; 95 96 uint32 device_type; 97 char device_identifier[32]; 98 struct pll_info pll_info; 99 }; 100 101 //----------------- ioctl() interface ---------------- 102 103 // magic code for ioctls 104 #define INTEL_PRIVATE_DATA_MAGIC 'itic' 105 106 // list ioctls 107 enum { 108 INTEL_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1, 109 110 INTEL_GET_DEVICE_NAME, 111 INTEL_ALLOCATE_GRAPHICS_MEMORY, 112 INTEL_FREE_GRAPHICS_MEMORY 113 }; 114 115 // retrieve the area_id of the kernel/accelerant shared info 116 struct intel_get_private_data { 117 uint32 magic; // magic number 118 area_id shared_info_area; 119 }; 120 121 // allocate graphics memory 122 struct intel_allocate_graphics_memory { 123 uint32 magic; 124 uint32 size; 125 uint32 buffer_offset; 126 uint32 handle; 127 }; 128 129 // free graphics memory 130 struct intel_free_graphics_memory { 131 uint32 magic; 132 uint32 handle; 133 }; 134 135 //---------------------------------------------------------- 136 // Register definitions, taken from X driver 137 138 // PCI bridge memory management 139 #define INTEL_GRAPHICS_MEMORY_CONTROL 0x52 140 #define STOLEN_MEMORY_MASK 0x70 141 142 // models i830 and up 143 #define i830_LOCAL_MEMORY_ONLY 0x10 144 #define i830_STOLEN_512K 0x20 145 #define i830_STOLEN_1M 0x30 146 #define i830_STOLEN_8M 0x40 147 148 // models i855 and up 149 #define i855_STOLEN_MEMORY_1M 0x10 150 #define i855_STOLEN_MEMORY_4M 0x20 151 #define i855_STOLEN_MEMORY_8M 0x30 152 #define i855_STOLEN_MEMORY_16M 0x40 153 #define i855_STOLEN_MEMORY_32M 0x50 154 #define i855_STOLEN_MEMORY_48M 0x60 155 #define i855_STOLEN_MEMORY_64M 0x70 156 157 // graphics page translation table 158 #define INTEL_PAGE_TABLE_CONTROL 0x02020 159 #define INTEL_PAGE_TABLE_ERROR 0x02024 160 #define INTEL_HARDWARE_STATUS_PAGE 0x02080 161 #define INTEL_GTT_BASE 0x10000 // (- 0x2ffff) 162 #define GTT_ENTRY_VALID 0x01 163 #define GTT_ENTRY_LOCAL_MEMORY 0x02 164 165 // interrupts 166 #define INTEL_INTERRUPT_ENABLED 0x020a0 167 #define INTEL_INTERRUPT_IDENTITY 0x020a4 168 #define INTEL_INTERRUPT_MASK 0x020a8 169 #define INTEL_INTERRUPT_STATUS 0x020ac 170 #define INTERRUPT_VBLANK (1 << 7) 171 172 // ring buffer 173 #define INTEL_PRIMARY_RING_BUFFER 0x02030 174 #define INTEL_SECONDARY_RING_BUFFER_0 0x02100 175 #define INTEL_SECONDARY_RING_BUFFER_1 0x02110 176 // offsets for the ring buffer base registers above 177 #define RING_BUFFER_TAIL 0x0 178 #define RING_BUFFER_HEAD 0x4 179 #define RING_BUFFER_START 0x8 180 #define RING_BUFFER_CONTROL 0xc 181 #define INTEL_RING_BUFFER_SIZE_MASK 0x000ff800 182 #define INTEL_RING_BUFFER_HEAD_MASK 0x001ffffc 183 #define INTEL_RING_BUFFER_ENABLED 1 184 185 // display A 186 #define INTEL_DISPLAY_A_HTOTAL 0x60000 187 #define INTEL_DISPLAY_A_HBLANK 0x60004 188 #define INTEL_DISPLAY_A_HSYNC 0x60008 189 #define INTEL_DISPLAY_A_VTOTAL 0x6000c 190 #define INTEL_DISPLAY_A_VBLANK 0x60010 191 #define INTEL_DISPLAY_A_VSYNC 0x60014 192 #define INTEL_DISPLAY_A_IMAGE_SIZE 0x6001c 193 194 #define INTEL_DISPLAY_A_CONTROL 0x70180 195 #define INTEL_DISPLAY_A_BASE 0x70184 196 #define INTEL_DISPLAY_A_BYTES_PER_ROW 0x70188 197 #define DISPLAY_CONTROL_ENABLED (1UL << 31) 198 #define DISPLAY_CONTROL_GAMMA (1UL << 30) 199 #define DISPLAY_CONTROL_COLOR_MASK (0x0fUL << 26) 200 #define DISPLAY_CONTROL_CMAP8 (2UL << 26) 201 #define DISPLAY_CONTROL_RGB15 (4UL << 26) 202 #define DISPLAY_CONTROL_RGB16 (5UL << 26) 203 #define DISPLAY_CONTROL_RGB32 (7UL << 26) 204 205 #define INTEL_VGA_DISPLAY_CONTROL 0x71400 206 #define VGA_DISPLAY_DISABLED (1UL << 31) 207 208 #define INTEL_DISPLAY_A_PALETTE 0x0a000 209 210 #define INTEL_DISPLAY_A_PIPE_CONTROL 0x70008 211 #define DISPLAY_PIPE_ENABLED (1UL << 31) 212 #define INTEL_DISPLAY_A_PIPE_STATUS 0x70024 213 #define DISPLAY_PIPE_VBLANK_ENABLED (1UL << 17) 214 #define DISPLAY_PIPE_VBLANK_STATUS (1UL << 1) 215 216 #define INTEL_DISPLAY_A_PLL 0x06014 217 #define INTEL_DISPLAY_A_PLL_DIVISOR_0 0x06040 218 #define INTEL_DISPLAY_A_PLL_DIVISOR_1 0x06044 219 #define DISPLAY_PLL_ENABLED (1UL << 31) 220 #define DISPLAY_PLL_2X_CLOCK (1UL << 30) 221 #define DISPLAY_PLL_SYNC_LOCK_ENABLED (1UL << 29) 222 #define DISPLAY_PLL_NO_VGA_CONTROL (1UL << 28) 223 #define DISPLAY_PLL_DIVIDE_4X (1UL << 23) 224 #define DISPLAY_PLL_POST_DIVISOR_MASK 0x001f0000 225 #define DISPLAY_PLL_POST_DIVISOR_SHIFT 16 226 #define DISPLAY_PLL_DIVISOR_1 (1UL << 8) 227 #define DISPLAY_PLL_N_DIVISOR_MASK 0x001f0000 228 #define DISPLAY_PLL_M1_DIVISOR_MASK 0x00001f00 229 #define DISPLAY_PLL_M2_DIVISOR_MASK 0x0000001f 230 #define DISPLAY_PLL_N_DIVISOR_SHIFT 16 231 #define DISPLAY_PLL_M1_DIVISOR_SHIFT 8 232 #define DISPLAY_PLL_M2_DIVISOR_SHIFT 0 233 234 #define INTEL_DISPLAY_A_ANALOG_PORT 0x61100 235 #define DISPLAY_MONITOR_PORT_ENABLED (1UL << 31) 236 #define DISPLAY_MONITOR_VGA_POLARITY (1UL << 15) 237 #define DISPLAY_MONITOR_MODE_MASK (3UL << 10) 238 #define DISPLAY_MONITOR_ON 0 239 #define DISPLAY_MONITOR_SUSPEND (1UL << 10) 240 #define DISPLAY_MONITOR_STAND_BY (2UL << 10) 241 #define DISPLAY_MONITOR_OFF (3UL << 10) 242 #define DISPLAY_MONITOR_POLARITY_MASK (3UL << 3) 243 #define DISPLAY_MONITOR_POSITIVE_HSYNC (1UL << 3) 244 #define DISPLAY_MONITOR_POSITIVE_VSYNC (2UL << 3) 245 246 // display B 247 #define INTEL_DISPLAY_B_DIGITAL_PORT 0x61140 248 #define INTEL_DISPLAY_B_IMAGE_SIZE 0x6101c 249 250 #define INTEL_DISPLAY_B_PIPE_CONTROL 0x71008 251 252 #define INTEL_DISPLAY_B_CONTROL 0x71180 253 #define INTEL_DISPLAY_B_BASE 0x71184 254 #define INTEL_DISPLAY_B_BYTES_PER_ROW 0x71188 255 256 #define INTEL_DISPLAY_B_PALETTE 0x0a800 257 258 #define INTEL_DISPLAY_A_DIGITAL_PORT 0x61120 259 #define INTEL_DISPLAY_C_DIGITAL 0x61160 260 #define INTEL_DISPLAY_LVDS_PORT 0x61180 261 262 // cursor 263 #define INTEL_CURSOR_CONTROL 0x70080 264 #define INTEL_CURSOR_BASE 0x70084 265 #define INTEL_CURSOR_POSITION 0x70088 266 #define INTEL_CURSOR_PALETTE 0x70090 // (- 0x7009f) 267 #define INTEL_CURSOR_SIZE 0x700a0 268 #define CURSOR_ENABLED (1UL << 31) 269 #define CURSOR_FORMAT_2_COLORS (0UL << 24) 270 #define CURSOR_FORMAT_3_COLORS (1UL << 24) 271 #define CURSOR_FORMAT_4_COLORS (2UL << 24) 272 #define CURSOR_FORMAT_ARGB (4UL << 24) 273 #define CURSOR_FORMAT_XRGB (5UL << 24) 274 #define CURSOR_POSITION_NEGATIVE 0x8000 275 #define CURSOR_POSITION_MASK 0x3fff 276 277 // ring buffer commands 278 279 #define COMMAND_NOOP 0x00 280 #define COMMAND_WAIT_FOR_EVENT (0x03 << 23) 281 #define COMMAND_WAIT_FOR_OVERLAY_FLIP (1 << 16) 282 283 #define COMMAND_FLUSH (0x04 << 23) 284 285 // overlay flip 286 #define COMMAND_OVERLAY_FLIP (0x11 << 23) 287 #define COMMAND_OVERLAY_CONTINUE (0 << 21) 288 #define COMMAND_OVERLAY_ON (1 << 21) 289 #define COMMAND_OVERLAY_OFF (2 << 21) 290 #define OVERLAY_UPDATE_COEFFICIENTS 0x1 291 292 // 2D acceleration 293 #define XY_COMMAND_SOURCE_BLIT 0x54c00006 294 #define XY_COMMAND_COLOR_BLIT 0x54000004 295 #define XY_COMMAND_SETUP_MONO_PATTERN 0x44400007 296 #define XY_COMMAND_SCANLINE_BLIT 0x49400001 297 #define COMMAND_COLOR_BLIT 0x50000003 298 #define COMMAND_BLIT_RGBA 0x00300000 299 300 #define COMMAND_MODE_SOLID_PATTERN 0x80 301 #define COMMAND_MODE_CMAP8 0x00 302 #define COMMAND_MODE_RGB15 0x02 303 #define COMMAND_MODE_RGB16 0x01 304 #define COMMAND_MODE_RGB32 0x03 305 306 // overlay 307 308 #define INTEL_OVERLAY_UPDATE 0x30000 309 #define INTEL_OVERLAY_TEST 0x30004 310 #define INTEL_OVERLAY_STATUS 0x30008 311 #define INTEL_OVERLAY_EXTENDED_STATUS 0x3000c 312 #define INTEL_OVERLAY_GAMMA_5 0x30010 313 #define INTEL_OVERLAY_GAMMA_4 0x30014 314 #define INTEL_OVERLAY_GAMMA_3 0x30018 315 #define INTEL_OVERLAY_GAMMA_2 0x3001c 316 #define INTEL_OVERLAY_GAMMA_1 0x30020 317 #define INTEL_OVERLAY_GAMMA_0 0x30024 318 319 struct overlay_scale { 320 uint32 _reserved0 : 3; 321 uint32 horizontal_scale_fraction : 12; 322 uint32 _reserved1 : 1; 323 uint32 horizontal_downscale_factor : 3; 324 uint32 _reserved2 : 1; 325 uint32 vertical_scale_fraction : 12; 326 }; 327 328 #define OVERLAY_FORMAT_RGB15 0x2 329 #define OVERLAY_FORMAT_RGB16 0x3 330 #define OVERLAY_FORMAT_RGB32 0x1 331 #define OVERLAY_FORMAT_YCbCr422 0x8 332 #define OVERLAY_FORMAT_YCbCr411 0x9 333 #define OVERLAY_FORMAT_YCbCr420 0xc 334 335 #define OVERLAY_MIRROR_NORMAL 0x0 336 #define OVERLAY_MIRROR_HORIZONTAL 0x1 337 #define OVERLAY_MIRROR_VERTICAL 0x2 338 339 // The real overlay registers are written to using an update buffer 340 341 struct overlay_registers { 342 uint32 buffer_rgb0; 343 uint32 buffer_rgb1; 344 uint32 buffer_u0; 345 uint32 buffer_v0; 346 uint32 buffer_u1; 347 uint32 buffer_v1; 348 // (0x18) OSTRIDE - overlay stride 349 uint16 stride_rgb; 350 uint16 stride_uv; 351 // (0x1c) YRGB_VPH - Y/RGB vertical phase 352 uint16 vertical_phase0_rgb; 353 uint16 vertical_phase1_rgb; 354 // (0x20) UV_VPH - UV vertical phase 355 uint16 vertical_phase0_uv; 356 uint16 vertical_phase1_uv; 357 // (0x24) HORZ_PH - horizontal phase 358 uint16 horizontal_phase_rgb; 359 uint16 horizontal_phase_uv; 360 // (0x28) INIT_PHS - initial phase shift 361 uint32 initial_vertical_phase0_shift_rgb0 : 4; 362 uint32 initial_vertical_phase1_shift_rgb0 : 4; 363 uint32 initial_horizontal_phase_shift_rgb0 : 4; 364 uint32 initial_vertical_phase0_shift_uv : 4; 365 uint32 initial_vertical_phase1_shift_uv : 4; 366 uint32 initial_horizontal_phase_shift_uv : 4; 367 uint32 _reserved0 : 8; 368 // (0x2c) DWINPOS - destination window position 369 uint16 window_left; 370 uint16 window_top; 371 // (0x30) DWINSZ - destination window size 372 uint16 window_width; 373 uint16 window_height; 374 // (0x34) SWIDTH - source width 375 uint16 source_width_rgb; 376 uint16 source_width_uv; 377 // (0x38) SWITDHSW - source width in 8 byte steps 378 uint16 source_bytes_per_row_rgb; 379 uint16 source_bytes_per_row_uv; 380 uint16 source_height_rgb; 381 uint16 source_height_uv; 382 overlay_scale scale_rgb; 383 overlay_scale scale_uv; 384 // (0x48) OCLRC0 - overlay color correction 0 385 uint32 brightness_correction : 8; // signed, -128 to 127 386 uint32 _reserved1 : 10; 387 uint32 contrast_correction : 9; // fixed point: 3.6 bits 388 uint32 _reserved2 : 5; 389 // (0x4c) OCLRC1 - overlay color correction 1 390 uint32 saturation_cos_correction : 10; // fixed point: 3.7 bits 391 uint32 _reserved3 : 6; 392 uint32 saturation_sin_correction : 11; // signed fixed point: 3.7 bits 393 uint32 _reserved4 : 5; 394 // (0x50) DCLRKV - destination color key value 395 uint32 color_key_blue : 8; 396 uint32 color_key_green : 8; 397 uint32 color_key_red : 8; 398 uint32 _reserved5 : 8; 399 // (0x54) DCLRKM - destination color key mask 400 uint32 color_key_mask_blue : 8; 401 uint32 color_key_mask_green : 8; 402 uint32 color_key_mask_red : 8; 403 uint32 _reserved6 : 7; 404 uint32 color_key_enabled : 1; 405 // (0x58) SCHRKVH - source chroma key high value 406 uint32 source_chroma_key_high_red : 8; 407 uint32 source_chroma_key_high_blue : 8; 408 uint32 source_chroma_key_high_green : 8; 409 uint32 _reserved7 : 8; 410 // (0x5c) SCHRKVL - source chroma key low value 411 uint32 source_chroma_key_low_red : 8; 412 uint32 source_chroma_key_low_blue : 8; 413 uint32 source_chroma_key_low_green : 8; 414 uint32 _reserved8 : 8; 415 // (0x60) SCHRKEN - source chroma key enable 416 uint32 _reserved9 : 24; 417 uint32 source_chroma_key_red_enabled : 1; 418 uint32 source_chroma_key_blue_enabled : 1; 419 uint32 source_chroma_key_green_enabled : 1; 420 uint32 _reserved10 : 5; 421 // (0x64) OCONFIG - overlay configuration 422 uint32 _reserved11 : 3; 423 uint32 color_control_output_mode : 1; 424 uint32 yuv_to_rgb_bypass : 1; 425 uint32 _reserved12 : 11; 426 uint32 gamma2_enabled : 1; 427 uint32 _reserved13 : 1; 428 uint32 select_pipe : 1; 429 uint32 slot_time : 8; 430 uint32 _reserved14 : 5; 431 // (0x68) OCOMD - overlay command 432 uint32 overlay_enabled : 1; 433 uint32 active_field : 1; 434 uint32 active_buffer : 2; 435 uint32 test_mode : 1; 436 uint32 buffer_field_mode : 1; 437 uint32 _reserved15 : 1; 438 uint32 tv_flip_field_enabled : 1; 439 uint32 _reserved16 : 1; 440 uint32 tv_flip_field_parity : 1; 441 uint32 source_format : 4; 442 uint32 ycbcr422_order : 2; 443 uint32 _reserved18 : 1; 444 uint32 mirroring_mode : 2; 445 uint32 _reserved19 : 13; 446 447 uint32 _reserved20; 448 449 // (0x70) AWINPOS - alpha blend window position 450 uint32 awinpos; 451 // (0x74) AWINSZ - alpha blend window size 452 uint32 awinsz; 453 454 uint32 _reserved21[10]; 455 456 // (0xa0) FASTHSCALE - fast horizontal downscale (strangely enough, 457 // the next two registers switch the usual Y/RGB vs. UV order) 458 uint16 horizontal_scale_uv; 459 uint16 horizontal_scale_rgb; 460 // (0xa4) UVSCALEV - vertical downscale 461 uint16 vertical_scale_uv; 462 uint16 vertical_scale_rgb; 463 464 uint32 _reserved22[86]; 465 466 // (0x200) polyphase filter coefficients 467 uint16 vertical_coefficients_rgb[128]; 468 uint16 horizontal_coefficients_rgb[128]; 469 470 uint32 _reserved23[64]; 471 472 // (0x500) 473 uint16 vertical_coefficients_uv[128]; 474 uint16 horizontal_coefficients_uv[128]; 475 }; 476 477 struct hardware_status { 478 uint32 interrupt_status_register; 479 uint32 _reserved0[3]; 480 void *primary_ring_head_storage; 481 uint32 _reserved1[3]; 482 void *secondary_ring_0_head_storage; 483 void *secondary_ring_1_head_storage; 484 uint32 _reserved2[2]; 485 void *binning_head_storage; 486 uint32 _reserved3[3]; 487 uint32 store[1008]; 488 }; 489 490 #endif /* INTEL_EXTREME_H */ 491