1 /* 2 * Copyright 2006-2008, Haiku, Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Axel Dörfler, axeld@pinc-software.de 7 */ 8 #ifndef INTEL_EXTREME_H 9 #define INTEL_EXTREME_H 10 11 12 #include "lock.h" 13 14 #include <memory_manager.h> 15 16 #include <Accelerant.h> 17 #include <Drivers.h> 18 #include <PCI.h> 19 20 21 #define VENDOR_ID_INTEL 0x8086 22 23 #define INTEL_TYPE_FAMILY_MASK 0x0f 24 #define INTEL_TYPE_GROUP_MASK 0xf0 25 #define INTEL_TYPE_7xx 0x01 26 #define INTEL_TYPE_8xx 0x02 27 #define INTEL_TYPE_9xx 0x04 28 #define INTEL_TYPE_83x 0x10 29 #define INTEL_TYPE_85x 0x20 30 #define INTEL_TYPE_91x 0x10 31 #define INTEL_TYPE_945 0x20 32 #define INTEL_TYPE_965 0x40 33 #define INTEL_TYPE_G33 0x80 34 35 #define DEVICE_NAME "intel_extreme" 36 #define INTEL_ACCELERANT_NAME "intel_extreme.accelerant" 37 38 // info about PLL on graphics card 39 struct pll_info { 40 uint32 reference_frequency; 41 uint32 max_frequency; 42 uint32 min_frequency; 43 uint32 divisor_register; 44 }; 45 46 struct ring_buffer { 47 struct lock lock; 48 uint32 register_base; 49 uint32 handle; 50 uint32 offset; 51 uint32 size; 52 uint32 position; 53 uint32 space_left; 54 uint8 *base; 55 }; 56 57 struct overlay_registers; 58 59 struct intel_shared_info { 60 area_id mode_list_area; // area containing display mode list 61 uint32 mode_count; 62 63 display_mode current_mode; 64 uint32 bytes_per_row; 65 uint32 bits_per_pixel; 66 uint32 dpms_mode; 67 68 area_id registers_area; // area of memory mapped registers 69 uint8 *physical_status_page; 70 uint8 *physical_cursor_memory; 71 area_id graphics_memory_area; 72 uint8 *graphics_memory; 73 uint8 *physical_graphics_memory; 74 uint32 graphics_memory_size; 75 76 uint32 frame_buffer_offset; 77 78 struct lock accelerant_lock; 79 struct lock engine_lock; 80 81 ring_buffer primary_ring_buffer; 82 ring_buffer secondary_ring_buffer; 83 84 int32 overlay_channel_used; 85 bool overlay_active; 86 uint32 overlay_token; 87 uint8* physical_overlay_registers; 88 uint32 overlay_offset; 89 90 bool hardware_cursor_enabled; 91 sem_id vblank_sem; 92 93 uint32 cursor_buffer_offset; 94 uint32 cursor_format; 95 bool cursor_visible; 96 uint16 cursor_hot_x; 97 uint16 cursor_hot_y; 98 99 uint32 device_type; 100 char device_identifier[32]; 101 struct pll_info pll_info; 102 }; 103 104 //----------------- ioctl() interface ---------------- 105 106 // magic code for ioctls 107 #define INTEL_PRIVATE_DATA_MAGIC 'itic' 108 109 // list ioctls 110 enum { 111 INTEL_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1, 112 113 INTEL_GET_DEVICE_NAME, 114 INTEL_ALLOCATE_GRAPHICS_MEMORY, 115 INTEL_FREE_GRAPHICS_MEMORY 116 }; 117 118 // retrieve the area_id of the kernel/accelerant shared info 119 struct intel_get_private_data { 120 uint32 magic; // magic number 121 area_id shared_info_area; 122 }; 123 124 // allocate graphics memory 125 struct intel_allocate_graphics_memory { 126 uint32 magic; 127 uint32 size; 128 uint32 buffer_offset; 129 uint32 handle; 130 }; 131 132 // free graphics memory 133 struct intel_free_graphics_memory { 134 uint32 magic; 135 uint32 handle; 136 }; 137 138 //---------------------------------------------------------- 139 // Register definitions, taken from X driver 140 141 // PCI bridge memory management 142 #define INTEL_GRAPHICS_MEMORY_CONTROL 0x52 143 #define MEMORY_MASK 0x01 144 #define STOLEN_MEMORY_MASK 0x70 145 #define i965_GTT_MASK 0x000e 146 #define G33_GTT_MASK 0x0300 147 148 // models i830 and up 149 #define i830_LOCAL_MEMORY_ONLY 0x10 150 #define i830_STOLEN_512K 0x20 151 #define i830_STOLEN_1M 0x30 152 #define i830_STOLEN_8M 0x40 153 #define i830_FRAME_BUFFER_64M 0x01 154 #define i830_FRAME_BUFFER_128M 0x00 155 156 // models i855 and up 157 #define i855_STOLEN_MEMORY_1M 0x10 158 #define i855_STOLEN_MEMORY_4M 0x20 159 #define i855_STOLEN_MEMORY_8M 0x30 160 #define i855_STOLEN_MEMORY_16M 0x40 161 #define i855_STOLEN_MEMORY_32M 0x50 162 #define i855_STOLEN_MEMORY_48M 0x60 163 #define i855_STOLEN_MEMORY_64M 0x70 164 #define i855_STOLEN_MEMORY_128M 0x80 165 #define i855_STOLEN_MEMORY_256M 0x90 166 167 // graphics page translation table 168 #define INTEL_PAGE_TABLE_CONTROL 0x02020 169 #define INTEL_PAGE_TABLE_ERROR 0x02024 170 #define INTEL_HARDWARE_STATUS_PAGE 0x02080 171 #define i830_GTT_BASE 0x10000 // (- 0x2ffff) 172 #define i830_GTT_SIZE 0x20000 173 #define i965_GTT_BASE 0x80000 // (- 0xfffff) 174 #define i965_GTT_SIZE 0x80000 175 #define i965_GTT_128K (2 << 1) 176 #define i965_GTT_256K (1 << 1) 177 #define i965_GTT_512K (0 << 1) 178 #define G33_GTT_1M (1 << 8) 179 #define G33_GTT_2M (2 << 8) 180 #define GTT_ENTRY_VALID 0x01 181 #define GTT_ENTRY_LOCAL_MEMORY 0x02 182 #define GTT_PAGE_SHIFT 12 183 184 // interrupts 185 #define INTEL_INTERRUPT_ENABLED 0x020a0 186 #define INTEL_INTERRUPT_IDENTITY 0x020a4 187 #define INTEL_INTERRUPT_MASK 0x020a8 188 #define INTEL_INTERRUPT_STATUS 0x020ac 189 #define INTERRUPT_VBLANK (1 << 7) 190 191 // ring buffer 192 #define INTEL_PRIMARY_RING_BUFFER 0x02030 193 #define INTEL_SECONDARY_RING_BUFFER_0 0x02100 194 #define INTEL_SECONDARY_RING_BUFFER_1 0x02110 195 // offsets for the ring buffer base registers above 196 #define RING_BUFFER_TAIL 0x0 197 #define RING_BUFFER_HEAD 0x4 198 #define RING_BUFFER_START 0x8 199 #define RING_BUFFER_CONTROL 0xc 200 #define INTEL_RING_BUFFER_SIZE_MASK 0x000ff800 201 #define INTEL_RING_BUFFER_HEAD_MASK 0x001ffffc 202 #define INTEL_RING_BUFFER_ENABLED 1 203 204 // display A 205 #define INTEL_DISPLAY_A_HTOTAL 0x60000 206 #define INTEL_DISPLAY_A_HBLANK 0x60004 207 #define INTEL_DISPLAY_A_HSYNC 0x60008 208 #define INTEL_DISPLAY_A_VTOTAL 0x6000c 209 #define INTEL_DISPLAY_A_VBLANK 0x60010 210 #define INTEL_DISPLAY_A_VSYNC 0x60014 211 #define INTEL_DISPLAY_A_IMAGE_SIZE 0x6001c 212 213 #define INTEL_DISPLAY_A_CONTROL 0x70180 214 #define INTEL_DISPLAY_A_BASE 0x70184 215 #define INTEL_DISPLAY_A_BYTES_PER_ROW 0x70188 216 #define INTEL_DISPLAY_A_SURFACE 0x7019c // i965 and up only 217 #define DISPLAY_CONTROL_ENABLED (1UL << 31) 218 #define DISPLAY_CONTROL_GAMMA (1UL << 30) 219 #define DISPLAY_CONTROL_COLOR_MASK (0x0fUL << 26) 220 #define DISPLAY_CONTROL_CMAP8 (2UL << 26) 221 #define DISPLAY_CONTROL_RGB15 (4UL << 26) 222 #define DISPLAY_CONTROL_RGB16 (5UL << 26) 223 #define DISPLAY_CONTROL_RGB32 (6UL << 26) 224 225 #define INTEL_VGA_DISPLAY_CONTROL 0x71400 226 #define VGA_DISPLAY_DISABLED (1UL << 31) 227 228 #define INTEL_DISPLAY_A_PALETTE 0x0a000 229 230 #define INTEL_DISPLAY_A_PIPE_CONTROL 0x70008 231 #define DISPLAY_PIPE_ENABLED (1UL << 31) 232 #define INTEL_DISPLAY_A_PIPE_STATUS 0x70024 233 #define DISPLAY_PIPE_VBLANK_ENABLED (1UL << 17) 234 #define DISPLAY_PIPE_VBLANK_STATUS (1UL << 1) 235 236 #define INTEL_DISPLAY_A_PLL 0x06014 237 #define INTEL_DISPLAY_A_PLL_DIVISOR_0 0x06040 238 #define INTEL_DISPLAY_A_PLL_DIVISOR_1 0x06044 239 #define DISPLAY_PLL_ENABLED (1UL << 31) 240 #define DISPLAY_PLL_2X_CLOCK (1UL << 30) 241 #define DISPLAY_PLL_SYNC_LOCK_ENABLED (1UL << 29) 242 #define DISPLAY_PLL_NO_VGA_CONTROL (1UL << 28) 243 #define DISPLAY_PLL_MODE_ANALOG (1UL << 26) 244 #define DISPLAY_PLL_DIVIDE_HIGH (1UL << 24) 245 #define DISPLAY_PLL_DIVIDE_4X (1UL << 23) 246 #define DISPLAY_PLL_POST1_DIVIDE_2 (1UL << 21) 247 #define DISPLAY_PLL_POST1_DIVISOR_MASK 0x001f0000 248 #define DISPLAY_PLL_9xx_POST1_DIVISOR_MASK 0x00ff0000 249 #define DISPLAY_PLL_POST1_DIVISOR_SHIFT 16 250 #define DISPLAY_PLL_DIVISOR_1 (1UL << 8) 251 #define DISPLAY_PLL_N_DIVISOR_MASK 0x001f0000 252 #define DISPLAY_PLL_M1_DIVISOR_MASK 0x00001f00 253 #define DISPLAY_PLL_M2_DIVISOR_MASK 0x0000001f 254 #define DISPLAY_PLL_N_DIVISOR_SHIFT 16 255 #define DISPLAY_PLL_M1_DIVISOR_SHIFT 8 256 #define DISPLAY_PLL_M2_DIVISOR_SHIFT 0 257 #define DISPLAY_PLL_PULSE_PHASE_SHIFT 9 258 259 #define INTEL_DISPLAY_A_ANALOG_PORT 0x61100 260 #define DISPLAY_MONITOR_PORT_ENABLED (1UL << 31) 261 #define DISPLAY_MONITOR_PIPE_B (1UL << 30) 262 #define DISPLAY_MONITOR_VGA_POLARITY (1UL << 15) 263 #define DISPLAY_MONITOR_MODE_MASK (3UL << 10) 264 #define DISPLAY_MONITOR_ON 0 265 #define DISPLAY_MONITOR_SUSPEND (1UL << 10) 266 #define DISPLAY_MONITOR_STAND_BY (2UL << 10) 267 #define DISPLAY_MONITOR_OFF (3UL << 10) 268 #define DISPLAY_MONITOR_POLARITY_MASK (3UL << 3) 269 #define DISPLAY_MONITOR_POSITIVE_HSYNC (1UL << 3) 270 #define DISPLAY_MONITOR_POSITIVE_VSYNC (2UL << 3) 271 272 // display B 273 #define INTEL_DISPLAY_B_DIGITAL_PORT 0x61140 274 #define INTEL_DISPLAY_B_IMAGE_SIZE 0x6101c 275 276 #define INTEL_DISPLAY_B_PIPE_CONTROL 0x71008 277 278 #define INTEL_DISPLAY_B_CONTROL 0x71180 279 #define INTEL_DISPLAY_B_BASE 0x71184 280 #define INTEL_DISPLAY_B_BYTES_PER_ROW 0x71188 281 #define INTEL_DISPLAY_B_SURFACE 0x7119c // i965 and up only 282 283 #define INTEL_DISPLAY_B_PALETTE 0x0a800 284 285 #define INTEL_DISPLAY_A_DIGITAL_PORT 0x61120 286 #define INTEL_DISPLAY_C_DIGITAL 0x61160 287 #define INTEL_DISPLAY_LVDS_PORT 0x61180 288 289 // cursor 290 #define INTEL_CURSOR_CONTROL 0x70080 291 #define INTEL_CURSOR_BASE 0x70084 292 #define INTEL_CURSOR_POSITION 0x70088 293 #define INTEL_CURSOR_PALETTE 0x70090 // (- 0x7009f) 294 #define INTEL_CURSOR_SIZE 0x700a0 295 #define CURSOR_ENABLED (1UL << 31) 296 #define CURSOR_FORMAT_2_COLORS (0UL << 24) 297 #define CURSOR_FORMAT_3_COLORS (1UL << 24) 298 #define CURSOR_FORMAT_4_COLORS (2UL << 24) 299 #define CURSOR_FORMAT_ARGB (4UL << 24) 300 #define CURSOR_FORMAT_XRGB (5UL << 24) 301 #define CURSOR_POSITION_NEGATIVE 0x8000 302 #define CURSOR_POSITION_MASK 0x3fff 303 304 // ring buffer commands 305 306 #define COMMAND_NOOP 0x00 307 #define COMMAND_WAIT_FOR_EVENT (0x03 << 23) 308 #define COMMAND_WAIT_FOR_OVERLAY_FLIP (1 << 16) 309 310 #define COMMAND_FLUSH (0x04 << 23) 311 312 // overlay flip 313 #define COMMAND_OVERLAY_FLIP (0x11 << 23) 314 #define COMMAND_OVERLAY_CONTINUE (0 << 21) 315 #define COMMAND_OVERLAY_ON (1 << 21) 316 #define COMMAND_OVERLAY_OFF (2 << 21) 317 #define OVERLAY_UPDATE_COEFFICIENTS 0x1 318 319 // 2D acceleration 320 #define XY_COMMAND_SOURCE_BLIT 0x54c00006 321 #define XY_COMMAND_COLOR_BLIT 0x54000004 322 #define XY_COMMAND_SETUP_MONO_PATTERN 0x44400007 323 #define XY_COMMAND_SCANLINE_BLIT 0x49400001 324 #define COMMAND_COLOR_BLIT 0x50000003 325 #define COMMAND_BLIT_RGBA 0x00300000 326 327 #define COMMAND_MODE_SOLID_PATTERN 0x80 328 #define COMMAND_MODE_CMAP8 0x00 329 #define COMMAND_MODE_RGB15 0x02 330 #define COMMAND_MODE_RGB16 0x01 331 #define COMMAND_MODE_RGB32 0x03 332 333 // i2c 334 335 #define INTEL_I2C_IO_A 0x5010 336 #define INTEL_I2C_IO_B 0x5014 337 #define INTEL_I2C_IO_C 0x5018 338 #define INTEL_I2C_IO_D 0x501c 339 #define INTEL_I2C_IO_E 0x5020 340 #define INTEL_I2C_IO_F 0x5024 341 #define INTEL_I2C_IO_G 0x5028 342 #define INTEL_I2C_IO_H 0x502c 343 344 #define I2C_CLOCK_DIRECTION_MASK (1 << 0) 345 #define I2C_CLOCK_DIRECTION_OUT (1 << 1) 346 #define I2C_CLOCK_VALUE_MASK (1 << 2) 347 #define I2C_CLOCK_VALUE_OUT (1 << 3) 348 #define I2C_CLOCK_VALUE_IN (1 << 4) 349 #define I2C_DATA_DIRECTION_MASK (1 << 8) 350 #define I2C_DATA_DIRECTION_OUT (1 << 9) 351 #define I2C_DATA_VALUE_MASK (1 << 10) 352 #define I2C_DATA_VALUE_OUT (1 << 11) 353 #define I2C_DATA_VALUE_IN (1 << 12) 354 #define I2C_RESERVED ((1 << 13) | (1 << 5)) 355 356 // overlay 357 358 #define INTEL_OVERLAY_UPDATE 0x30000 359 #define INTEL_OVERLAY_TEST 0x30004 360 #define INTEL_OVERLAY_STATUS 0x30008 361 #define INTEL_OVERLAY_EXTENDED_STATUS 0x3000c 362 #define INTEL_OVERLAY_GAMMA_5 0x30010 363 #define INTEL_OVERLAY_GAMMA_4 0x30014 364 #define INTEL_OVERLAY_GAMMA_3 0x30018 365 #define INTEL_OVERLAY_GAMMA_2 0x3001c 366 #define INTEL_OVERLAY_GAMMA_1 0x30020 367 #define INTEL_OVERLAY_GAMMA_0 0x30024 368 369 struct overlay_scale { 370 uint32 _reserved0 : 3; 371 uint32 horizontal_scale_fraction : 12; 372 uint32 _reserved1 : 1; 373 uint32 horizontal_downscale_factor : 3; 374 uint32 _reserved2 : 1; 375 uint32 vertical_scale_fraction : 12; 376 }; 377 378 #define OVERLAY_FORMAT_RGB15 0x2 379 #define OVERLAY_FORMAT_RGB16 0x3 380 #define OVERLAY_FORMAT_RGB32 0x1 381 #define OVERLAY_FORMAT_YCbCr422 0x8 382 #define OVERLAY_FORMAT_YCbCr411 0x9 383 #define OVERLAY_FORMAT_YCbCr420 0xc 384 385 #define OVERLAY_MIRROR_NORMAL 0x0 386 #define OVERLAY_MIRROR_HORIZONTAL 0x1 387 #define OVERLAY_MIRROR_VERTICAL 0x2 388 389 // The real overlay registers are written to using an update buffer 390 391 struct overlay_registers { 392 uint32 buffer_rgb0; 393 uint32 buffer_rgb1; 394 uint32 buffer_u0; 395 uint32 buffer_v0; 396 uint32 buffer_u1; 397 uint32 buffer_v1; 398 // (0x18) OSTRIDE - overlay stride 399 uint16 stride_rgb; 400 uint16 stride_uv; 401 // (0x1c) YRGB_VPH - Y/RGB vertical phase 402 uint16 vertical_phase0_rgb; 403 uint16 vertical_phase1_rgb; 404 // (0x20) UV_VPH - UV vertical phase 405 uint16 vertical_phase0_uv; 406 uint16 vertical_phase1_uv; 407 // (0x24) HORZ_PH - horizontal phase 408 uint16 horizontal_phase_rgb; 409 uint16 horizontal_phase_uv; 410 // (0x28) INIT_PHS - initial phase shift 411 uint32 initial_vertical_phase0_shift_rgb0 : 4; 412 uint32 initial_vertical_phase1_shift_rgb0 : 4; 413 uint32 initial_horizontal_phase_shift_rgb0 : 4; 414 uint32 initial_vertical_phase0_shift_uv : 4; 415 uint32 initial_vertical_phase1_shift_uv : 4; 416 uint32 initial_horizontal_phase_shift_uv : 4; 417 uint32 _reserved0 : 8; 418 // (0x2c) DWINPOS - destination window position 419 uint16 window_left; 420 uint16 window_top; 421 // (0x30) DWINSZ - destination window size 422 uint16 window_width; 423 uint16 window_height; 424 // (0x34) SWIDTH - source width 425 uint16 source_width_rgb; 426 uint16 source_width_uv; 427 // (0x38) SWITDHSW - source width in 8 byte steps 428 uint16 source_bytes_per_row_rgb; 429 uint16 source_bytes_per_row_uv; 430 uint16 source_height_rgb; 431 uint16 source_height_uv; 432 overlay_scale scale_rgb; 433 overlay_scale scale_uv; 434 // (0x48) OCLRC0 - overlay color correction 0 435 uint32 brightness_correction : 8; // signed, -128 to 127 436 uint32 _reserved1 : 10; 437 uint32 contrast_correction : 9; // fixed point: 3.6 bits 438 uint32 _reserved2 : 5; 439 // (0x4c) OCLRC1 - overlay color correction 1 440 uint32 saturation_cos_correction : 10; // fixed point: 3.7 bits 441 uint32 _reserved3 : 6; 442 uint32 saturation_sin_correction : 11; // signed fixed point: 3.7 bits 443 uint32 _reserved4 : 5; 444 // (0x50) DCLRKV - destination color key value 445 uint32 color_key_blue : 8; 446 uint32 color_key_green : 8; 447 uint32 color_key_red : 8; 448 uint32 _reserved5 : 8; 449 // (0x54) DCLRKM - destination color key mask 450 uint32 color_key_mask_blue : 8; 451 uint32 color_key_mask_green : 8; 452 uint32 color_key_mask_red : 8; 453 uint32 _reserved6 : 7; 454 uint32 color_key_enabled : 1; 455 // (0x58) SCHRKVH - source chroma key high value 456 uint32 source_chroma_key_high_red : 8; 457 uint32 source_chroma_key_high_blue : 8; 458 uint32 source_chroma_key_high_green : 8; 459 uint32 _reserved7 : 8; 460 // (0x5c) SCHRKVL - source chroma key low value 461 uint32 source_chroma_key_low_red : 8; 462 uint32 source_chroma_key_low_blue : 8; 463 uint32 source_chroma_key_low_green : 8; 464 uint32 _reserved8 : 8; 465 // (0x60) SCHRKEN - source chroma key enable 466 uint32 _reserved9 : 24; 467 uint32 source_chroma_key_red_enabled : 1; 468 uint32 source_chroma_key_blue_enabled : 1; 469 uint32 source_chroma_key_green_enabled : 1; 470 uint32 _reserved10 : 5; 471 // (0x64) OCONFIG - overlay configuration 472 uint32 _reserved11 : 3; 473 uint32 color_control_output_mode : 1; 474 uint32 yuv_to_rgb_bypass : 1; 475 uint32 _reserved12 : 11; 476 uint32 gamma2_enabled : 1; 477 uint32 _reserved13 : 1; 478 uint32 select_pipe : 1; 479 uint32 slot_time : 8; 480 uint32 _reserved14 : 5; 481 // (0x68) OCOMD - overlay command 482 uint32 overlay_enabled : 1; 483 uint32 active_field : 1; 484 uint32 active_buffer : 2; 485 uint32 test_mode : 1; 486 uint32 buffer_field_mode : 1; 487 uint32 _reserved15 : 1; 488 uint32 tv_flip_field_enabled : 1; 489 uint32 _reserved16 : 1; 490 uint32 tv_flip_field_parity : 1; 491 uint32 source_format : 4; 492 uint32 ycbcr422_order : 2; 493 uint32 _reserved18 : 1; 494 uint32 mirroring_mode : 2; 495 uint32 _reserved19 : 13; 496 497 uint32 _reserved20; 498 499 uint32 start_0y; 500 uint32 start_1y; 501 uint32 start_0u; 502 uint32 start_0v; 503 uint32 start_1u; 504 uint32 start_1v; 505 uint32 _reserved21[6]; 506 #if 0 507 // (0x70) AWINPOS - alpha blend window position 508 uint32 awinpos; 509 // (0x74) AWINSZ - alpha blend window size 510 uint32 awinsz; 511 512 uint32 _reserved21[10]; 513 #endif 514 515 // (0xa0) FASTHSCALE - fast horizontal downscale (strangely enough, 516 // the next two registers switch the usual Y/RGB vs. UV order) 517 uint16 horizontal_scale_uv; 518 uint16 horizontal_scale_rgb; 519 // (0xa4) UVSCALEV - vertical downscale 520 uint16 vertical_scale_uv; 521 uint16 vertical_scale_rgb; 522 523 uint32 _reserved22[86]; 524 525 // (0x200) polyphase filter coefficients 526 uint16 vertical_coefficients_rgb[128]; 527 uint16 horizontal_coefficients_rgb[128]; 528 529 uint32 _reserved23[64]; 530 531 // (0x500) 532 uint16 vertical_coefficients_uv[128]; 533 uint16 horizontal_coefficients_uv[128]; 534 }; 535 536 // i965 overlay support is currently realized using its 3D hardware 537 #define INTEL_i965_OVERLAY_STATE_SIZE 36864 538 #define INTEL_i965_3D_CONTEXT_SIZE 32768 539 540 struct hardware_status { 541 uint32 interrupt_status_register; 542 uint32 _reserved0[3]; 543 void *primary_ring_head_storage; 544 uint32 _reserved1[3]; 545 void *secondary_ring_0_head_storage; 546 void *secondary_ring_1_head_storage; 547 uint32 _reserved2[2]; 548 void *binning_head_storage; 549 uint32 _reserved3[3]; 550 uint32 store[1008]; 551 }; 552 553 #endif /* INTEL_EXTREME_H */ 554