1 /* 2 * Copyright 2006-2009, Haiku, Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Axel Dörfler, axeld@pinc-software.de 7 */ 8 #ifndef INTEL_EXTREME_H 9 #define INTEL_EXTREME_H 10 11 12 #include "lock.h" 13 14 #include <Accelerant.h> 15 #include <Drivers.h> 16 #include <PCI.h> 17 18 19 #define VENDOR_ID_INTEL 0x8086 20 21 #define INTEL_TYPE_FAMILY_MASK 0x000f0000 22 #define INTEL_TYPE_GROUP_MASK 0x000ffff0 23 #define INTEL_TYPE_MODEL_MASK 0x000fffff 24 // families 25 #define INTEL_TYPE_7xx 0x00010000 26 #define INTEL_TYPE_8xx 0x00020000 27 #define INTEL_TYPE_9xx 0x00040000 28 // groups 29 #define INTEL_TYPE_83x (INTEL_TYPE_8xx | 0x0010) 30 #define INTEL_TYPE_85x (INTEL_TYPE_8xx | 0x0020) 31 #define INTEL_TYPE_91x (INTEL_TYPE_9xx | 0x0040) 32 #define INTEL_TYPE_94x (INTEL_TYPE_9xx | 0x0080) 33 #define INTEL_TYPE_96x (INTEL_TYPE_9xx | 0x0100) 34 #define INTEL_TYPE_Gxx (INTEL_TYPE_9xx | 0x0200) 35 #define INTEL_TYPE_G4x (INTEL_TYPE_9xx | 0x0400) 36 #define INTEL_TYPE_IGD (INTEL_TYPE_9xx | 0x0800) 37 #define INTEL_TYPE_ILK (INTEL_TYPE_9xx | 0x1000) 38 #define INTEL_TYPE_SNB (INTEL_TYPE_9xx | 0x2000) 39 // models 40 #define INTEL_TYPE_SERVER 0x0004 41 #define INTEL_TYPE_MOBILE 0x0008 42 #define INTEL_TYPE_915 (INTEL_TYPE_91x) 43 #define INTEL_TYPE_915M (INTEL_TYPE_91x | INTEL_TYPE_MOBILE) 44 #define INTEL_TYPE_945 (INTEL_TYPE_94x) 45 #define INTEL_TYPE_945M (INTEL_TYPE_94x | INTEL_TYPE_MOBILE) 46 #define INTEL_TYPE_965 (INTEL_TYPE_96x) 47 #define INTEL_TYPE_965M (INTEL_TYPE_96x | INTEL_TYPE_MOBILE) 48 #define INTEL_TYPE_G33 (INTEL_TYPE_Gxx) 49 #define INTEL_TYPE_G45 (INTEL_TYPE_G4x) 50 #define INTEL_TYPE_GM45 (INTEL_TYPE_G4x | INTEL_TYPE_MOBILE) 51 #define INTEL_TYPE_IGDG (INTEL_TYPE_IGD) 52 #define INTEL_TYPE_IGDGM (INTEL_TYPE_IGD | INTEL_TYPE_MOBILE) 53 #define INTEL_TYPE_ILKG (INTEL_TYPE_ILK) 54 #define INTEL_TYPE_ILKGM (INTEL_TYPE_ILK | INTEL_TYPE_MOBILE) 55 #define INTEL_TYPE_SNBG (INTEL_TYPE_SNB) 56 #define INTEL_TYPE_SNBGM (INTEL_TYPE_SNB | INTEL_TYPE_MOBILE) 57 #define INTEL_TYPE_SNBGS (INTEL_TYPE_SNB | INTEL_TYPE_SERVER) 58 59 #define DEVICE_NAME "intel_extreme" 60 #define INTEL_ACCELERANT_NAME "intel_extreme.accelerant" 61 62 // We encode the register block into the value and extract/translate it when 63 // actually accessing. 64 #define REGISTER_BLOCK_COUNT 6 65 #define REGISTER_BLOCK_SHIFT 24 66 #define REGISTER_BLOCK_MASK 0xff000000 67 #define REGISTER_REGISTER_MASK 0x00ffffff 68 #define REGISTER_BLOCK(x) ((x & REGISTER_BLOCK_MASK) >> REGISTER_BLOCK_SHIFT) 69 #define REGISTER_REGISTER(x) (x & REGISTER_REGISTER_MASK) 70 71 #define REGS_FLAT (0 << REGISTER_BLOCK_SHIFT) 72 #define REGS_NORTH_SHARED (1 << REGISTER_BLOCK_SHIFT) 73 #define REGS_NORTH_PIPE_AND_PORT (2 << REGISTER_BLOCK_SHIFT) 74 #define REGS_NORTH_PLANE_CONTROL (3 << REGISTER_BLOCK_SHIFT) 75 #define REGS_SOUTH_SHARED (4 << REGISTER_BLOCK_SHIFT) 76 #define REGS_SOUTH_TRANSCODER_PORT (5 << REGISTER_BLOCK_SHIFT) 77 78 // register blocks for (G)MCH/ICH based platforms 79 #define MCH_SHARED_REGISTER_BASE 0x00000 80 #define MCH_PIPE_AND_PORT_REGISTER_BASE 0x60000 81 #define MCH_PLANE_CONTROL_REGISTER_BASE 0x70000 82 #define ICH_SHARED_REGISTER_BASE 0x00000 83 #define ICH_PORT_REGISTER_BASE 0x60000 84 85 // PCH - Platform Control Hub - Newer hardware moves from a MCH/ICH based setup 86 // to a PCH based one, that means anything that used to communicate via (G)MCH 87 // registers needs to use different ones on PCH based platforms (Ironlake and 88 // up, SandyBridge, etc.). 89 #define PCH_NORTH_SHARED_REGISTER_BASE 0x40000 90 #define PCH_NORTH_PIPE_AND_PORT_REGISTER_BASE 0x60000 91 #define PCH_NORTH_PLANE_CONTROL_REGISTER_BASE 0x70000 92 #define PCH_SOUTH_SHARED_REGISTER_BASE 0xc0000 93 #define PCH_SOUTH_TRANSCODER_AND_PORT_REGISTER_BASE 0xe0000 94 95 96 struct DeviceType { 97 uint32 type; 98 99 DeviceType(int t) 100 { 101 type = t; 102 } 103 104 DeviceType& operator=(int t) 105 { 106 type = t; 107 return *this; 108 } 109 110 bool InFamily(uint32 family) const 111 { 112 return (type & INTEL_TYPE_FAMILY_MASK) == family; 113 } 114 115 bool InGroup(uint32 group) const 116 { 117 return (type & INTEL_TYPE_GROUP_MASK) == group; 118 } 119 120 bool IsModel(uint32 model) const 121 { 122 return (type & INTEL_TYPE_MODEL_MASK) == model; 123 } 124 125 bool HasPlatformControlHub() const 126 { 127 return InGroup(INTEL_TYPE_ILK) || InGroup(INTEL_TYPE_SNB); 128 } 129 }; 130 131 // info about PLL on graphics card 132 struct pll_info { 133 uint32 reference_frequency; 134 uint32 max_frequency; 135 uint32 min_frequency; 136 uint32 divisor_register; 137 }; 138 139 struct ring_buffer { 140 struct lock lock; 141 uint32 register_base; 142 uint32 offset; 143 uint32 size; 144 uint32 position; 145 uint32 space_left; 146 uint8* base; 147 }; 148 149 struct overlay_registers; 150 151 struct intel_shared_info { 152 area_id mode_list_area; // area containing display mode list 153 uint32 mode_count; 154 155 display_mode current_mode; 156 uint32 bytes_per_row; 157 uint32 bits_per_pixel; 158 uint32 dpms_mode; 159 160 area_id registers_area; // area of memory mapped registers 161 uint32 register_blocks[REGISTER_BLOCK_COUNT]; 162 uint8* status_page; 163 phys_addr_t physical_status_page; 164 uint8* graphics_memory; 165 phys_addr_t physical_graphics_memory; 166 uint32 graphics_memory_size; 167 168 addr_t frame_buffer; 169 uint32 frame_buffer_offset; 170 171 struct lock accelerant_lock; 172 struct lock engine_lock; 173 174 ring_buffer primary_ring_buffer; 175 176 int32 overlay_channel_used; 177 bool overlay_active; 178 uint32 overlay_token; 179 phys_addr_t physical_overlay_registers; 180 uint32 overlay_offset; 181 182 bool hardware_cursor_enabled; 183 sem_id vblank_sem; 184 185 uint8* cursor_memory; 186 phys_addr_t physical_cursor_memory; 187 uint32 cursor_buffer_offset; 188 uint32 cursor_format; 189 bool cursor_visible; 190 uint16 cursor_hot_x; 191 uint16 cursor_hot_y; 192 193 DeviceType device_type; 194 char device_identifier[32]; 195 struct pll_info pll_info; 196 }; 197 198 //----------------- ioctl() interface ---------------- 199 200 // magic code for ioctls 201 #define INTEL_PRIVATE_DATA_MAGIC 'itic' 202 203 // list ioctls 204 enum { 205 INTEL_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1, 206 207 INTEL_GET_DEVICE_NAME, 208 INTEL_ALLOCATE_GRAPHICS_MEMORY, 209 INTEL_FREE_GRAPHICS_MEMORY 210 }; 211 212 // retrieve the area_id of the kernel/accelerant shared info 213 struct intel_get_private_data { 214 uint32 magic; // magic number 215 area_id shared_info_area; 216 }; 217 218 // allocate graphics memory 219 struct intel_allocate_graphics_memory { 220 uint32 magic; 221 uint32 size; 222 uint32 alignment; 223 uint32 flags; 224 uint32 buffer_base; 225 }; 226 227 // free graphics memory 228 struct intel_free_graphics_memory { 229 uint32 magic; 230 uint32 buffer_base; 231 }; 232 233 //---------------------------------------------------------- 234 // Register definitions, taken from X driver 235 236 // PCI bridge memory management 237 #define INTEL_GRAPHICS_MEMORY_CONTROL 0x52 238 // GGC - (G)MCH Graphics Control Register 239 #define MEMORY_CONTROL_ENABLED 0x0004 240 #define MEMORY_MASK 0x0001 241 #define STOLEN_MEMORY_MASK 0x00f0 242 #define i965_GTT_MASK 0x000e 243 #define G33_GTT_MASK 0x0300 244 #define G4X_GTT_MASK 0x0f00 // GGMS (GSM Memory Size) mask 245 246 // models i830 and up 247 #define i830_LOCAL_MEMORY_ONLY 0x10 248 #define i830_STOLEN_512K 0x20 249 #define i830_STOLEN_1M 0x30 250 #define i830_STOLEN_8M 0x40 251 #define i830_FRAME_BUFFER_64M 0x01 252 #define i830_FRAME_BUFFER_128M 0x00 253 254 // models i855 and up 255 #define i855_STOLEN_MEMORY_1M 0x10 256 #define i855_STOLEN_MEMORY_4M 0x20 257 #define i855_STOLEN_MEMORY_8M 0x30 258 #define i855_STOLEN_MEMORY_16M 0x40 259 #define i855_STOLEN_MEMORY_32M 0x50 260 #define i855_STOLEN_MEMORY_48M 0x60 261 #define i855_STOLEN_MEMORY_64M 0x70 262 #define i855_STOLEN_MEMORY_128M 0x80 263 #define i855_STOLEN_MEMORY_256M 0x90 264 265 #define G4X_STOLEN_MEMORY_96MB 0xa0 // GMS - Graphics Mode Select 266 #define G4X_STOLEN_MEMORY_160MB 0xb0 267 #define G4X_STOLEN_MEMORY_224MB 0xc0 268 #define G4X_STOLEN_MEMORY_352MB 0xd0 269 270 // SandyBridge (SNB) 271 #define SNB_GRAPHICS_MEMORY_CONTROL 0x50 272 273 #define SNB_STOLEN_MEMORY_MASK 0xf8 274 #define SNB_STOLEN_MEMORY_32MB (1 << 3) 275 #define SNB_STOLEN_MEMORY_64MB (2 << 3) 276 #define SNB_STOLEN_MEMORY_96MB (3 << 3) 277 #define SNB_STOLEN_MEMORY_128MB (4 << 3) 278 #define SNB_STOLEN_MEMORY_160MB (5 << 3) 279 #define SNB_STOLEN_MEMORY_192MB (6 << 3) 280 #define SNB_STOLEN_MEMORY_224MB (7 << 3) 281 #define SNB_STOLEN_MEMORY_256MB (8 << 3) 282 #define SNB_STOLEN_MEMORY_288MB (9 << 3) 283 #define SNB_STOLEN_MEMORY_320MB (10 << 3) 284 #define SNB_STOLEN_MEMORY_352MB (11 << 3) 285 #define SNB_STOLEN_MEMORY_384MB (12 << 3) 286 #define SNB_STOLEN_MEMORY_416MB (13 << 3) 287 #define SNB_STOLEN_MEMORY_448MB (14 << 3) 288 #define SNB_STOLEN_MEMORY_480MB (15 << 3) 289 #define SNB_STOLEN_MEMORY_512MB (16 << 3) 290 291 #define SNB_GTT_SIZE_MASK (3 << 8) 292 #define SNB_GTT_SIZE_NONE (0 << 8) 293 #define SNB_GTT_SIZE_1MB (1 << 8) 294 #define SNB_GTT_SIZE_2MB (2 << 8) 295 296 // graphics page translation table 297 #define INTEL_PAGE_TABLE_CONTROL 0x02020 298 #define PAGE_TABLE_ENABLED 0x00000001 299 #define INTEL_PAGE_TABLE_ERROR 0x02024 300 #define INTEL_HARDWARE_STATUS_PAGE 0x02080 301 #define i915_GTT_BASE 0x1c 302 #define i830_GTT_BASE 0x10000 // (- 0x2ffff) 303 #define i830_GTT_SIZE 0x20000 304 #define i965_GTT_BASE 0x80000 // (- 0xfffff) 305 #define i965_GTT_SIZE 0x80000 306 #define i965_GTT_128K (2 << 1) 307 #define i965_GTT_256K (1 << 1) 308 #define i965_GTT_512K (0 << 1) 309 #define G33_GTT_1M (1 << 8) 310 #define G33_GTT_2M (2 << 8) 311 #define G4X_GTT_NONE 0x000 // GGMS - GSM Memory Size 312 #define G4X_GTT_1M_NO_IVT 0x100 // no Intel Virtualization Tech. 313 #define G4X_GTT_2M_NO_IVT 0x300 314 #define G4X_GTT_2M_IVT 0x900 // with Intel Virt. Tech. 315 #define G4X_GTT_3M_IVT 0xa00 316 #define G4X_GTT_4M_IVT 0xb00 317 318 319 #define GTT_ENTRY_VALID 0x01 320 #define GTT_ENTRY_LOCAL_MEMORY 0x02 321 #define GTT_PAGE_SHIFT 12 322 323 324 // ring buffer 325 #define INTEL_PRIMARY_RING_BUFFER 0x02030 326 #define INTEL_SECONDARY_RING_BUFFER_0 0x02100 327 #define INTEL_SECONDARY_RING_BUFFER_1 0x02110 328 // offsets for the ring buffer base registers above 329 #define RING_BUFFER_TAIL 0x0 330 #define RING_BUFFER_HEAD 0x4 331 #define RING_BUFFER_START 0x8 332 #define RING_BUFFER_CONTROL 0xc 333 #define INTEL_RING_BUFFER_SIZE_MASK 0x001ff000 334 #define INTEL_RING_BUFFER_HEAD_MASK 0x001ffffc 335 #define INTEL_RING_BUFFER_ENABLED 1 336 337 // interrupts 338 #define INTEL_INTERRUPT_ENABLED 0x020a0 339 #define INTEL_INTERRUPT_IDENTITY 0x020a4 340 #define INTEL_INTERRUPT_MASK 0x020a8 341 #define INTEL_INTERRUPT_STATUS 0x020ac 342 #define INTERRUPT_VBLANK_PIPEA (1 << 7) 343 #define INTERRUPT_VBLANK_PIPEB (1 << 5) 344 345 // PCH interrupts 346 #define PCH_INTERRUPT_STATUS 0x44000 347 #define PCH_INTERRUPT_MASK 0x44004 348 #define PCH_INTERRUPT_IDENTITY 0x44008 349 #define PCH_INTERRUPT_ENABLED 0x4400c 350 #define PCH_INTERRUPT_VBLANK_PIPEA (1 << 7) 351 #define PCH_INTERRUPT_VBLANK_PIPEB (1 << 15) 352 353 // display ports 354 #define INTEL_DISPLAY_A_ANALOG_PORT (0x1100 | REGS_SOUTH_TRANSCODER_PORT) 355 #define DISPLAY_MONITOR_PORT_ENABLED (1UL << 31) 356 #define DISPLAY_MONITOR_PIPE_B (1UL << 30) 357 #define DISPLAY_MONITOR_VGA_POLARITY (1UL << 15) 358 #define DISPLAY_MONITOR_MODE_MASK (3UL << 10) 359 #define DISPLAY_MONITOR_ON 0 360 #define DISPLAY_MONITOR_SUSPEND (1UL << 10) 361 #define DISPLAY_MONITOR_STAND_BY (2UL << 10) 362 #define DISPLAY_MONITOR_OFF (3UL << 10) 363 #define DISPLAY_MONITOR_POLARITY_MASK (3UL << 3) 364 #define DISPLAY_MONITOR_POSITIVE_HSYNC (1UL << 3) 365 #define DISPLAY_MONITOR_POSITIVE_VSYNC (2UL << 3) 366 #define INTEL_DISPLAY_A_DIGITAL_PORT (0x1120 | REGS_SOUTH_TRANSCODER_PORT) 367 #define INTEL_DISPLAY_C_DIGITAL (0x1160 | REGS_SOUTH_TRANSCODER_PORT) 368 #define INTEL_DISPLAY_LVDS_PORT (0x1180 | REGS_SOUTH_TRANSCODER_PORT) 369 #define LVDS_POST2_RATE_SLOW 14 // PLL Divisors 370 #define LVDS_POST2_RATE_FAST 7 371 #define LVDS_CLKB_POWER_MASK (3 << 4) 372 #define LVDS_CLKB_POWER_UP (3 << 4) 373 #define LVDS_PORT_EN (1 << 31) 374 #define LVDS_A0A2_CLKA_POWER_UP (3 << 8) 375 #define LVDS_PIPEB_SELECT (1 << 30) 376 #define LVDS_B0B3PAIRS_POWER_UP (3 << 2) 377 #define LVDS_PLL_MODE_LVDS (2 << 26) 378 #define LVDS_18BIT_DITHER (1 << 25) 379 380 // PLL flags 381 #define DISPLAY_PLL_ENABLED (1UL << 31) 382 #define DISPLAY_PLL_2X_CLOCK (1UL << 30) 383 #define DISPLAY_PLL_SYNC_LOCK_ENABLED (1UL << 29) 384 #define DISPLAY_PLL_NO_VGA_CONTROL (1UL << 28) 385 #define DISPLAY_PLL_MODE_ANALOG (1UL << 26) 386 #define DISPLAY_PLL_DIVIDE_HIGH (1UL << 24) 387 #define DISPLAY_PLL_DIVIDE_4X (1UL << 23) 388 #define DISPLAY_PLL_POST1_DIVIDE_2 (1UL << 21) 389 #define DISPLAY_PLL_POST1_DIVISOR_MASK 0x001f0000 390 #define DISPLAY_PLL_9xx_POST1_DIVISOR_MASK 0x00ff0000 391 #define DISPLAY_PLL_IGD_POST1_DIVISOR_MASK 0x00ff8000 392 #define DISPLAY_PLL_POST1_DIVISOR_SHIFT 16 393 #define DISPLAY_PLL_IGD_POST1_DIVISOR_SHIFT 15 394 #define DISPLAY_PLL_DIVISOR_1 (1UL << 8) 395 #define DISPLAY_PLL_N_DIVISOR_MASK 0x001f0000 396 #define DISPLAY_PLL_IGD_N_DIVISOR_MASK 0x00ff0000 397 #define DISPLAY_PLL_M1_DIVISOR_MASK 0x00001f00 398 #define DISPLAY_PLL_M2_DIVISOR_MASK 0x0000001f 399 #define DISPLAY_PLL_IGD_M2_DIVISOR_MASK 0x000000ff 400 #define DISPLAY_PLL_N_DIVISOR_SHIFT 16 401 #define DISPLAY_PLL_M1_DIVISOR_SHIFT 8 402 #define DISPLAY_PLL_M2_DIVISOR_SHIFT 0 403 #define DISPLAY_PLL_PULSE_PHASE_SHIFT 9 404 405 // display 406 #define INTEL_DISPLAY_A_HTOTAL (0x0000 | REGS_SOUTH_TRANSCODER_PORT) 407 #define INTEL_DISPLAY_A_HBLANK (0x0004 | REGS_SOUTH_TRANSCODER_PORT) 408 #define INTEL_DISPLAY_A_HSYNC (0x0008 | REGS_SOUTH_TRANSCODER_PORT) 409 #define INTEL_DISPLAY_A_VTOTAL (0x000c | REGS_SOUTH_TRANSCODER_PORT) 410 #define INTEL_DISPLAY_A_VBLANK (0x0010 | REGS_SOUTH_TRANSCODER_PORT) 411 #define INTEL_DISPLAY_A_VSYNC (0x0014 | REGS_SOUTH_TRANSCODER_PORT) 412 #define INTEL_DISPLAY_B_HTOTAL (0x1000 | REGS_SOUTH_TRANSCODER_PORT) 413 #define INTEL_DISPLAY_B_HBLANK (0x1004 | REGS_SOUTH_TRANSCODER_PORT) 414 #define INTEL_DISPLAY_B_HSYNC (0x1008 | REGS_SOUTH_TRANSCODER_PORT) 415 #define INTEL_DISPLAY_B_VTOTAL (0x100c | REGS_SOUTH_TRANSCODER_PORT) 416 #define INTEL_DISPLAY_B_VBLANK (0x1010 | REGS_SOUTH_TRANSCODER_PORT) 417 #define INTEL_DISPLAY_B_VSYNC (0x1014 | REGS_SOUTH_TRANSCODER_PORT) 418 419 #define INTEL_DISPLAY_A_IMAGE_SIZE (0x001c | REGS_NORTH_PIPE_AND_PORT) 420 #define INTEL_DISPLAY_B_IMAGE_SIZE (0x101c | REGS_NORTH_PIPE_AND_PORT) 421 422 #define INTEL_DISPLAY_B_DIGITAL_PORT (0x1140 | REGS_SOUTH_TRANSCODER_PORT) 423 424 // planes 425 #define INTEL_DISPLAY_A_PIPE_CONTROL (0x0008 | REGS_NORTH_PLANE_CONTROL) 426 #define INTEL_DISPLAY_B_PIPE_CONTROL (0x1008 | REGS_NORTH_PLANE_CONTROL) 427 #define DISPLAY_PIPE_ENABLED (1UL << 31) 428 429 #define INTEL_DISPLAY_A_PIPE_STATUS (0x0024 | REGS_NORTH_PLANE_CONTROL) 430 #define INTEL_DISPLAY_B_PIPE_STATUS (0x1024 | REGS_NORTH_PLANE_CONTROL) 431 #define DISPLAY_PIPE_VBLANK_ENABLED (1UL << 17) 432 #define DISPLAY_PIPE_VBLANK_STATUS (1UL << 1) 433 434 #define INTEL_DISPLAY_A_CONTROL (0x0180 | REGS_NORTH_PLANE_CONTROL) 435 #define INTEL_DISPLAY_A_BASE (0x0184 | REGS_NORTH_PLANE_CONTROL) 436 #define INTEL_DISPLAY_A_BYTES_PER_ROW (0x0188 | REGS_NORTH_PLANE_CONTROL) 437 #define INTEL_DISPLAY_A_POS (0x018c | REGS_NORTH_PLANE_CONTROL) 438 // reserved on A 439 #define INTEL_DISPLAY_A_PIPE_SIZE (0x0190 | REGS_NORTH_PLANE_CONTROL) 440 #define INTEL_DISPLAY_A_SURFACE (0x019c | REGS_NORTH_PLANE_CONTROL) 441 // i965 and up only 442 443 #define INTEL_DISPLAY_B_CONTROL (0x1180 | REGS_NORTH_PLANE_CONTROL) 444 #define INTEL_DISPLAY_B_BASE (0x1184 | REGS_NORTH_PLANE_CONTROL) 445 #define INTEL_DISPLAY_B_BYTES_PER_ROW (0x1188 | REGS_NORTH_PLANE_CONTROL) 446 #define INTEL_DISPLAY_B_POS (0x118c | REGS_NORTH_PLANE_CONTROL) 447 #define INTEL_DISPLAY_B_PIPE_SIZE (0x1190 | REGS_NORTH_PLANE_CONTROL) 448 #define INTEL_DISPLAY_B_SURFACE (0x119c | REGS_NORTH_PLANE_CONTROL) 449 // i965 and up only 450 451 #define DISPLAY_CONTROL_ENABLED (1UL << 31) 452 #define DISPLAY_CONTROL_GAMMA (1UL << 30) 453 #define DISPLAY_CONTROL_COLOR_MASK (0x0fUL << 26) 454 #define DISPLAY_CONTROL_CMAP8 (2UL << 26) 455 #define DISPLAY_CONTROL_RGB15 (4UL << 26) 456 #define DISPLAY_CONTROL_RGB16 (5UL << 26) 457 #define DISPLAY_CONTROL_RGB32 (6UL << 26) 458 459 // cursors 460 #define INTEL_CURSOR_CONTROL (0x0080 | REGS_NORTH_PLANE_CONTROL) 461 #define INTEL_CURSOR_BASE (0x0084 | REGS_NORTH_PLANE_CONTROL) 462 #define INTEL_CURSOR_POSITION (0x0088 | REGS_NORTH_PLANE_CONTROL) 463 #define INTEL_CURSOR_PALETTE (0x0090 | REGS_NORTH_PLANE_CONTROL) 464 // (- 0x009f) 465 #define INTEL_CURSOR_SIZE (0x00a0 | REGS_NORTH_PLANE_CONTROL) 466 #define CURSOR_ENABLED (1UL << 31) 467 #define CURSOR_FORMAT_2_COLORS (0UL << 24) 468 #define CURSOR_FORMAT_3_COLORS (1UL << 24) 469 #define CURSOR_FORMAT_4_COLORS (2UL << 24) 470 #define CURSOR_FORMAT_ARGB (4UL << 24) 471 #define CURSOR_FORMAT_XRGB (5UL << 24) 472 #define CURSOR_POSITION_NEGATIVE 0x8000 473 #define CURSOR_POSITION_MASK 0x3fff 474 475 // palette registers 476 #define INTEL_DISPLAY_A_PALETTE (0xa000 | REGS_NORTH_SHARED) 477 #define INTEL_DISPLAY_B_PALETTE (0xa800 | REGS_NORTH_SHARED) 478 479 // PLL registers 480 #define INTEL_DISPLAY_A_PLL (0x6014 | REGS_SOUTH_SHARED) 481 #define INTEL_DISPLAY_B_PLL (0x6018 | REGS_SOUTH_SHARED) 482 #define INTEL_DISPLAY_A_PLL_MULTIPLIER_DIVISOR \ 483 (0x601c | REGS_SOUTH_SHARED) 484 #define INTEL_DISPLAY_B_PLL_MULTIPLIER_DIVISOR \ 485 (0x6020 | REGS_SOUTH_SHARED) 486 #define INTEL_DISPLAY_A_PLL_DIVISOR_0 (0x6040 | REGS_SOUTH_SHARED) 487 #define INTEL_DISPLAY_A_PLL_DIVISOR_1 (0x6044 | REGS_SOUTH_SHARED) 488 #define INTEL_DISPLAY_B_PLL_DIVISOR_0 (0x6048 | REGS_SOUTH_SHARED) 489 #define INTEL_DISPLAY_B_PLL_DIVISOR_1 (0x604c | REGS_SOUTH_SHARED) 490 491 // i2c 492 #define INTEL_I2C_IO_A (0x5010 | REGS_SOUTH_SHARED) 493 #define INTEL_I2C_IO_B (0x5014 | REGS_SOUTH_SHARED) 494 #define INTEL_I2C_IO_C (0x5018 | REGS_SOUTH_SHARED) 495 #define INTEL_I2C_IO_D (0x501c | REGS_SOUTH_SHARED) 496 #define INTEL_I2C_IO_E (0x5020 | REGS_SOUTH_SHARED) 497 #define INTEL_I2C_IO_F (0x5024 | REGS_SOUTH_SHARED) 498 #define INTEL_I2C_IO_G (0x5028 | REGS_SOUTH_SHARED) 499 #define INTEL_I2C_IO_H (0x502c | REGS_SOUTH_SHARED) 500 501 #define I2C_CLOCK_DIRECTION_MASK (1 << 0) 502 #define I2C_CLOCK_DIRECTION_OUT (1 << 1) 503 #define I2C_CLOCK_VALUE_MASK (1 << 2) 504 #define I2C_CLOCK_VALUE_OUT (1 << 3) 505 #define I2C_CLOCK_VALUE_IN (1 << 4) 506 #define I2C_DATA_DIRECTION_MASK (1 << 8) 507 #define I2C_DATA_DIRECTION_OUT (1 << 9) 508 #define I2C_DATA_VALUE_MASK (1 << 10) 509 #define I2C_DATA_VALUE_OUT (1 << 11) 510 #define I2C_DATA_VALUE_IN (1 << 12) 511 #define I2C_RESERVED ((1 << 13) | (1 << 5)) 512 513 // TODO: on IronLake this is in the north shared block at 0x41000 514 #define INTEL_VGA_DISPLAY_CONTROL 0x71400 515 #define VGA_DISPLAY_DISABLED (1UL << 31) 516 517 // LVDS panel 518 #define INTEL_PANEL_STATUS 0x61200 519 #define PANEL_STATUS_POWER_ON (1UL << 31) 520 #define INTEL_PANEL_CONTROL 0x61204 521 #define PANEL_CONTROL_POWER_TARGET_ON (1UL << 0) 522 #define INTEL_PANEL_FIT_CONTROL 0x61230 523 #define INTEL_PANEL_FIT_RATIOS 0x61234 524 525 // LVDS on IronLake and up 526 #define PCH_PANEL_CONTROL 0xc7200 527 #define PCH_PANEL_STATUS 0xc7204 528 #define PANEL_REGISTER_UNLOCK (0xabcd << 16) 529 #define PCH_LVDS_DETECTED (1 << 1) 530 531 532 // ring buffer commands 533 534 #define COMMAND_NOOP 0x00 535 #define COMMAND_WAIT_FOR_EVENT (0x03 << 23) 536 #define COMMAND_WAIT_FOR_OVERLAY_FLIP (1 << 16) 537 538 #define COMMAND_FLUSH (0x04 << 23) 539 540 // overlay flip 541 #define COMMAND_OVERLAY_FLIP (0x11 << 23) 542 #define COMMAND_OVERLAY_CONTINUE (0 << 21) 543 #define COMMAND_OVERLAY_ON (1 << 21) 544 #define COMMAND_OVERLAY_OFF (2 << 21) 545 #define OVERLAY_UPDATE_COEFFICIENTS 0x1 546 547 // 2D acceleration 548 #define XY_COMMAND_SOURCE_BLIT 0x54c00006 549 #define XY_COMMAND_COLOR_BLIT 0x54000004 550 #define XY_COMMAND_SETUP_MONO_PATTERN 0x44400007 551 #define XY_COMMAND_SCANLINE_BLIT 0x49400001 552 #define COMMAND_COLOR_BLIT 0x50000003 553 #define COMMAND_BLIT_RGBA 0x00300000 554 555 #define COMMAND_MODE_SOLID_PATTERN 0x80 556 #define COMMAND_MODE_CMAP8 0x00 557 #define COMMAND_MODE_RGB15 0x02 558 #define COMMAND_MODE_RGB16 0x01 559 #define COMMAND_MODE_RGB32 0x03 560 561 // overlay 562 #define INTEL_OVERLAY_UPDATE 0x30000 563 #define INTEL_OVERLAY_TEST 0x30004 564 #define INTEL_OVERLAY_STATUS 0x30008 565 #define INTEL_OVERLAY_EXTENDED_STATUS 0x3000c 566 #define INTEL_OVERLAY_GAMMA_5 0x30010 567 #define INTEL_OVERLAY_GAMMA_4 0x30014 568 #define INTEL_OVERLAY_GAMMA_3 0x30018 569 #define INTEL_OVERLAY_GAMMA_2 0x3001c 570 #define INTEL_OVERLAY_GAMMA_1 0x30020 571 #define INTEL_OVERLAY_GAMMA_0 0x30024 572 573 struct overlay_scale { 574 uint32 _reserved0 : 3; 575 uint32 horizontal_scale_fraction : 12; 576 uint32 _reserved1 : 1; 577 uint32 horizontal_downscale_factor : 3; 578 uint32 _reserved2 : 1; 579 uint32 vertical_scale_fraction : 12; 580 }; 581 582 #define OVERLAY_FORMAT_RGB15 0x2 583 #define OVERLAY_FORMAT_RGB16 0x3 584 #define OVERLAY_FORMAT_RGB32 0x1 585 #define OVERLAY_FORMAT_YCbCr422 0x8 586 #define OVERLAY_FORMAT_YCbCr411 0x9 587 #define OVERLAY_FORMAT_YCbCr420 0xc 588 589 #define OVERLAY_MIRROR_NORMAL 0x0 590 #define OVERLAY_MIRROR_HORIZONTAL 0x1 591 #define OVERLAY_MIRROR_VERTICAL 0x2 592 593 // The real overlay registers are written to using an update buffer 594 595 struct overlay_registers { 596 uint32 buffer_rgb0; 597 uint32 buffer_rgb1; 598 uint32 buffer_u0; 599 uint32 buffer_v0; 600 uint32 buffer_u1; 601 uint32 buffer_v1; 602 // (0x18) OSTRIDE - overlay stride 603 uint16 stride_rgb; 604 uint16 stride_uv; 605 // (0x1c) YRGB_VPH - Y/RGB vertical phase 606 uint16 vertical_phase0_rgb; 607 uint16 vertical_phase1_rgb; 608 // (0x20) UV_VPH - UV vertical phase 609 uint16 vertical_phase0_uv; 610 uint16 vertical_phase1_uv; 611 // (0x24) HORZ_PH - horizontal phase 612 uint16 horizontal_phase_rgb; 613 uint16 horizontal_phase_uv; 614 // (0x28) INIT_PHS - initial phase shift 615 uint32 initial_vertical_phase0_shift_rgb0 : 4; 616 uint32 initial_vertical_phase1_shift_rgb0 : 4; 617 uint32 initial_horizontal_phase_shift_rgb0 : 4; 618 uint32 initial_vertical_phase0_shift_uv : 4; 619 uint32 initial_vertical_phase1_shift_uv : 4; 620 uint32 initial_horizontal_phase_shift_uv : 4; 621 uint32 _reserved0 : 8; 622 // (0x2c) DWINPOS - destination window position 623 uint16 window_left; 624 uint16 window_top; 625 // (0x30) DWINSZ - destination window size 626 uint16 window_width; 627 uint16 window_height; 628 // (0x34) SWIDTH - source width 629 uint16 source_width_rgb; 630 uint16 source_width_uv; 631 // (0x38) SWITDHSW - source width in 8 byte steps 632 uint16 source_bytes_per_row_rgb; 633 uint16 source_bytes_per_row_uv; 634 uint16 source_height_rgb; 635 uint16 source_height_uv; 636 overlay_scale scale_rgb; 637 overlay_scale scale_uv; 638 // (0x48) OCLRC0 - overlay color correction 0 639 uint32 brightness_correction : 8; // signed, -128 to 127 640 uint32 _reserved1 : 10; 641 uint32 contrast_correction : 9; // fixed point: 3.6 bits 642 uint32 _reserved2 : 5; 643 // (0x4c) OCLRC1 - overlay color correction 1 644 uint32 saturation_cos_correction : 10; // fixed point: 3.7 bits 645 uint32 _reserved3 : 6; 646 uint32 saturation_sin_correction : 11; // signed fixed point: 3.7 bits 647 uint32 _reserved4 : 5; 648 // (0x50) DCLRKV - destination color key value 649 uint32 color_key_blue : 8; 650 uint32 color_key_green : 8; 651 uint32 color_key_red : 8; 652 uint32 _reserved5 : 8; 653 // (0x54) DCLRKM - destination color key mask 654 uint32 color_key_mask_blue : 8; 655 uint32 color_key_mask_green : 8; 656 uint32 color_key_mask_red : 8; 657 uint32 _reserved6 : 7; 658 uint32 color_key_enabled : 1; 659 // (0x58) SCHRKVH - source chroma key high value 660 uint32 source_chroma_key_high_red : 8; 661 uint32 source_chroma_key_high_blue : 8; 662 uint32 source_chroma_key_high_green : 8; 663 uint32 _reserved7 : 8; 664 // (0x5c) SCHRKVL - source chroma key low value 665 uint32 source_chroma_key_low_red : 8; 666 uint32 source_chroma_key_low_blue : 8; 667 uint32 source_chroma_key_low_green : 8; 668 uint32 _reserved8 : 8; 669 // (0x60) SCHRKEN - source chroma key enable 670 uint32 _reserved9 : 24; 671 uint32 source_chroma_key_red_enabled : 1; 672 uint32 source_chroma_key_blue_enabled : 1; 673 uint32 source_chroma_key_green_enabled : 1; 674 uint32 _reserved10 : 5; 675 // (0x64) OCONFIG - overlay configuration 676 uint32 _reserved11 : 3; 677 uint32 color_control_output_mode : 1; 678 uint32 yuv_to_rgb_bypass : 1; 679 uint32 _reserved12 : 11; 680 uint32 gamma2_enabled : 1; 681 uint32 _reserved13 : 1; 682 uint32 select_pipe : 1; 683 uint32 slot_time : 8; 684 uint32 _reserved14 : 5; 685 // (0x68) OCOMD - overlay command 686 uint32 overlay_enabled : 1; 687 uint32 active_field : 1; 688 uint32 active_buffer : 2; 689 uint32 test_mode : 1; 690 uint32 buffer_field_mode : 1; 691 uint32 _reserved15 : 1; 692 uint32 tv_flip_field_enabled : 1; 693 uint32 _reserved16 : 1; 694 uint32 tv_flip_field_parity : 1; 695 uint32 source_format : 4; 696 uint32 ycbcr422_order : 2; 697 uint32 _reserved18 : 1; 698 uint32 mirroring_mode : 2; 699 uint32 _reserved19 : 13; 700 701 uint32 _reserved20; 702 703 uint32 start_0y; 704 uint32 start_1y; 705 uint32 start_0u; 706 uint32 start_0v; 707 uint32 start_1u; 708 uint32 start_1v; 709 uint32 _reserved21[6]; 710 #if 0 711 // (0x70) AWINPOS - alpha blend window position 712 uint32 awinpos; 713 // (0x74) AWINSZ - alpha blend window size 714 uint32 awinsz; 715 716 uint32 _reserved21[10]; 717 #endif 718 719 // (0xa0) FASTHSCALE - fast horizontal downscale (strangely enough, 720 // the next two registers switch the usual Y/RGB vs. UV order) 721 uint16 horizontal_scale_uv; 722 uint16 horizontal_scale_rgb; 723 // (0xa4) UVSCALEV - vertical downscale 724 uint16 vertical_scale_uv; 725 uint16 vertical_scale_rgb; 726 727 uint32 _reserved22[86]; 728 729 // (0x200) polyphase filter coefficients 730 uint16 vertical_coefficients_rgb[128]; 731 uint16 horizontal_coefficients_rgb[128]; 732 733 uint32 _reserved23[64]; 734 735 // (0x500) 736 uint16 vertical_coefficients_uv[128]; 737 uint16 horizontal_coefficients_uv[128]; 738 }; 739 740 // i965 overlay support is currently realized using its 3D hardware 741 #define INTEL_i965_OVERLAY_STATE_SIZE 36864 742 #define INTEL_i965_3D_CONTEXT_SIZE 32768 743 744 inline bool 745 intel_uses_physical_overlay(intel_shared_info &info) 746 { 747 return !info.device_type.InGroup(INTEL_TYPE_Gxx); 748 } 749 750 751 struct hardware_status { 752 uint32 interrupt_status_register; 753 uint32 _reserved0[3]; 754 void* primary_ring_head_storage; 755 uint32 _reserved1[3]; 756 void* secondary_ring_0_head_storage; 757 void* secondary_ring_1_head_storage; 758 uint32 _reserved2[2]; 759 void* binning_head_storage; 760 uint32 _reserved3[3]; 761 uint32 store[1008]; 762 }; 763 764 #endif /* INTEL_EXTREME_H */ 765