1 /* 2 Copyright (c) 2003, Thomas Kurschel 3 4 5 Part of DDC driver 6 7 EDID handling, including decoded EDID data block definitin. 8 */ 9 10 #ifndef _EDID_H 11 #define _EDID_H 12 13 #include "edid_raw.h" 14 15 // vendor info 16 typedef struct { 17 char manufacturer[4]; 18 uint16 prod_id; 19 uint32 serial; 20 uint8 week; 21 uint16 year; 22 } edid1_vendor; 23 24 25 // version info 26 typedef struct { 27 uint8 version; 28 uint8 revision; 29 } edid1_version; 30 31 32 // display info 33 typedef struct { 34 BBITFIELD8_7 ( 35 input_type : 1, // 1 : digital 36 input_voltage : 2, // 0=0.7V/0.3V, 1=0.714V/0.286, 37 // 2=1V/0.4V, 3=0.7V/0V 38 setup : 1, // true if voltage configurable 39 sep_sync : 1, 40 comp_sync : 1, 41 sync_on_green : 1, 42 sync_serr : 1 43 ); 44 uint8 h_size; 45 uint8 v_size; 46 uint8 gamma; // (x+100)/100 47 BBITFIELD8_7 ( 48 dpms_standby : 1, 49 dpms_suspend : 1, 50 dpms_off : 1, 51 display_type : 2, // 0=mono, 1=rgb, 2=multicolour 52 // since EDID version 1.1 53 std_colour_space : 1, 54 preferred_timing_mode : 1, 55 gtf_supported : 1 56 ); 57 uint16 red_x; // all colours are 0.10 fixed point 58 uint16 red_y; 59 uint16 green_x; 60 uint16 green_y; 61 uint16 blue_x; 62 uint16 blue_y; 63 uint16 white_x; 64 uint16 white_y; 65 } edid1_display; 66 67 68 // standard timing data 69 typedef struct { 70 uint16 h_size; 71 uint16 v_size; 72 uint16 id; 73 uint8 ratio; 74 uint8 refresh; 75 } edid1_std_timing; 76 77 78 // additional whitepoint 79 typedef struct { 80 uint8 index; 81 uint16 white_x; 82 uint16 white_y; 83 uint8 gamma; // (x+100)/100 84 } edid1_whitepoint; 85 86 87 // detailed timing description 88 typedef struct { 89 uint16 pixel_clock; // in 10 kHz 90 uint16 h_active; 91 uint16 h_blank; 92 uint16 v_active; 93 uint16 v_blank; 94 uint16 h_sync_off; 95 uint16 h_sync_width; 96 uint16 v_sync_off; 97 uint16 v_sync_width; 98 uint16 h_size; 99 uint16 v_size; 100 uint16 h_border; 101 uint16 v_border; 102 BBITFIELD8_4 ( 103 interlaced : 1, 104 stereo : 2, // upper bit set - left on sync 105 // lower bit set - right on sync 106 sync : 2, 107 misc : 2 108 ); 109 } edid1_detailed_timing; 110 111 112 // detailed monitor description 113 typedef struct { 114 uint8 monitor_desc_type; 115 union { 116 char serial_number[EDID1_EXTRA_STRING_LEN]; 117 char ascii_data[EDID1_EXTRA_STRING_LEN]; 118 edid1_monitor_range monitor_range; 119 char monitor_name[EDID1_EXTRA_STRING_LEN]; 120 edid1_whitepoint whitepoint[EDID1_NUM_EXTRA_WHITEPOINTS]; 121 edid1_std_timing std_timing[EDID1_NUM_EXTRA_STD_TIMING]; 122 edid1_detailed_timing detailed_timing; 123 } data; 124 } edid1_detailed_monitor; 125 126 127 // EDID data block 128 typedef struct{ 129 edid1_vendor vendor; 130 edid1_version version; 131 edid1_display display; 132 edid1_established_timing established_timing; 133 edid1_std_timing std_timing[EDID1_NUM_STD_TIMING]; 134 135 // since EDID version 1.2 136 edid1_detailed_monitor detailed_monitor[EDID1_NUM_DETAILED_MONITOR_DESC]; 137 138 uint8 num_sections; 139 } edid1_info; 140 141 // decode raw EDID info into usuable EDID info 142 void edid_decode( edid1_info *edid, const edid1_raw *raw ); 143 // dump EDID info to syslog 144 void edid_dump( edid1_info *edid ); 145 146 #endif 147