1 /* 2 * Copyright 2012-2016 Haiku, Inc. All rights reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Alexander von Gluck, kallisti5@unixzen.com 7 */ 8 #ifndef _DP_RAW_H 9 #define _DP_RAW_H 10 11 12 /* ****************************************************** */ 13 /* *** AUX Channel Communications *** */ 14 // Native AUX Communications 15 #define DP_AUX_NATIVE_WRITE 0x8 16 #define DP_AUX_NATIVE_READ 0x9 17 #define DP_AUX_NATIVE_REPLY_ACK (0x0 << 0) 18 #define DP_AUX_NATIVE_REPLY_NACK (0x1 << 0) 19 #define DP_AUX_NATIVE_REPLY_DEFER (0x2 << 0) 20 #define DP_AUX_NATIVE_REPLY_MASK (0x3 << 0) 21 // AUX i2c Communications 22 #define DP_AUX_I2C_WRITE 0x0 23 #define DP_AUX_I2C_READ 0x1 24 #define DP_AUX_I2C_WRITE_STATUS_UPDATE 0x2 25 #define DP_AUX_I2C_MOT 0x4 26 #define DP_AUX_I2C_REPLY_ACK (0x0 << 2) 27 #define DP_AUX_I2C_REPLY_NACK (0x1 << 2) 28 #define DP_AUX_I2C_REPLY_DEFER (0x2 << 2) 29 #define DP_AUX_I2C_REPLY_MASK (0x3 << 2) 30 31 32 /* ****************************************************** */ 33 /* *** DPCD (DisplayPort Configuration Data) *** */ 34 /* *** Read / Written over DisplayPort AUX link *** */ 35 36 /* *** DPCD Receiver Compatibility Field (0x0000) *** */ 37 /* *** VESA DisplayPort Standard, rev 1.1, p112 *** */ 38 // DPCD Version (0x0) 39 #define DP_DPCD_SIZE 0xf // Size 40 #define DP_DPCD_REV 0x0000 // Reg 41 #define DP_DPCD_REV_MINOR_MASK (15 << 0) // Int 42 #define DP_DPCD_REV_MAJOR_MASK (15 << 4) // Int 43 #define DP_DPCD_REV_10 0x0010 // Value 44 #define DP_DPCD_REV_11 0x0011 // Value 45 #define DP_DPCD_REV_12 0x0012 // Value 46 // DP Maximum Link Rate (0x1) 47 #define DP_MAX_LINK_RATE 0x0001 // Reg 48 // Use DP_LINK_RATE_* for speed. 49 // DP Maximum Lane Count (0x2) 50 #define DP_MAX_LANE_COUNT 0x0002 // Reg 51 #define DP_MAX_LANE_COUNT_MASK (31 << 0) // Count 52 #define DP_MAX_LANE_COUNT_1 (1 << 0) // Value 53 #define DP_MAX_LANE_COUNT_2 (2 << 0) // Value 54 #define DP_MAX_LANE_COUNT_4 (4 << 0) // Value 55 #define DP_ENHANCED_FRAME_CAP_EN (1 << 7) // Bool, Rev 1.1 56 // DP Maximum Downspread (0x3) 57 #define DP_MAX_DOWNSPREAD 0x0003 // Reg 58 #define DP_MAX_DOWNSPREAD_EN (1 << 0) // Bool 59 #define DP_MAX_DOWNSPREAD_REQ_NO_HANDSHAKE (1 << 6) // Bool 60 // DP Number of Receiver Ports (0x4) 61 #define DP_NORP 0x0004 // Reg 62 #define DP_NORP_MASK (1 << 0) // Count 63 // DP Downstream Port Present (0x5) 64 #define DP_DOWNSTREAMPORT 0x0005 // Reg 65 #define DP_DOWNSTREAMPORT_EN (1 << 0) // Bool 66 #define DP_DOWNSTREAMPORT_TYPE_MASK (3 << 1) // Mask 67 #define DP_DOWNSTREAMPORT_TYPE_DP (0 << 1) // Value 68 #define DP_DOWNSTREAMPORT_TYPE_ANALOG (1 << 1) // Value 69 #define DP_DOWNSTREAMPORT_TYPE_DIGITAL (2 << 1) // Value 70 #define DP_DOWNSTREAMPORT_TYPE_OTHER (3 << 1) // Value 71 #define DP_DOWNSTREAMPORT_FORMAT_EN (1 << 3) // Bool 72 // DP Main Link Channel Coding (0x6) 73 #define DP_CURR_MAIN_CHAN_CODE 0x0006 // Reg 74 #define DP_CURR_MAIN_CHAN_CODE_ANSIX3_EN (1 << 0) // Bool 75 // DP Downstream Port Count (0x7) (Only 1.1+) 76 #define DP_DOWNSTREAMPORT_COUNT 0x0007 // Reg 77 #define DP_DOWNSTREAMPORT_COUNT_MASK (15 << 0) // Count 78 #define DP_DOWNSTREAMPORT_COUNT_OUI_EN (1 << 7) // Bool 79 // DP Port Capability 0 80 #define DP_PORT0_CAPABILITY0 0x0008 // Reg 81 #define DP_PORT1_CAPABILITY0 0x000A // Reg 82 #define DP_PORT_CAPABILITY0_EDID_EN (1 << 1) // Bool 83 #define DP_PORT_CAPABILITY0_SECOND_EN (1 << 2) // Bool 84 // DP Port Capability 1 85 #define DP_PORT0_CAPABILITY1 0x0009 // Reg 86 #define DP_PORT1_CAPABILITY1 0x000B // Reg 87 #define DP_PORT_CAPABILITY1_BUF_SIZE_MASK (255 << 0) // Size 88 // (value + 1) * 32 bytes per lane 89 90 /* *** DPCD Link Configuration Field (0x0100) *** */ 91 /* *** VESA DisplayPort Standard, rev 1.1, p117 *** */ 92 93 // DP Set Link Rate Per Lane (0x0100) 94 #define DP_LINK_RATE 0x0100 // Reg 95 #define DP_LINK_RATE_162 0x0006 // 1.62Ghz 96 #define DP_LINK_RATE_270 0x000A // 2.70Ghz 97 #define DP_LINK_RATE_540 0x0014 // 5.40Ghz 98 // DP Set Lane Count (0x0101) 99 #define DP_LANE_COUNT 0x0101 // Reg 100 #define DP_LANE_COUNT_MASK (31 << 0) // Count 101 #define DP_ENHANCED_FRAME_EN (1 << 7) // Bool, Rev 1.1 102 // DP Training Pattern (0x0102) 103 #define DP_TRAIN 0x0102 // Reg 104 #define DP_TRAIN_PATTERN_MASK (3 << 0) // Mask 105 #define DP_TRAIN_PATTERN_DISABLED (0 << 0) // Value 106 #define DP_TRAIN_PATTERN_1 (1 << 0) // Value 107 #define DP_TRAIN_PATTERN_2 (2 << 0) // Value 108 #define DP_TRAIN_PATTERN_3 (3 << 0) // Value 109 110 #define DP_TRAIN_QUAL_MASK (3 << 2) // Mask 111 #define DP_TRAIN_QUAL_NONE (0 << 2) // Value 112 #define DP_TRAIN_QUAL_D102 (1 << 2) // Value 113 #define DP_TRAIN_QUAL_SYMB_ERR (2 << 2) // Value 114 #define DP_TRAIN_QUAL_PRBS7 (3 << 2) // Value 115 116 #define DP_TRAIN_CLOCK_RECOVER_EN (1 << 4) // Bool 117 #define DP_TRAIN_SCRAMBLE_DI (1 << 5) // Bool (rev) 118 #define DP_TRAIN_SYMBL_ERR_SEL_MASK (3 << 6) // Mask 119 #define DP_TRAIN_SYMBL_ERR_SEL_BOTH (0 << 6) // Value 120 #define DP_TRAIN_SYMBL_ERR_SEL_DISPARITY (1 << 6) // Value 121 #define DP_TRAIN_SYMBL_ERR_SEL_SYMBOL (2 << 6) // Value 122 // DP Training Lane n (0x0103 - 0x0106) 123 #define DP_TRAIN_LANE0 0x0103 // Reg 124 #define DP_TRAIN_LANE1 0x0104 // Reg 125 #define DP_TRAIN_LANE2 0x0105 // Reg 126 #define DP_TRAIN_LANE3 0x0106 // Reg 127 128 #define DP_TRAIN_VCC_SWING_SHIFT (0 << 0) // Shift 129 #define DP_TRAIN_VCC_SWING_MASK (3 << 0) // Mask 130 #define DP_TRAIN_VCC_SWING_400 (0 << 0) // Value 131 #define DP_TRAIN_VCC_SWING_600 (1 << 0) // Value 132 #define DP_TRAIN_VCC_SWING_800 (2 << 0) // Value 133 #define DP_TRAIN_VCC_SWING_1200 (3 << 0) // Value 134 #define DP_TRAIN_MAX_SWING_EN (1 << 2) // Bool 135 136 #define DP_TRAIN_PRE_EMPHASIS_SHIFT (3 << 0) // Shift 137 #define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3) // Mask 138 #define DP_TRAIN_PRE_EMPHASIS_0 (0 << 3) // Value 139 #define DP_TRAIN_PRE_EMPHASIS_3_5 (1 << 3) // Value 140 #define DP_TRAIN_PRE_EMPHASIS_6 (2 << 3) // Value 141 #define DP_TRAIN_PRE_EMPHASIS_9_5 (3 << 3) // Value 142 #define DP_TRAIN_MAX_EMPHASIS_EN (1 << 5) // Bool 143 // DP Down-spread Control (0x0107) 144 #define DP_DOWNSPREAD_CTRL 0x0107 // Reg 145 #define DP_DOWNSPREAD_CTRL_FREQ_MASK (1 << 0) // Int 146 #define DP_DOWNSPREAD_CTRL_AMP_EN (1 << 4) // Int 147 // DP Main Link Channel Coding (0x0108) 148 #define DP_MAIN_CHAN_CODE 0x0108 // Reg 149 #define DP_MAIN_CHAN_CODE_ANSIX3_EN (1 << 0) // Bool 150 151 /* *** DPCD Link / Sink Status Field (0x0200) *** */ 152 /* *** VESA DisplayPort Standard, rev 1.1, p120 *** */ 153 154 // DP Sink Count (0x0200) 155 #define DP_SINK_COUNT 0x0200 // Reg 156 #define DP_SINK_COUNT_MASK (63 << 0) // Mask 157 #define DP_SINK_COUNT_CP_READY (1 << 6) // Bool 158 // DP Service IRQ Vector (0x0201) 159 #define DP_SINK_IRQ_VECTOR 0x0201 // Reg 160 #define DP_SINK_IRQ_TEST_REQ (1 << 1) // Bool 161 #define DP_SINK_IRQ_CP_IRQ (1 << 2) // Bool 162 #define DP_SINK_IRQ_VENDOR (1 << 6) // Bool 163 // DP Lane Status A B 164 #define DP_LANE_STATUS_0_1 0x0202 // Reg 165 #define DP_LANE_STATUS_2_3 0x0203 // Reg 166 #define DP_LINK_STATUS_SIZE 6 // Size 167 #define DP_LANE_STATUS_CR_DONE_A (1 << 0) // Bool 168 #define DP_LANE_STATUS_CHEQ_DONE_A (1 << 1) // Bool 169 #define DP_LANE_STATUS_SYMB_LOCK_A (1 << 2) // Bool 170 #define DP_LANE_STATUS_CR_DONE_B (1 << 4) // Bool 171 #define DP_LANE_STATUS_CHEQ_DONE_B (1 << 5) // Bool 172 #define DP_LANE_STATUS_SYMB_LOCK_B (1 << 6) // Bool 173 #define DP_LANE_STATUS_EQUALIZED_A (DP_LANE_STATUS_CR_DONE_A \ 174 | DP_LANE_STATUS_CHEQ_DONE_A \ 175 | DP_LANE_STATUS_SYMB_LOCK_A) 176 #define DP_LANE_STATUS_EQUALIZED_B (DP_LANE_STATUS_CR_DONE_B \ 177 | DP_LANE_STATUS_CHEQ_DONE_B \ 178 | DP_LANE_STATUS_SYMB_LOCK_B) 179 // DP Lane Align Status (0x0204) 180 #define DP_LANE_ALIGN 0x0204 // Reg 181 #define DP_LANE_ALIGN_DONE (1 << 0) // Bool 182 #define DP_LANE_ALIGN_PORT_STATUS_CHANGE (1 << 6) // Bool 183 #define DP_LANE_ALIGN_LINK_STATUS_UPDATE (1 << 7) // Bool 184 // DP Sink Status (0x0205) 185 #define DP_SINK_STATUS 0x0205 // Reg 186 #define DP_SINK_STATUS_IN_SYNC_0 (1 << 0) // Bool 187 #define DP_SINK_STATUS_IN_SYNC_1 (1 << 1) // Bool 188 // DP Adjust Request A B 189 #define DP_ADJ_REQUEST_0_1 0x0206 // Reg 190 #define DP_ADJ_REQUEST_2_3 0x0207 // Reg 191 #define DP_ADJ_VCC_SWING_LANEA_SHIFT 0 // Shift 192 #define DP_ADJ_VCC_SWING_LANEA_MASK (3 << 0) // Mask 193 #define DP_ADJ_PRE_EMPHASIS_LANEA_SHIFT 2 // Shift 194 #define DP_ADJ_PRE_EMPHASIS_LANEA_MASK (3 << 2) // Mask 195 #define DP_ADJ_VCC_SWING_LANEB_SHIFT 4 // Shift 196 #define DP_ADJ_VCC_SRING_LANEB_MASK (3 << 4) // Mask 197 #define DP_ADJ_PRE_EMPHASIS_LANEB_SHIFT 6 // Shift 198 #define DP_ADJ_PRE_EMPHASIS_LANEB_MASK (3 << 6) // Mask 199 200 // TODO: 0x0210 - 0x0217 201 202 /* *** DPCD Automated Self-testing Field (0x0218) *** */ 203 /* *** VESA DisplayPort Standard, rev 1.1, p123 *** */ 204 205 // TODO: Optional Field 206 207 /* *** DPCD Source Device Specific Field (0x0300) *** */ 208 /* *** VESA DisplayPort Standard, rev 1.1, p127 *** */ 209 210 // TODO 211 212 /* *** DPCD Sink Device Specific Field (0x0400) *** */ 213 /* *** VESA DisplayPort Standard, rev 1.1, p127 *** */ 214 215 // TODO 216 217 /* *** DPCD Branch Device Specific Field (0x0500) *** */ 218 /* *** VESA DisplayPort Standard, rev 1.1, p127 *** */ 219 220 // TODO 221 222 /* *** DPCD Sink Control Field (0x0600) *** */ 223 /* *** VESA DisplayPort Standard, rev 1.1, p128 *** */ 224 225 #define DP_SET_POWER 0x0600 // Reg 226 #define DP_SET_POWER_D0 (1 << 0) // Value 227 #define DP_SET_POWER_D3 (1 << 1) // Value 228 229 /* *** DPCD Reserved (0x0700+) *** */ 230 /* ****************************************************** */ 231 232 233 #endif /* _DP_RAW_H */ 234