14185aa0cSAlexander von Gluck IV /* 24185aa0cSAlexander von Gluck IV * Copyright 2012 Haiku, Inc. All rights reserved. 34185aa0cSAlexander von Gluck IV * Distributed under the terms of the MIT License. 44185aa0cSAlexander von Gluck IV * 54185aa0cSAlexander von Gluck IV * Authors: 64185aa0cSAlexander von Gluck IV * Alexander von Gluck, kallisti5@unixzen.com 74185aa0cSAlexander von Gluck IV */ 84185aa0cSAlexander von Gluck IV #ifndef _DP_RAW_H 94185aa0cSAlexander von Gluck IV #define _DP_RAW_H 104185aa0cSAlexander von Gluck IV 114185aa0cSAlexander von Gluck IV 124185aa0cSAlexander von Gluck IV /* ****************************************************** */ 1337550d80SAlexander von Gluck IV /* *** AUX Channel Communications *** */ 1437550d80SAlexander von Gluck IV // Native AUX Communications 15*c6799d8aSAlexander von Gluck IV #define AUX_NATIVE_WRITE (8 << 0) 16*c6799d8aSAlexander von Gluck IV #define AUX_NATIVE_READ (9 << 0) 17*c6799d8aSAlexander von Gluck IV #define AUX_NATIVE_REPLY_ACK (0 << 4) 18*c6799d8aSAlexander von Gluck IV #define AUX_NATIVE_REPLY_NACK (1 << 4) 19*c6799d8aSAlexander von Gluck IV #define AUX_NATIVE_REPLY_DEFER (2 << 4) 20*c6799d8aSAlexander von Gluck IV #define AUX_NATIVE_REPLY_MASK (3 << 4) 2137550d80SAlexander von Gluck IV // AUX i2c Communications 22*c6799d8aSAlexander von Gluck IV #define AUX_I2C_WRITE (0 << 0) 23*c6799d8aSAlexander von Gluck IV #define AUX_I2C_READ (1 << 0) 24*c6799d8aSAlexander von Gluck IV #define AUX_I2C_STATUS (2 << 0) 25*c6799d8aSAlexander von Gluck IV #define AUX_I2C_MOT (4 << 0) 26*c6799d8aSAlexander von Gluck IV #define AUX_I2C_REPLY_ACK (0 << 6) 27*c6799d8aSAlexander von Gluck IV #define AUX_I2C_REPLY_NACK (1 << 6) 28*c6799d8aSAlexander von Gluck IV #define AUX_I2C_REPLY_DEFER (2 << 6) 29*c6799d8aSAlexander von Gluck IV #define AUX_I2C_REPLY_MASK (3 << 6) 3037550d80SAlexander von Gluck IV 3137550d80SAlexander von Gluck IV 3237550d80SAlexander von Gluck IV /* ****************************************************** */ 334185aa0cSAlexander von Gluck IV /* *** DPCD (DisplayPort Configuration Data) *** */ 344185aa0cSAlexander von Gluck IV /* *** Read / Written over DisplayPort AUX link *** */ 354185aa0cSAlexander von Gluck IV 364185aa0cSAlexander von Gluck IV /* *** DPCD Receiver Compatibility Field (0x0000) *** */ 374185aa0cSAlexander von Gluck IV /* *** VESA DisplayPort Standard, rev 1.1, p112 *** */ 384185aa0cSAlexander von Gluck IV // DPCD Version (0x0) 394185aa0cSAlexander von Gluck IV #define DP_DPCD_REV 0x0000 // Reg 40*c6799d8aSAlexander von Gluck IV #define DP_DPCD_REV_MINOR_MASK (15 << 0) // Int 41*c6799d8aSAlexander von Gluck IV #define DP_DPCD_REV_MAJOR_MASK (15 << 4) // Int 42*c6799d8aSAlexander von Gluck IV #define DP_DPCD_REV_10 0x0010 // Value 43*c6799d8aSAlexander von Gluck IV #define DP_DPCD_REV_11 0x0011 // Value 444185aa0cSAlexander von Gluck IV // DP Maximum Link Rate (0x1) 454185aa0cSAlexander von Gluck IV #define DP_MAX_LINK_RATE 0x0001 // Reg 46*c6799d8aSAlexander von Gluck IV // Use DP_LINK_RATE_* for speed. 474185aa0cSAlexander von Gluck IV // DP Maximum Lane Count (0x2) 484185aa0cSAlexander von Gluck IV #define DP_MAX_LANE_COUNT 0x0002 // Reg 49*c6799d8aSAlexander von Gluck IV #define DP_MAX_LANE_COUNT_MASK (31 << 0) // Count 50*c6799d8aSAlexander von Gluck IV #define DP_MAX_LANE_COUNT_1 (1 << 0) // Value 51*c6799d8aSAlexander von Gluck IV #define DP_MAX_LANE_COUNT_2 (2 << 0) // Value 52*c6799d8aSAlexander von Gluck IV #define DP_MAX_LANE_COUNT_4 (4 << 0) // Value 53*c6799d8aSAlexander von Gluck IV #define DP_ENHANCED_FRAME_CAP_EN (1 << 7) // Bool, Rev 1.1 544185aa0cSAlexander von Gluck IV // DP Maximum Downspread (0x3) 554185aa0cSAlexander von Gluck IV #define DP_MAX_DOWNSPREAD 0x0003 // Reg 56*c6799d8aSAlexander von Gluck IV #define DP_MAX_DOWNSPREAD_EN (1 << 0) // Bool 57*c6799d8aSAlexander von Gluck IV #define DP_MAX_DOWNSPREAD_REQ_NO_HANDSHAKE (1 << 6) // Bool 584185aa0cSAlexander von Gluck IV // DP Number of Receiver Ports (0x4) 594185aa0cSAlexander von Gluck IV #define DP_NORP 0x0004 // Reg 60*c6799d8aSAlexander von Gluck IV #define DP_NORP_MASK (1 << 0) // Count 614185aa0cSAlexander von Gluck IV // DP Downstream Port Present (0x5) 624185aa0cSAlexander von Gluck IV #define DP_DOWNSTREAMPORT 0x0005 // Reg 63*c6799d8aSAlexander von Gluck IV #define DP_DOWNSTREAMPORT_EN (1 << 0) // Bool 64*c6799d8aSAlexander von Gluck IV #define DP_DOWNSTREAMPORT_TYPE_MASK (3 << 1) // Mask 65*c6799d8aSAlexander von Gluck IV #define DP_DOWNSTREAMPORT_TYPE_DP (0 << 1) // Value 66*c6799d8aSAlexander von Gluck IV #define DP_DOWNSTREAMPORT_TYPE_ANALOG (1 << 1) // Value 67*c6799d8aSAlexander von Gluck IV #define DP_DOWNSTREAMPORT_TYPE_DIGITAL (2 << 1) // Value 68*c6799d8aSAlexander von Gluck IV #define DP_DOWNSTREAMPORT_TYPE_OTHER (3 << 1) // Value 69*c6799d8aSAlexander von Gluck IV #define DP_DOWNSTREAMPORT_FORMAT_EN (1 << 3) // Bool 704185aa0cSAlexander von Gluck IV // DP Main Link Channel Coding (0x6) 714185aa0cSAlexander von Gluck IV #define DP_CURR_MAIN_CHAN_CODE 0x0006 // Reg 72*c6799d8aSAlexander von Gluck IV #define DP_CURR_MAIN_CHAN_CODE_ANSIX3_EN (1 << 0) // Bool 734185aa0cSAlexander von Gluck IV // DP Downstream Port Count (0x7) (Only 1.1+) 744185aa0cSAlexander von Gluck IV #define DP_DOWNSTREAMPORT_COUNT 0x0007 // Reg 75*c6799d8aSAlexander von Gluck IV #define DP_DOWNSTREAMPORT_COUNT_MASK (15 << 0) // Count 76*c6799d8aSAlexander von Gluck IV #define DP_DOWNSTREAMPORT_COUNT_OUI_EN (1 << 7) // Bool 774185aa0cSAlexander von Gluck IV // DP Port Capability 0 784185aa0cSAlexander von Gluck IV #define DP_PORT0_CAPABILITY0 0x0008 // Reg 794185aa0cSAlexander von Gluck IV #define DP_PORT1_CAPABILITY0 0x000A // Reg 80*c6799d8aSAlexander von Gluck IV #define DP_PORT_CAPABILITY0_EDID_EN (1 << 1) // Bool 81*c6799d8aSAlexander von Gluck IV #define DP_PORT_CAPABILITY0_SECOND_EN (1 << 2) // Bool 824185aa0cSAlexander von Gluck IV // DP Port Capability 1 834185aa0cSAlexander von Gluck IV #define DP_PORT0_CAPABILITY1 0x0009 // Reg 844185aa0cSAlexander von Gluck IV #define DP_PORT1_CAPABILITY1 0x000B // Reg 85*c6799d8aSAlexander von Gluck IV #define DP_PORT_CAPABILITY1_BUF_SIZE_MASK (255 << 0) // Size 864185aa0cSAlexander von Gluck IV // (value + 1) * 32 bytes per lane 874185aa0cSAlexander von Gluck IV 884185aa0cSAlexander von Gluck IV /* *** DPCD Link Configuration Field (0x0100) *** */ 894185aa0cSAlexander von Gluck IV /* *** VESA DisplayPort Standard, rev 1.1, p117 *** */ 904185aa0cSAlexander von Gluck IV 914185aa0cSAlexander von Gluck IV // DP Set Link Rate Per Lane (0x0100) 924185aa0cSAlexander von Gluck IV #define DP_LINK_RATE 0x0100 // Reg 934185aa0cSAlexander von Gluck IV #define DP_LINK_RATE_162 0x0006 // 1.62Ghz 944185aa0cSAlexander von Gluck IV #define DP_LINK_RATE_270 0x000A // 2.70Ghz 954185aa0cSAlexander von Gluck IV #define DP_LINK_RATE_540 0x0014 // 5.40Ghz 964185aa0cSAlexander von Gluck IV // DP Set Lane Count (0x0101) 974185aa0cSAlexander von Gluck IV #define DP_LANE_COUNT 0x0101 // Reg 98*c6799d8aSAlexander von Gluck IV #define DP_LANE_COUNT_MASK (31 << 0) // Count 99*c6799d8aSAlexander von Gluck IV #define DP_ENHANCED_FRAME_EN (1 << 7) // Bool, Rev 1.1 1004185aa0cSAlexander von Gluck IV // DP Training Pattern (0x0102) 101*c6799d8aSAlexander von Gluck IV #define DP_TRAIN 0x0102 // Reg 102*c6799d8aSAlexander von Gluck IV #define DP_TRAIN_PATTERN_MASK (3 << 0) // Mask 103*c6799d8aSAlexander von Gluck IV #define DP_TRAIN_PATTERN_DISABLED (0 << 0) // Value 104*c6799d8aSAlexander von Gluck IV #define DP_TRAIN_PATTERN_1 (1 << 0) // Value 105*c6799d8aSAlexander von Gluck IV #define DP_TRAIN_PATTERN_2 (2 << 0) // Value 106*c6799d8aSAlexander von Gluck IV #define DP_TRAIN_PATTERN_3 (3 << 0) // Value 107*c6799d8aSAlexander von Gluck IV 108*c6799d8aSAlexander von Gluck IV #define DP_TRAIN_QUAL_MASK (3 << 2) // Mask 109*c6799d8aSAlexander von Gluck IV #define DP_TRAIN_QUAL_NONE (0 << 2) // Value 110*c6799d8aSAlexander von Gluck IV #define DP_TRAIN_QUAL_D102 (1 << 2) // Value 111*c6799d8aSAlexander von Gluck IV #define DP_TRAIN_QUAL_SYMB_ERR (2 << 2) // Value 112*c6799d8aSAlexander von Gluck IV #define DP_TRAIN_QUAL_PRBS7 (3 << 2) // Value 113*c6799d8aSAlexander von Gluck IV 114*c6799d8aSAlexander von Gluck IV #define DP_TRAIN_CLOCK_RECOVER_EN (1 << 4) // Bool 115*c6799d8aSAlexander von Gluck IV #define DP_TRAIN_SCRAMBLE_DI (1 << 5) // Bool (rev) 116*c6799d8aSAlexander von Gluck IV #define DP_TRAIN_SYMBL_ERR_SEL_MASK (3 << 6) // Mask 117*c6799d8aSAlexander von Gluck IV #define DP_TRAIN_SYMBL_ERR_SEL_BOTH (0 << 6) // Value 118*c6799d8aSAlexander von Gluck IV #define DP_TRAIN_SYMBL_ERR_SEL_DISPARITY (1 << 6) // Value 119*c6799d8aSAlexander von Gluck IV #define DP_TRAIN_SYMBL_ERR_SEL_SYMBOL (2 << 6) // Value 1204185aa0cSAlexander von Gluck IV // DP Training Lane n (0x0103 - 0x0106) 121*c6799d8aSAlexander von Gluck IV #define DP_TRAIN_LANE0 0x0103 // Reg 122*c6799d8aSAlexander von Gluck IV #define DP_TRAIN_LANE1 0x0104 // Reg 123*c6799d8aSAlexander von Gluck IV #define DP_TRAIN_LANE2 0x0105 // Reg 124*c6799d8aSAlexander von Gluck IV #define DP_TRAIN_LANE3 0x0106 // Reg 125*c6799d8aSAlexander von Gluck IV 126*c6799d8aSAlexander von Gluck IV #define DP_TRAIN_VCC_SWING_SHIFT (0 << 0) // Shift 127*c6799d8aSAlexander von Gluck IV #define DP_TRAIN_VCC_SWING_MASK (3 << 0) // Mask 128*c6799d8aSAlexander von Gluck IV #define DP_TRAIN_VCC_SWING_400 (0 << 0) // Value 129*c6799d8aSAlexander von Gluck IV #define DP_TRAIN_VCC_SWING_600 (1 << 0) // Value 130*c6799d8aSAlexander von Gluck IV #define DP_TRAIN_VCC_SWING_800 (2 << 0) // Value 131*c6799d8aSAlexander von Gluck IV #define DP_TRAIN_VCC_SWING_1200 (3 << 0) // Value 132*c6799d8aSAlexander von Gluck IV #define DP_TRAIN_MAX_SWING_EN (1 << 2) // Bool 133*c6799d8aSAlexander von Gluck IV 134*c6799d8aSAlexander von Gluck IV #define DP_TRAIN_PRE_EMPHASIS_SHIFT (3 << 0) // Shift 135*c6799d8aSAlexander von Gluck IV #define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3) // Mask 136*c6799d8aSAlexander von Gluck IV #define DP_TRAIN_PRE_EMPHASIS_0 (0 << 3) // Value 137*c6799d8aSAlexander von Gluck IV #define DP_TRAIN_PRE_EMPHASIS_3_5 (1 << 3) // Value 138*c6799d8aSAlexander von Gluck IV #define DP_TRAIN_PRE_EMPHASIS_6 (2 << 3) // Value 139*c6799d8aSAlexander von Gluck IV #define DP_TRAIN_PRE_EMPHASIS_9_5 (3 << 3) // Value 140*c6799d8aSAlexander von Gluck IV #define DP_TRAIN_MAX_EMPHASIS_EN (1 << 5) // Bool 1414185aa0cSAlexander von Gluck IV // DP Down-spread Control (0x0107) 14264dcb00fSAlexander von Gluck IV #define DP_DOWNSPREAD_CTRL 0x0107 // Reg 143*c6799d8aSAlexander von Gluck IV #define DP_DOWNSPREAD_CTRL_FREQ_MASK (1 << 0) // Int 144*c6799d8aSAlexander von Gluck IV #define DP_DOWNSPREAD_CTRL_AMP_EN (1 << 4) // Int 1454185aa0cSAlexander von Gluck IV // DP Main Link Channel Coding (0x0108) 1464185aa0cSAlexander von Gluck IV #define DP_MAIN_CHAN_CODE 0x0108 // Reg 147*c6799d8aSAlexander von Gluck IV #define DP_MAIN_CHAN_CODE_ANSIX3_EN (1 << 0) // Bool 1484185aa0cSAlexander von Gluck IV 1494185aa0cSAlexander von Gluck IV /* *** DPCD Link / Sink Status Field (0x0200) *** */ 1504185aa0cSAlexander von Gluck IV /* *** VESA DisplayPort Standard, rev 1.1, p120 *** */ 1514185aa0cSAlexander von Gluck IV 1524185aa0cSAlexander von Gluck IV // TODO 1534185aa0cSAlexander von Gluck IV 1544185aa0cSAlexander von Gluck IV /* *** DPCD Automated Self-testing Field (0x0218) *** */ 1554185aa0cSAlexander von Gluck IV /* *** VESA DisplayPort Standard, rev 1.1, p123 *** */ 1564185aa0cSAlexander von Gluck IV 1574185aa0cSAlexander von Gluck IV // TODO: Optional Field 1584185aa0cSAlexander von Gluck IV 1594185aa0cSAlexander von Gluck IV /* *** DPCD Source Device Specific Field (0x0300) *** */ 1604185aa0cSAlexander von Gluck IV /* *** VESA DisplayPort Standard, rev 1.1, p127 *** */ 1614185aa0cSAlexander von Gluck IV 1624185aa0cSAlexander von Gluck IV // TODO 1634185aa0cSAlexander von Gluck IV 1644185aa0cSAlexander von Gluck IV /* *** DPCD Sink Device Specific Field (0x0400) *** */ 1654185aa0cSAlexander von Gluck IV /* *** VESA DisplayPort Standard, rev 1.1, p127 *** */ 1664185aa0cSAlexander von Gluck IV 1674185aa0cSAlexander von Gluck IV // TODO 1684185aa0cSAlexander von Gluck IV 1694185aa0cSAlexander von Gluck IV /* *** DPCD Branch Device Specific Field (0x0500) *** */ 1704185aa0cSAlexander von Gluck IV /* *** VESA DisplayPort Standard, rev 1.1, p127 *** */ 1714185aa0cSAlexander von Gluck IV 1724185aa0cSAlexander von Gluck IV // TODO 1734185aa0cSAlexander von Gluck IV 1744185aa0cSAlexander von Gluck IV /* *** DPCD Sink Control Field (0x0600) *** */ 1754185aa0cSAlexander von Gluck IV /* *** VESA DisplayPort Standard, rev 1.1, p128 *** */ 1764185aa0cSAlexander von Gluck IV 1774185aa0cSAlexander von Gluck IV // TODO 1784185aa0cSAlexander von Gluck IV 1794185aa0cSAlexander von Gluck IV /* *** DPCD Reserved (0x0700+) *** */ 1804185aa0cSAlexander von Gluck IV /* ****************************************************** */ 1814185aa0cSAlexander von Gluck IV 1824185aa0cSAlexander von Gluck IV 1834185aa0cSAlexander von Gluck IV #endif /* _DP_RAW_H */ 184