14185aa0cSAlexander von Gluck IV /* 24185aa0cSAlexander von Gluck IV * Copyright 2012 Haiku, Inc. All rights reserved. 34185aa0cSAlexander von Gluck IV * Distributed under the terms of the MIT License. 44185aa0cSAlexander von Gluck IV * 54185aa0cSAlexander von Gluck IV * Authors: 64185aa0cSAlexander von Gluck IV * Alexander von Gluck, kallisti5@unixzen.com 74185aa0cSAlexander von Gluck IV */ 84185aa0cSAlexander von Gluck IV #ifndef _DP_RAW_H 94185aa0cSAlexander von Gluck IV #define _DP_RAW_H 104185aa0cSAlexander von Gluck IV 114185aa0cSAlexander von Gluck IV 124185aa0cSAlexander von Gluck IV /* ****************************************************** */ 1337550d80SAlexander von Gluck IV /* *** AUX Channel Communications *** */ 1437550d80SAlexander von Gluck IV // Native AUX Communications 15c6799d8aSAlexander von Gluck IV #define AUX_NATIVE_WRITE (8 << 0) 16c6799d8aSAlexander von Gluck IV #define AUX_NATIVE_READ (9 << 0) 17c6799d8aSAlexander von Gluck IV #define AUX_NATIVE_REPLY_ACK (0 << 4) 18c6799d8aSAlexander von Gluck IV #define AUX_NATIVE_REPLY_NACK (1 << 4) 19c6799d8aSAlexander von Gluck IV #define AUX_NATIVE_REPLY_DEFER (2 << 4) 20c6799d8aSAlexander von Gluck IV #define AUX_NATIVE_REPLY_MASK (3 << 4) 2137550d80SAlexander von Gluck IV // AUX i2c Communications 22c6799d8aSAlexander von Gluck IV #define AUX_I2C_WRITE (0 << 0) 23c6799d8aSAlexander von Gluck IV #define AUX_I2C_READ (1 << 0) 24c6799d8aSAlexander von Gluck IV #define AUX_I2C_STATUS (2 << 0) 25c6799d8aSAlexander von Gluck IV #define AUX_I2C_MOT (4 << 0) 26c6799d8aSAlexander von Gluck IV #define AUX_I2C_REPLY_ACK (0 << 6) 27c6799d8aSAlexander von Gluck IV #define AUX_I2C_REPLY_NACK (1 << 6) 28c6799d8aSAlexander von Gluck IV #define AUX_I2C_REPLY_DEFER (2 << 6) 29c6799d8aSAlexander von Gluck IV #define AUX_I2C_REPLY_MASK (3 << 6) 3037550d80SAlexander von Gluck IV 3137550d80SAlexander von Gluck IV 3237550d80SAlexander von Gluck IV /* ****************************************************** */ 334185aa0cSAlexander von Gluck IV /* *** DPCD (DisplayPort Configuration Data) *** */ 344185aa0cSAlexander von Gluck IV /* *** Read / Written over DisplayPort AUX link *** */ 354185aa0cSAlexander von Gluck IV 364185aa0cSAlexander von Gluck IV /* *** DPCD Receiver Compatibility Field (0x0000) *** */ 374185aa0cSAlexander von Gluck IV /* *** VESA DisplayPort Standard, rev 1.1, p112 *** */ 384185aa0cSAlexander von Gluck IV // DPCD Version (0x0) 394185aa0cSAlexander von Gluck IV #define DP_DPCD_REV 0x0000 // Reg 40c6799d8aSAlexander von Gluck IV #define DP_DPCD_REV_MINOR_MASK (15 << 0) // Int 41c6799d8aSAlexander von Gluck IV #define DP_DPCD_REV_MAJOR_MASK (15 << 4) // Int 42c6799d8aSAlexander von Gluck IV #define DP_DPCD_REV_10 0x0010 // Value 43c6799d8aSAlexander von Gluck IV #define DP_DPCD_REV_11 0x0011 // Value 444185aa0cSAlexander von Gluck IV // DP Maximum Link Rate (0x1) 454185aa0cSAlexander von Gluck IV #define DP_MAX_LINK_RATE 0x0001 // Reg 46c6799d8aSAlexander von Gluck IV // Use DP_LINK_RATE_* for speed. 474185aa0cSAlexander von Gluck IV // DP Maximum Lane Count (0x2) 484185aa0cSAlexander von Gluck IV #define DP_MAX_LANE_COUNT 0x0002 // Reg 49c6799d8aSAlexander von Gluck IV #define DP_MAX_LANE_COUNT_MASK (31 << 0) // Count 50c6799d8aSAlexander von Gluck IV #define DP_MAX_LANE_COUNT_1 (1 << 0) // Value 51c6799d8aSAlexander von Gluck IV #define DP_MAX_LANE_COUNT_2 (2 << 0) // Value 52c6799d8aSAlexander von Gluck IV #define DP_MAX_LANE_COUNT_4 (4 << 0) // Value 53c6799d8aSAlexander von Gluck IV #define DP_ENHANCED_FRAME_CAP_EN (1 << 7) // Bool, Rev 1.1 544185aa0cSAlexander von Gluck IV // DP Maximum Downspread (0x3) 554185aa0cSAlexander von Gluck IV #define DP_MAX_DOWNSPREAD 0x0003 // Reg 56c6799d8aSAlexander von Gluck IV #define DP_MAX_DOWNSPREAD_EN (1 << 0) // Bool 57c6799d8aSAlexander von Gluck IV #define DP_MAX_DOWNSPREAD_REQ_NO_HANDSHAKE (1 << 6) // Bool 584185aa0cSAlexander von Gluck IV // DP Number of Receiver Ports (0x4) 594185aa0cSAlexander von Gluck IV #define DP_NORP 0x0004 // Reg 60c6799d8aSAlexander von Gluck IV #define DP_NORP_MASK (1 << 0) // Count 614185aa0cSAlexander von Gluck IV // DP Downstream Port Present (0x5) 624185aa0cSAlexander von Gluck IV #define DP_DOWNSTREAMPORT 0x0005 // Reg 63c6799d8aSAlexander von Gluck IV #define DP_DOWNSTREAMPORT_EN (1 << 0) // Bool 64c6799d8aSAlexander von Gluck IV #define DP_DOWNSTREAMPORT_TYPE_MASK (3 << 1) // Mask 65c6799d8aSAlexander von Gluck IV #define DP_DOWNSTREAMPORT_TYPE_DP (0 << 1) // Value 66c6799d8aSAlexander von Gluck IV #define DP_DOWNSTREAMPORT_TYPE_ANALOG (1 << 1) // Value 67c6799d8aSAlexander von Gluck IV #define DP_DOWNSTREAMPORT_TYPE_DIGITAL (2 << 1) // Value 68c6799d8aSAlexander von Gluck IV #define DP_DOWNSTREAMPORT_TYPE_OTHER (3 << 1) // Value 69c6799d8aSAlexander von Gluck IV #define DP_DOWNSTREAMPORT_FORMAT_EN (1 << 3) // Bool 704185aa0cSAlexander von Gluck IV // DP Main Link Channel Coding (0x6) 714185aa0cSAlexander von Gluck IV #define DP_CURR_MAIN_CHAN_CODE 0x0006 // Reg 72c6799d8aSAlexander von Gluck IV #define DP_CURR_MAIN_CHAN_CODE_ANSIX3_EN (1 << 0) // Bool 734185aa0cSAlexander von Gluck IV // DP Downstream Port Count (0x7) (Only 1.1+) 744185aa0cSAlexander von Gluck IV #define DP_DOWNSTREAMPORT_COUNT 0x0007 // Reg 75c6799d8aSAlexander von Gluck IV #define DP_DOWNSTREAMPORT_COUNT_MASK (15 << 0) // Count 76c6799d8aSAlexander von Gluck IV #define DP_DOWNSTREAMPORT_COUNT_OUI_EN (1 << 7) // Bool 774185aa0cSAlexander von Gluck IV // DP Port Capability 0 784185aa0cSAlexander von Gluck IV #define DP_PORT0_CAPABILITY0 0x0008 // Reg 794185aa0cSAlexander von Gluck IV #define DP_PORT1_CAPABILITY0 0x000A // Reg 80c6799d8aSAlexander von Gluck IV #define DP_PORT_CAPABILITY0_EDID_EN (1 << 1) // Bool 81c6799d8aSAlexander von Gluck IV #define DP_PORT_CAPABILITY0_SECOND_EN (1 << 2) // Bool 824185aa0cSAlexander von Gluck IV // DP Port Capability 1 834185aa0cSAlexander von Gluck IV #define DP_PORT0_CAPABILITY1 0x0009 // Reg 844185aa0cSAlexander von Gluck IV #define DP_PORT1_CAPABILITY1 0x000B // Reg 85c6799d8aSAlexander von Gluck IV #define DP_PORT_CAPABILITY1_BUF_SIZE_MASK (255 << 0) // Size 864185aa0cSAlexander von Gluck IV // (value + 1) * 32 bytes per lane 874185aa0cSAlexander von Gluck IV 884185aa0cSAlexander von Gluck IV /* *** DPCD Link Configuration Field (0x0100) *** */ 894185aa0cSAlexander von Gluck IV /* *** VESA DisplayPort Standard, rev 1.1, p117 *** */ 904185aa0cSAlexander von Gluck IV 914185aa0cSAlexander von Gluck IV // DP Set Link Rate Per Lane (0x0100) 924185aa0cSAlexander von Gluck IV #define DP_LINK_RATE 0x0100 // Reg 934185aa0cSAlexander von Gluck IV #define DP_LINK_RATE_162 0x0006 // 1.62Ghz 944185aa0cSAlexander von Gluck IV #define DP_LINK_RATE_270 0x000A // 2.70Ghz 954185aa0cSAlexander von Gluck IV #define DP_LINK_RATE_540 0x0014 // 5.40Ghz 964185aa0cSAlexander von Gluck IV // DP Set Lane Count (0x0101) 974185aa0cSAlexander von Gluck IV #define DP_LANE_COUNT 0x0101 // Reg 98c6799d8aSAlexander von Gluck IV #define DP_LANE_COUNT_MASK (31 << 0) // Count 99c6799d8aSAlexander von Gluck IV #define DP_ENHANCED_FRAME_EN (1 << 7) // Bool, Rev 1.1 1004185aa0cSAlexander von Gluck IV // DP Training Pattern (0x0102) 101c6799d8aSAlexander von Gluck IV #define DP_TRAIN 0x0102 // Reg 102c6799d8aSAlexander von Gluck IV #define DP_TRAIN_PATTERN_MASK (3 << 0) // Mask 103c6799d8aSAlexander von Gluck IV #define DP_TRAIN_PATTERN_DISABLED (0 << 0) // Value 104c6799d8aSAlexander von Gluck IV #define DP_TRAIN_PATTERN_1 (1 << 0) // Value 105c6799d8aSAlexander von Gluck IV #define DP_TRAIN_PATTERN_2 (2 << 0) // Value 106c6799d8aSAlexander von Gluck IV #define DP_TRAIN_PATTERN_3 (3 << 0) // Value 107c6799d8aSAlexander von Gluck IV 108c6799d8aSAlexander von Gluck IV #define DP_TRAIN_QUAL_MASK (3 << 2) // Mask 109c6799d8aSAlexander von Gluck IV #define DP_TRAIN_QUAL_NONE (0 << 2) // Value 110c6799d8aSAlexander von Gluck IV #define DP_TRAIN_QUAL_D102 (1 << 2) // Value 111c6799d8aSAlexander von Gluck IV #define DP_TRAIN_QUAL_SYMB_ERR (2 << 2) // Value 112c6799d8aSAlexander von Gluck IV #define DP_TRAIN_QUAL_PRBS7 (3 << 2) // Value 113c6799d8aSAlexander von Gluck IV 114c6799d8aSAlexander von Gluck IV #define DP_TRAIN_CLOCK_RECOVER_EN (1 << 4) // Bool 115c6799d8aSAlexander von Gluck IV #define DP_TRAIN_SCRAMBLE_DI (1 << 5) // Bool (rev) 116c6799d8aSAlexander von Gluck IV #define DP_TRAIN_SYMBL_ERR_SEL_MASK (3 << 6) // Mask 117c6799d8aSAlexander von Gluck IV #define DP_TRAIN_SYMBL_ERR_SEL_BOTH (0 << 6) // Value 118c6799d8aSAlexander von Gluck IV #define DP_TRAIN_SYMBL_ERR_SEL_DISPARITY (1 << 6) // Value 119c6799d8aSAlexander von Gluck IV #define DP_TRAIN_SYMBL_ERR_SEL_SYMBOL (2 << 6) // Value 1204185aa0cSAlexander von Gluck IV // DP Training Lane n (0x0103 - 0x0106) 121c6799d8aSAlexander von Gluck IV #define DP_TRAIN_LANE0 0x0103 // Reg 122c6799d8aSAlexander von Gluck IV #define DP_TRAIN_LANE1 0x0104 // Reg 123c6799d8aSAlexander von Gluck IV #define DP_TRAIN_LANE2 0x0105 // Reg 124c6799d8aSAlexander von Gluck IV #define DP_TRAIN_LANE3 0x0106 // Reg 125c6799d8aSAlexander von Gluck IV 126c6799d8aSAlexander von Gluck IV #define DP_TRAIN_VCC_SWING_SHIFT (0 << 0) // Shift 127c6799d8aSAlexander von Gluck IV #define DP_TRAIN_VCC_SWING_MASK (3 << 0) // Mask 128c6799d8aSAlexander von Gluck IV #define DP_TRAIN_VCC_SWING_400 (0 << 0) // Value 129c6799d8aSAlexander von Gluck IV #define DP_TRAIN_VCC_SWING_600 (1 << 0) // Value 130c6799d8aSAlexander von Gluck IV #define DP_TRAIN_VCC_SWING_800 (2 << 0) // Value 131c6799d8aSAlexander von Gluck IV #define DP_TRAIN_VCC_SWING_1200 (3 << 0) // Value 132c6799d8aSAlexander von Gluck IV #define DP_TRAIN_MAX_SWING_EN (1 << 2) // Bool 133c6799d8aSAlexander von Gluck IV 134c6799d8aSAlexander von Gluck IV #define DP_TRAIN_PRE_EMPHASIS_SHIFT (3 << 0) // Shift 135c6799d8aSAlexander von Gluck IV #define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3) // Mask 136c6799d8aSAlexander von Gluck IV #define DP_TRAIN_PRE_EMPHASIS_0 (0 << 3) // Value 137c6799d8aSAlexander von Gluck IV #define DP_TRAIN_PRE_EMPHASIS_3_5 (1 << 3) // Value 138c6799d8aSAlexander von Gluck IV #define DP_TRAIN_PRE_EMPHASIS_6 (2 << 3) // Value 139c6799d8aSAlexander von Gluck IV #define DP_TRAIN_PRE_EMPHASIS_9_5 (3 << 3) // Value 140c6799d8aSAlexander von Gluck IV #define DP_TRAIN_MAX_EMPHASIS_EN (1 << 5) // Bool 1414185aa0cSAlexander von Gluck IV // DP Down-spread Control (0x0107) 14264dcb00fSAlexander von Gluck IV #define DP_DOWNSPREAD_CTRL 0x0107 // Reg 143c6799d8aSAlexander von Gluck IV #define DP_DOWNSPREAD_CTRL_FREQ_MASK (1 << 0) // Int 144c6799d8aSAlexander von Gluck IV #define DP_DOWNSPREAD_CTRL_AMP_EN (1 << 4) // Int 1454185aa0cSAlexander von Gluck IV // DP Main Link Channel Coding (0x0108) 1464185aa0cSAlexander von Gluck IV #define DP_MAIN_CHAN_CODE 0x0108 // Reg 147c6799d8aSAlexander von Gluck IV #define DP_MAIN_CHAN_CODE_ANSIX3_EN (1 << 0) // Bool 1484185aa0cSAlexander von Gluck IV 1494185aa0cSAlexander von Gluck IV /* *** DPCD Link / Sink Status Field (0x0200) *** */ 1504185aa0cSAlexander von Gluck IV /* *** VESA DisplayPort Standard, rev 1.1, p120 *** */ 1514185aa0cSAlexander von Gluck IV 152*8dfc5dbbSAlexander von Gluck IV // DP Sink Count (0x0200) 153*8dfc5dbbSAlexander von Gluck IV #define DP_SINK_COUNT 0x0200 // Reg 154*8dfc5dbbSAlexander von Gluck IV #define DP_SINK_COUNT_MASK (63 << 0) // Mask 155*8dfc5dbbSAlexander von Gluck IV #define DP_SINK_COUNT_CP_READY (1 << 6) // Bool 156*8dfc5dbbSAlexander von Gluck IV // DP Service IRQ Vector (0x0201) 157*8dfc5dbbSAlexander von Gluck IV #define DP_SINK_IRQ_VECTOR 0x0201 // Reg 158*8dfc5dbbSAlexander von Gluck IV #define DP_SINK_IRQ_TEST_REQ (1 << 1) // Bool 159*8dfc5dbbSAlexander von Gluck IV #define DP_SINK_IRQ_CP_IRQ (1 << 2) // Bool 160*8dfc5dbbSAlexander von Gluck IV #define DP_SINK_IRQ_VENDOR (1 << 6) // Bool 161*8dfc5dbbSAlexander von Gluck IV // DP Lane Status A B 162*8dfc5dbbSAlexander von Gluck IV #define DP_LANE_STATUS_0_1 0x0202 // Reg 163*8dfc5dbbSAlexander von Gluck IV #define DP_LANE_STATUS_2_3 0x0203 // Reg 164*8dfc5dbbSAlexander von Gluck IV #define DP_LINK_STATUS_SIZE 6 // Size 165*8dfc5dbbSAlexander von Gluck IV #define DP_LANE_STATUS_CR_DONE_A (1 << 0) // Bool 166*8dfc5dbbSAlexander von Gluck IV #define DP_LANE_STATUS_CHEQ_DONE_A (1 << 1) // Bool 167*8dfc5dbbSAlexander von Gluck IV #define DP_LANE_STATUS_SYMB_LOCK_A (1 << 2) // Bool 168*8dfc5dbbSAlexander von Gluck IV #define DP_LANE_STATUS_CR_DONE_B (1 << 4) // Bool 169*8dfc5dbbSAlexander von Gluck IV #define DP_LANE_STATUS_CHEQ_DONE_B (1 << 5) // Bool 170*8dfc5dbbSAlexander von Gluck IV #define DP_LANE_STATUS_SYMB_LOCK_B (1 << 6) // Bool 171*8dfc5dbbSAlexander von Gluck IV // DP Lane Align Status (0x0204) 172*8dfc5dbbSAlexander von Gluck IV #define DP_LANE_ALIGN 0x0204 // Reg 173*8dfc5dbbSAlexander von Gluck IV #define DP_LANE_ALIGN_DONE (1 << 0) // Bool 174*8dfc5dbbSAlexander von Gluck IV #define DP_LANE_ALIGN_PORT_STATUS_CHANGE (1 << 6) // Bool 175*8dfc5dbbSAlexander von Gluck IV #define DP_LANE_ALIGN_LINK_STATUS_UPDATE (1 << 7) // Bool 176*8dfc5dbbSAlexander von Gluck IV // DP Sink Status (0x0205) 177*8dfc5dbbSAlexander von Gluck IV #define DP_SINK_STATUS 0x0205 // Reg 178*8dfc5dbbSAlexander von Gluck IV #define DP_SINK_STATUS_IN_SYNC_0 (1 << 0) // Bool 179*8dfc5dbbSAlexander von Gluck IV #define DP_SINK_STATUS_IN_SYNC_1 (1 << 1) // Bool 180*8dfc5dbbSAlexander von Gluck IV // DP Adjust Request A B 181*8dfc5dbbSAlexander von Gluck IV #define DP_ADJ_REQUEST_0_1 0x0206 // Reg 182*8dfc5dbbSAlexander von Gluck IV #define DP_ADJ_REQUEST_2_3 0x0207 // Reg 183*8dfc5dbbSAlexander von Gluck IV #define DP_ADJ_VCC_SWING_LANEA_SHIFT 0 // Shift 184*8dfc5dbbSAlexander von Gluck IV #define DP_ADJ_VCC_SWING_LANEA_MASK (3 << 0) // Mask 185*8dfc5dbbSAlexander von Gluck IV #define DP_ADJ_PRE_EMPHASIS_LANEA_SHIFT 2 // Shift 186*8dfc5dbbSAlexander von Gluck IV #define DP_ADJ_PRE_EMPHASIS_LANEA_MASK (3 << 2) // Mask 187*8dfc5dbbSAlexander von Gluck IV #define DP_ADJ_VCC_SWING_LANEB_SHIFT 4 // Shift 188*8dfc5dbbSAlexander von Gluck IV #define DP_ADJ_VCC_SRING_LANEB_MASK (3 << 4) // Mask 189*8dfc5dbbSAlexander von Gluck IV #define DP_ADJ_PRE_EMPHASIS_LANEB_SHIFT 6 // Shift 190*8dfc5dbbSAlexander von Gluck IV #define DP_ADJ_PRE_EMPHASIS_LANEB_MASK (3 << 6) // Mask 191*8dfc5dbbSAlexander von Gluck IV 192*8dfc5dbbSAlexander von Gluck IV // TODO: 0x0210 - 0x0217 1934185aa0cSAlexander von Gluck IV 1944185aa0cSAlexander von Gluck IV /* *** DPCD Automated Self-testing Field (0x0218) *** */ 1954185aa0cSAlexander von Gluck IV /* *** VESA DisplayPort Standard, rev 1.1, p123 *** */ 1964185aa0cSAlexander von Gluck IV 1974185aa0cSAlexander von Gluck IV // TODO: Optional Field 1984185aa0cSAlexander von Gluck IV 1994185aa0cSAlexander von Gluck IV /* *** DPCD Source Device Specific Field (0x0300) *** */ 2004185aa0cSAlexander von Gluck IV /* *** VESA DisplayPort Standard, rev 1.1, p127 *** */ 2014185aa0cSAlexander von Gluck IV 2024185aa0cSAlexander von Gluck IV // TODO 2034185aa0cSAlexander von Gluck IV 2044185aa0cSAlexander von Gluck IV /* *** DPCD Sink Device Specific Field (0x0400) *** */ 2054185aa0cSAlexander von Gluck IV /* *** VESA DisplayPort Standard, rev 1.1, p127 *** */ 2064185aa0cSAlexander von Gluck IV 2074185aa0cSAlexander von Gluck IV // TODO 2084185aa0cSAlexander von Gluck IV 2094185aa0cSAlexander von Gluck IV /* *** DPCD Branch Device Specific Field (0x0500) *** */ 2104185aa0cSAlexander von Gluck IV /* *** VESA DisplayPort Standard, rev 1.1, p127 *** */ 2114185aa0cSAlexander von Gluck IV 2124185aa0cSAlexander von Gluck IV // TODO 2134185aa0cSAlexander von Gluck IV 2144185aa0cSAlexander von Gluck IV /* *** DPCD Sink Control Field (0x0600) *** */ 2154185aa0cSAlexander von Gluck IV /* *** VESA DisplayPort Standard, rev 1.1, p128 *** */ 2164185aa0cSAlexander von Gluck IV 217*8dfc5dbbSAlexander von Gluck IV #define DP_SET_POWER 0x0600 // Reg 218*8dfc5dbbSAlexander von Gluck IV #define DP_SET_POWER_D0 (1 << 0) // Value 219*8dfc5dbbSAlexander von Gluck IV #define DP_SET_POWER_D3 (1 << 1) // Value 2204185aa0cSAlexander von Gluck IV 2214185aa0cSAlexander von Gluck IV /* *** DPCD Reserved (0x0700+) *** */ 2224185aa0cSAlexander von Gluck IV /* ****************************************************** */ 2234185aa0cSAlexander von Gluck IV 2244185aa0cSAlexander von Gluck IV 2254185aa0cSAlexander von Gluck IV #endif /* _DP_RAW_H */ 226