14185aa0cSAlexander von Gluck IV /* 24185aa0cSAlexander von Gluck IV * Copyright 2012 Haiku, Inc. All rights reserved. 34185aa0cSAlexander von Gluck IV * Distributed under the terms of the MIT License. 44185aa0cSAlexander von Gluck IV * 54185aa0cSAlexander von Gluck IV * Authors: 64185aa0cSAlexander von Gluck IV * Alexander von Gluck, kallisti5@unixzen.com 74185aa0cSAlexander von Gluck IV */ 84185aa0cSAlexander von Gluck IV #ifndef _DP_RAW_H 94185aa0cSAlexander von Gluck IV #define _DP_RAW_H 104185aa0cSAlexander von Gluck IV 114185aa0cSAlexander von Gluck IV 124185aa0cSAlexander von Gluck IV /* ****************************************************** */ 13*37550d80SAlexander von Gluck IV /* *** AUX Channel Communications *** */ 14*37550d80SAlexander von Gluck IV // Native AUX Communications 15*37550d80SAlexander von Gluck IV #define AUX_NATIVE_WRITE 0x8 16*37550d80SAlexander von Gluck IV #define AUX_NATIVE_READ 0x9 17*37550d80SAlexander von Gluck IV #define AUX_NATIVE_REPLY_ACK (0x0 << 4) 18*37550d80SAlexander von Gluck IV #define AUX_NATIVE_REPLY_NACK (0x1 << 4) 19*37550d80SAlexander von Gluck IV #define AUX_NATIVE_REPLY_DEFER (0x2 << 4) 20*37550d80SAlexander von Gluck IV #define AUX_NATIVE_REPLY_MASK (0x3 << 4) 21*37550d80SAlexander von Gluck IV // AUX i2c Communications 22*37550d80SAlexander von Gluck IV #define AUX_I2C_WRITE 0x0 23*37550d80SAlexander von Gluck IV #define AUX_I2C_READ 0x1 24*37550d80SAlexander von Gluck IV #define AUX_I2C_STATUS 0x2 25*37550d80SAlexander von Gluck IV #define AUX_I2C_MOT 0x4 26*37550d80SAlexander von Gluck IV #define AUX_I2C_REPLY_ACK (0x0 << 6) 27*37550d80SAlexander von Gluck IV #define AUX_I2C_REPLY_NACK (0x1 << 6) 28*37550d80SAlexander von Gluck IV #define AUX_I2C_REPLY_DEFER (0x2 << 6) 29*37550d80SAlexander von Gluck IV #define AUX_I2C_REPLY_MASK (0x3 << 6) 30*37550d80SAlexander von Gluck IV 31*37550d80SAlexander von Gluck IV 32*37550d80SAlexander von Gluck IV /* ****************************************************** */ 334185aa0cSAlexander von Gluck IV /* *** DPCD (DisplayPort Configuration Data) *** */ 344185aa0cSAlexander von Gluck IV /* *** Read / Written over DisplayPort AUX link *** */ 354185aa0cSAlexander von Gluck IV 364185aa0cSAlexander von Gluck IV /* *** DPCD Receiver Compatibility Field (0x0000) *** */ 374185aa0cSAlexander von Gluck IV /* *** VESA DisplayPort Standard, rev 1.1, p112 *** */ 384185aa0cSAlexander von Gluck IV // DPCD Version (0x0) 394185aa0cSAlexander von Gluck IV #define DP_DPCD_REV 0x0000 // Reg 404185aa0cSAlexander von Gluck IV #define DP_DPCD_REV_MINOR_MASK 0x000F // Int 414185aa0cSAlexander von Gluck IV #define DP_DPCD_REV_MAJOR_MASK 0x00F0 // Int 424185aa0cSAlexander von Gluck IV // DP Maximum Link Rate (0x1) 434185aa0cSAlexander von Gluck IV #define DP_MAX_LINK_RATE 0x0001 // Reg 444185aa0cSAlexander von Gluck IV #define DP_MAX_LINK_RATE_162 0x0006 // 1.62Ghz 454185aa0cSAlexander von Gluck IV #define DP_MAX_LINK_RATE_270 0x000A // 2.70Ghz 464185aa0cSAlexander von Gluck IV #define DP_MAX_LINK_RATE_540 0x0014 // 5.40Ghz 474185aa0cSAlexander von Gluck IV // DP Maximum Lane Count (0x2) 484185aa0cSAlexander von Gluck IV #define DP_MAX_LANE_COUNT 0x0002 // Reg 494185aa0cSAlexander von Gluck IV #define DP_MAX_LANE_COUNT_MASK 0x001F // Count 504185aa0cSAlexander von Gluck IV #define DP_ENHANCED_FRAME_CAP_MASK 0x0080 // Bool, Rev 1.1+ 514185aa0cSAlexander von Gluck IV // DP Maximum Downspread (0x3) 524185aa0cSAlexander von Gluck IV #define DP_MAX_DOWNSPREAD 0x0003 // Reg 534185aa0cSAlexander von Gluck IV #define DP_MAX_DOWNSPREAD_EN_MASK 0x0001 // Bool 544185aa0cSAlexander von Gluck IV #define DP_MAX_DOWNSPREAD_EN_AUX_TRAIN_MASK 0x0040 // Bool 554185aa0cSAlexander von Gluck IV // DP Number of Receiver Ports (0x4) 564185aa0cSAlexander von Gluck IV #define DP_NORP 0x0004 // Reg 574185aa0cSAlexander von Gluck IV #define DP_NORP_MASK 0x0001 // Count 584185aa0cSAlexander von Gluck IV // DP Downstream Port Present (0x5) 594185aa0cSAlexander von Gluck IV #define DP_DOWNSTREAMPORT 0x0005 // Reg 604185aa0cSAlexander von Gluck IV #define DP_DOWNSTREAMPORT_EN_MASK 0x0001 // Bool 614185aa0cSAlexander von Gluck IV #define DP_DOWNSTREAMPORT_TYPE_MASK 0x0006 // Type 624185aa0cSAlexander von Gluck IV #define DP_DOWNSTREAMPORT_EN_FORMAT_MASK 0x0008 // Bool 634185aa0cSAlexander von Gluck IV // DP Main Link Channel Coding (0x6) 644185aa0cSAlexander von Gluck IV #define DP_CURR_MAIN_CHAN_CODE 0x0006 // Reg 654185aa0cSAlexander von Gluck IV #define DP_CURR_MAIN_CHAN_CODE_EN_ANSI_MASK 0x0001 // Bool 664185aa0cSAlexander von Gluck IV // DP Downstream Port Count (0x7) (Only 1.1+) 674185aa0cSAlexander von Gluck IV #define DP_DOWNSTREAMPORT_COUNT 0x0007 // Reg 684185aa0cSAlexander von Gluck IV #define DP_DOWNSTREAMPORT_COUNT_MASK 0x000F // Count 694185aa0cSAlexander von Gluck IV #define DP_DOWNSTREAMPORT_COUNT_EN_OUI_MASK 0x0080 // Bool 704185aa0cSAlexander von Gluck IV // DP Port Capability 0 714185aa0cSAlexander von Gluck IV #define DP_PORT0_CAPABILITY0 0x0008 // Reg 724185aa0cSAlexander von Gluck IV #define DP_PORT1_CAPABILITY0 0x000A // Reg 734185aa0cSAlexander von Gluck IV #define DP_PORTX_CAPABILITY0_EN_EDID_MASK 0x0002 // Bool 744185aa0cSAlexander von Gluck IV #define DP_PORTX_CAPABILITY0_EN_SECOND_MASK 0x0004 // Bool 754185aa0cSAlexander von Gluck IV // DP Port Capability 1 764185aa0cSAlexander von Gluck IV #define DP_PORT0_CAPABILITY1 0x0009 // Reg 774185aa0cSAlexander von Gluck IV #define DP_PORT1_CAPABILITY1 0x000B // Reg 784185aa0cSAlexander von Gluck IV #define DP_PORT0_CAPABILITY1_BUF_SIZE_MASK 0x00FF // Size 794185aa0cSAlexander von Gluck IV // (value + 1) * 32 bytes per lane 804185aa0cSAlexander von Gluck IV 814185aa0cSAlexander von Gluck IV /* *** DPCD Link Configuration Field (0x0100) *** */ 824185aa0cSAlexander von Gluck IV /* *** VESA DisplayPort Standard, rev 1.1, p117 *** */ 834185aa0cSAlexander von Gluck IV 844185aa0cSAlexander von Gluck IV // DP Set Link Rate Per Lane (0x0100) 854185aa0cSAlexander von Gluck IV #define DP_LINK_RATE 0x0100 // Reg 864185aa0cSAlexander von Gluck IV #define DP_LINK_RATE_162 0x0006 // 1.62Ghz 874185aa0cSAlexander von Gluck IV #define DP_LINK_RATE_270 0x000A // 2.70Ghz 884185aa0cSAlexander von Gluck IV #define DP_LINK_RATE_540 0x0014 // 5.40Ghz 894185aa0cSAlexander von Gluck IV // DP Set Lane Count (0x0101) 904185aa0cSAlexander von Gluck IV #define DP_LANE_COUNT 0x0101 // Reg 914185aa0cSAlexander von Gluck IV #define DP_LANE_COUNT_MASK 0x001F // Count 924185aa0cSAlexander von Gluck IV #define DP_ENHANCED_FRAME_EN_MASK 0x0080 // Bool, Rev 1.1+ 934185aa0cSAlexander von Gluck IV // DP Training Pattern (0x0102) 944185aa0cSAlexander von Gluck IV #define DP_LINK_TRAIN 0x0102 // Reg 954185aa0cSAlexander von Gluck IV #define DP_LINK_TRAIN_PATTERN_MASK 0x0003 // Mask 964185aa0cSAlexander von Gluck IV #define DP_LINK_TRAIN_PATTERN_DISABLED 0x0000 // Value 974185aa0cSAlexander von Gluck IV #define DP_LINK_TRAIN_PATTERN_1 0x0001 // Value 984185aa0cSAlexander von Gluck IV #define DP_LINK_TRAIN_PATTERN_2 0x0002 // Value 994185aa0cSAlexander von Gluck IV #define DP_LINK_TRAIN_PATTERN_3 0x0003 // Value 1004185aa0cSAlexander von Gluck IV #define DP_LINK_TRAIN_QUAL_MASK 0x000C // Mask 1014185aa0cSAlexander von Gluck IV #define DP_LINK_TRAIN_QUAL_NONE 0x0000 // Value 1024185aa0cSAlexander von Gluck IV #define DP_LINK_TRAIN_QUAL_D102 0x0004 // Value 1034185aa0cSAlexander von Gluck IV #define DP_LINK_TRAIN_QUAL_SYMB_ERR 0x0008 // Value 1044185aa0cSAlexander von Gluck IV #define DP_LINK_TRAIN_QUAL_PRBS7 0x000C // Value 1054185aa0cSAlexander von Gluck IV #define DP_LINK_TRAIN_CLOCK_RECOVER_EN_MASK 0x0010 // Bool 1064185aa0cSAlexander von Gluck IV #define DP_LINK_TRAIN_SCRAMBLE_DI_MASK 0x0020 // Bool (rev) 1074185aa0cSAlexander von Gluck IV #define DP_LINK_TRAIN_SYMBL_ERR_SEL_MASK 0x00C0 // Mask 1084185aa0cSAlexander von Gluck IV // DP Training Lane n (0x0103 - 0x0106) 1094185aa0cSAlexander von Gluck IV #define DP_LINK_TRAIN_LANE0 0x0103 // Reg 1104185aa0cSAlexander von Gluck IV #define DP_LINK_TRAIN_LANE1 0x0104 // Reg 1114185aa0cSAlexander von Gluck IV #define DP_LINK_TRAIN_LANE2 0x0105 // Reg 1124185aa0cSAlexander von Gluck IV #define DP_LINK_TRAIN_LANE3 0x0106 // Reg 1134185aa0cSAlexander von Gluck IV #define DP_LINK_TRAIN_LANEn_VCCSWING_MASK 0x0003 // Mask 1144185aa0cSAlexander von Gluck IV #define DP_LINK_TRAIN_LANEn_MAXSWING_MASK 0x0004 // Mask 1154185aa0cSAlexander von Gluck IV #define DP_LINK_TRAIN_LANEn_PREE_MASK 0x0018 // Mask 1164185aa0cSAlexander von Gluck IV #define DP_LINK_TRAIN_LANEn_MAXPREE_MASK 0x0020 // Mask 1174185aa0cSAlexander von Gluck IV // DP Down-spread Control (0x0107) 1184185aa0cSAlexander von Gluck IV #define DP_DOWNSPREAD_CTL 0x0107 // Reg 1194185aa0cSAlexander von Gluck IV #define DP_DOWNSPREAD_CTL_FREQ_MASK 0x0001 // Int 1204185aa0cSAlexander von Gluck IV #define DP_DOWNSPREAD_CTL_AMP_MASK 0x0010 // Int 1214185aa0cSAlexander von Gluck IV // DP Main Link Channel Coding (0x0108) 1224185aa0cSAlexander von Gluck IV #define DP_MAIN_CHAN_CODE 0x0108 // Reg 1234185aa0cSAlexander von Gluck IV #define DP_MAIN_CHAN_CODE_EN_ANSI_MASK 0x0001 // Bool 1244185aa0cSAlexander von Gluck IV 1254185aa0cSAlexander von Gluck IV /* *** DPCD Link / Sink Status Field (0x0200) *** */ 1264185aa0cSAlexander von Gluck IV /* *** VESA DisplayPort Standard, rev 1.1, p120 *** */ 1274185aa0cSAlexander von Gluck IV 1284185aa0cSAlexander von Gluck IV // TODO 1294185aa0cSAlexander von Gluck IV 1304185aa0cSAlexander von Gluck IV /* *** DPCD Automated Self-testing Field (0x0218) *** */ 1314185aa0cSAlexander von Gluck IV /* *** VESA DisplayPort Standard, rev 1.1, p123 *** */ 1324185aa0cSAlexander von Gluck IV 1334185aa0cSAlexander von Gluck IV // TODO: Optional Field 1344185aa0cSAlexander von Gluck IV 1354185aa0cSAlexander von Gluck IV /* *** DPCD Source Device Specific Field (0x0300) *** */ 1364185aa0cSAlexander von Gluck IV /* *** VESA DisplayPort Standard, rev 1.1, p127 *** */ 1374185aa0cSAlexander von Gluck IV 1384185aa0cSAlexander von Gluck IV // TODO 1394185aa0cSAlexander von Gluck IV 1404185aa0cSAlexander von Gluck IV /* *** DPCD Sink Device Specific Field (0x0400) *** */ 1414185aa0cSAlexander von Gluck IV /* *** VESA DisplayPort Standard, rev 1.1, p127 *** */ 1424185aa0cSAlexander von Gluck IV 1434185aa0cSAlexander von Gluck IV // TODO 1444185aa0cSAlexander von Gluck IV 1454185aa0cSAlexander von Gluck IV /* *** DPCD Branch Device Specific Field (0x0500) *** */ 1464185aa0cSAlexander von Gluck IV /* *** VESA DisplayPort Standard, rev 1.1, p127 *** */ 1474185aa0cSAlexander von Gluck IV 1484185aa0cSAlexander von Gluck IV // TODO 1494185aa0cSAlexander von Gluck IV 1504185aa0cSAlexander von Gluck IV /* *** DPCD Sink Control Field (0x0600) *** */ 1514185aa0cSAlexander von Gluck IV /* *** VESA DisplayPort Standard, rev 1.1, p128 *** */ 1524185aa0cSAlexander von Gluck IV 1534185aa0cSAlexander von Gluck IV // TODO 1544185aa0cSAlexander von Gluck IV 1554185aa0cSAlexander von Gluck IV /* *** DPCD Reserved (0x0700+) *** */ 1564185aa0cSAlexander von Gluck IV /* ****************************************************** */ 1574185aa0cSAlexander von Gluck IV 1584185aa0cSAlexander von Gluck IV 1594185aa0cSAlexander von Gluck IV #endif /* _DP_RAW_H */ 160