14185aa0cSAlexander von Gluck IV /* 299756206SAlexander von Gluck IV * Copyright 2012-2016 Haiku, Inc. All rights reserved. 34185aa0cSAlexander von Gluck IV * Distributed under the terms of the MIT License. 44185aa0cSAlexander von Gluck IV * 54185aa0cSAlexander von Gluck IV * Authors: 64185aa0cSAlexander von Gluck IV * Alexander von Gluck, kallisti5@unixzen.com 74185aa0cSAlexander von Gluck IV */ 84185aa0cSAlexander von Gluck IV #ifndef _DP_RAW_H 94185aa0cSAlexander von Gluck IV #define _DP_RAW_H 104185aa0cSAlexander von Gluck IV 114185aa0cSAlexander von Gluck IV 124185aa0cSAlexander von Gluck IV /* ****************************************************** */ 1337550d80SAlexander von Gluck IV /* *** AUX Channel Communications *** */ 1437550d80SAlexander von Gluck IV // Native AUX Communications 157ea1ad10SAlexander von Gluck IV #define DP_AUX_NATIVE_WRITE 0x8 167ea1ad10SAlexander von Gluck IV #define DP_AUX_NATIVE_READ 0x9 177ea1ad10SAlexander von Gluck IV #define DP_AUX_NATIVE_REPLY_ACK (0x0 << 0) 187ea1ad10SAlexander von Gluck IV #define DP_AUX_NATIVE_REPLY_NACK (0x1 << 0) 197ea1ad10SAlexander von Gluck IV #define DP_AUX_NATIVE_REPLY_DEFER (0x2 << 0) 207ea1ad10SAlexander von Gluck IV #define DP_AUX_NATIVE_REPLY_MASK (0x3 << 0) 2137550d80SAlexander von Gluck IV // AUX i2c Communications 227ea1ad10SAlexander von Gluck IV #define DP_AUX_I2C_WRITE 0x0 237ea1ad10SAlexander von Gluck IV #define DP_AUX_I2C_READ 0x1 2466a16010SAlexander von Gluck IV #define DP_AUX_I2C_WRITE_STATUS_UPDATE 0x2 257ea1ad10SAlexander von Gluck IV #define DP_AUX_I2C_MOT 0x4 267ea1ad10SAlexander von Gluck IV #define DP_AUX_I2C_REPLY_ACK (0x0 << 2) 277ea1ad10SAlexander von Gluck IV #define DP_AUX_I2C_REPLY_NACK (0x1 << 2) 287ea1ad10SAlexander von Gluck IV #define DP_AUX_I2C_REPLY_DEFER (0x2 << 2) 297ea1ad10SAlexander von Gluck IV #define DP_AUX_I2C_REPLY_MASK (0x3 << 2) 3037550d80SAlexander von Gluck IV 3137550d80SAlexander von Gluck IV 3237550d80SAlexander von Gluck IV /* ****************************************************** */ 334185aa0cSAlexander von Gluck IV /* *** DPCD (DisplayPort Configuration Data) *** */ 344185aa0cSAlexander von Gluck IV /* *** Read / Written over DisplayPort AUX link *** */ 354185aa0cSAlexander von Gluck IV 364185aa0cSAlexander von Gluck IV /* *** DPCD Receiver Compatibility Field (0x0000) *** */ 374185aa0cSAlexander von Gluck IV /* *** VESA DisplayPort Standard, rev 1.1, p112 *** */ 384185aa0cSAlexander von Gluck IV // DPCD Version (0x0) 394185aa0cSAlexander von Gluck IV #define DP_DPCD_REV 0x0000 // Reg 40c6799d8aSAlexander von Gluck IV #define DP_DPCD_REV_MINOR_MASK (15 << 0) // Int 41c6799d8aSAlexander von Gluck IV #define DP_DPCD_REV_MAJOR_MASK (15 << 4) // Int 42c6799d8aSAlexander von Gluck IV #define DP_DPCD_REV_10 0x0010 // Value 43c6799d8aSAlexander von Gluck IV #define DP_DPCD_REV_11 0x0011 // Value 442da9ebb7SAlexander von Gluck IV #define DP_DPCD_REV_12 0x0012 // Value 454185aa0cSAlexander von Gluck IV // DP Maximum Link Rate (0x1) 464185aa0cSAlexander von Gluck IV #define DP_MAX_LINK_RATE 0x0001 // Reg 47c6799d8aSAlexander von Gluck IV // Use DP_LINK_RATE_* for speed. 484185aa0cSAlexander von Gluck IV // DP Maximum Lane Count (0x2) 494185aa0cSAlexander von Gluck IV #define DP_MAX_LANE_COUNT 0x0002 // Reg 50*f6e7d9dfSJérôme Duval #define DP_MAX_LANE_COUNT_MASK 0x1f // Count 51*f6e7d9dfSJérôme Duval #define DP_ENHANCED_FRAME_CAP (1 << 7) // Bool, Rev 1.1 524185aa0cSAlexander von Gluck IV // DP Maximum Downspread (0x3) 534185aa0cSAlexander von Gluck IV #define DP_MAX_DOWNSPREAD 0x0003 // Reg 54*f6e7d9dfSJérôme Duval #define DP_MAX_DOWNSPREAD_0_5 (1 << 0) // Bool 55*f6e7d9dfSJérôme Duval #define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6) // Bool 564185aa0cSAlexander von Gluck IV // DP Number of Receiver Ports (0x4) 574185aa0cSAlexander von Gluck IV #define DP_NORP 0x0004 // Reg 58*f6e7d9dfSJérôme Duval #define DP_NORP_MASK 0x1 // Count 594185aa0cSAlexander von Gluck IV // DP Downstream Port Present (0x5) 60*f6e7d9dfSJérôme Duval #define DP_DOWNSTREAMPORT_PRESENT 0x0005 // Reg 61*f6e7d9dfSJérôme Duval #define DP_DWN_STRM_PORT_PRESENT (1 << 0) // Bool 62*f6e7d9dfSJérôme Duval #define DP_DWN_STRM_PORT_TYPE_MASK (3 << 1) // Mask 63*f6e7d9dfSJérôme Duval #define DP_DWN_STRM_PORT_TYPE_DP (0 << 1) // Value 64*f6e7d9dfSJérôme Duval #define DP_DWN_STRM_PORT_TYPE_ANALOG (1 << 1) // Value 65*f6e7d9dfSJérôme Duval #define DP_DWN_STRM_PORT_TYPE_TMDS (2 << 1) // Value 66*f6e7d9dfSJérôme Duval #define DP_DWN_STRM_PORT_TYPE_OTHER (3 << 1) // Value 67*f6e7d9dfSJérôme Duval #define DP_FORMAT_CONVERSION (1 << 3) // Bool 68*f6e7d9dfSJérôme Duval #define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4) // Bool 694185aa0cSAlexander von Gluck IV // DP Main Link Channel Coding (0x6) 70*f6e7d9dfSJérôme Duval #define DP_MAIN_LINK_CHANNEL_CODING_SET 0x0006 // Reg 71*f6e7d9dfSJérôme Duval #define DP_CAP_ANSI_8B10B (1 << 0) // Bool 724185aa0cSAlexander von Gluck IV // DP Downstream Port Count (0x7) (Only 1.1+) 73*f6e7d9dfSJérôme Duval #define DP_DOWN_STREAM_PORT_COUNT 0x0007 // Reg 74*f6e7d9dfSJérôme Duval #define DP_PORT_COUNT_MASK 0xf // Count 75*f6e7d9dfSJérôme Duval #define DP_OUI_SUPPORT (1 << 7) // Bool 764185aa0cSAlexander von Gluck IV // DP Port Capability 0 77*f6e7d9dfSJérôme Duval #define DP_RECEIVE_PORT_0_CAP_0 0x0008 // Reg 78*f6e7d9dfSJérôme Duval #define DP_RECEIVE_PORT_1_CAP_0 0x000a // Reg 79*f6e7d9dfSJérôme Duval #define DP_LOCAL_EDID_PRESENT (1 << 1) // Bool 80*f6e7d9dfSJérôme Duval #define DP_ASSOCIATED_TO_PRECEDING_PORT (1 << 2) // Bool 81*f6e7d9dfSJérôme Duval // DP Port Buffer Size 82*f6e7d9dfSJérôme Duval #define DP_RECEIVE_PORT_0_BUFFER_SIZE 0x0009 // Reg 83*f6e7d9dfSJérôme Duval #define DP_RECEIVE_PORT_1_BUFFER_SIZE 0x000b // Reg 844185aa0cSAlexander von Gluck IV // (value + 1) * 32 bytes per lane 854185aa0cSAlexander von Gluck IV 864185aa0cSAlexander von Gluck IV /* *** DPCD Link Configuration Field (0x0100) *** */ 874185aa0cSAlexander von Gluck IV /* *** VESA DisplayPort Standard, rev 1.1, p117 *** */ 884185aa0cSAlexander von Gluck IV 894185aa0cSAlexander von Gluck IV // DP Set Link Rate Per Lane (0x0100) 904185aa0cSAlexander von Gluck IV #define DP_LINK_RATE 0x0100 // Reg 914185aa0cSAlexander von Gluck IV #define DP_LINK_RATE_162 0x0006 // 1.62Ghz 924185aa0cSAlexander von Gluck IV #define DP_LINK_RATE_270 0x000A // 2.70Ghz 934185aa0cSAlexander von Gluck IV #define DP_LINK_RATE_540 0x0014 // 5.40Ghz 944185aa0cSAlexander von Gluck IV // DP Set Lane Count (0x0101) 954185aa0cSAlexander von Gluck IV #define DP_LANE_COUNT 0x0101 // Reg 96c6799d8aSAlexander von Gluck IV #define DP_LANE_COUNT_MASK (31 << 0) // Count 97c6799d8aSAlexander von Gluck IV #define DP_ENHANCED_FRAME_EN (1 << 7) // Bool, Rev 1.1 984185aa0cSAlexander von Gluck IV // DP Training Pattern (0x0102) 99*f6e7d9dfSJérôme Duval #define DP_TRAINING_PATTERN_SET 0x0102 // Reg 100*f6e7d9dfSJérôme Duval #define DP_TRAINING_PATTERN_MASK (3 << 0) // Mask 101*f6e7d9dfSJérôme Duval #define DP_TRAINING_PATTERN_DISABLE (0 << 0) // Value 102*f6e7d9dfSJérôme Duval #define DP_TRAINING_PATTERN_1 (1 << 0) // Value 103*f6e7d9dfSJérôme Duval #define DP_TRAINING_PATTERN_2 (2 << 0) // Value 104*f6e7d9dfSJérôme Duval #define DP_TRAINING_PATTERN_3 (3 << 0) // Value 105c6799d8aSAlexander von Gluck IV 106c6799d8aSAlexander von Gluck IV #define DP_TRAIN_QUAL_MASK (3 << 2) // Mask 107c6799d8aSAlexander von Gluck IV #define DP_TRAIN_QUAL_NONE (0 << 2) // Value 108c6799d8aSAlexander von Gluck IV #define DP_TRAIN_QUAL_D102 (1 << 2) // Value 109c6799d8aSAlexander von Gluck IV #define DP_TRAIN_QUAL_SYMB_ERR (2 << 2) // Value 110c6799d8aSAlexander von Gluck IV #define DP_TRAIN_QUAL_PRBS7 (3 << 2) // Value 111c6799d8aSAlexander von Gluck IV 112c6799d8aSAlexander von Gluck IV #define DP_TRAIN_CLOCK_RECOVER_EN (1 << 4) // Bool 113c6799d8aSAlexander von Gluck IV #define DP_TRAIN_SCRAMBLE_DI (1 << 5) // Bool (rev) 114c6799d8aSAlexander von Gluck IV #define DP_TRAIN_SYMBL_ERR_SEL_MASK (3 << 6) // Mask 115c6799d8aSAlexander von Gluck IV #define DP_TRAIN_SYMBL_ERR_SEL_BOTH (0 << 6) // Value 116c6799d8aSAlexander von Gluck IV #define DP_TRAIN_SYMBL_ERR_SEL_DISPARITY (1 << 6) // Value 117c6799d8aSAlexander von Gluck IV #define DP_TRAIN_SYMBL_ERR_SEL_SYMBOL (2 << 6) // Value 1184185aa0cSAlexander von Gluck IV // DP Training Lane n (0x0103 - 0x0106) 119*f6e7d9dfSJérôme Duval #define DP_TRAINING_LANE0_SET 0x0103 // Reg 120*f6e7d9dfSJérôme Duval #define DP_TRAINING_LANE1_SET 0x0104 // Reg 121*f6e7d9dfSJérôme Duval #define DP_TRAINING_LANE2_SET 0x0105 // Reg 122*f6e7d9dfSJérôme Duval #define DP_TRAINING_LANE3_SET 0x0106 // Reg 123c6799d8aSAlexander von Gluck IV 124c6799d8aSAlexander von Gluck IV #define DP_TRAIN_VCC_SWING_SHIFT (0 << 0) // Shift 125c6799d8aSAlexander von Gluck IV #define DP_TRAIN_VCC_SWING_MASK (3 << 0) // Mask 126c6799d8aSAlexander von Gluck IV #define DP_TRAIN_VCC_SWING_400 (0 << 0) // Value 127c6799d8aSAlexander von Gluck IV #define DP_TRAIN_VCC_SWING_600 (1 << 0) // Value 128c6799d8aSAlexander von Gluck IV #define DP_TRAIN_VCC_SWING_800 (2 << 0) // Value 129c6799d8aSAlexander von Gluck IV #define DP_TRAIN_VCC_SWING_1200 (3 << 0) // Value 130c6799d8aSAlexander von Gluck IV #define DP_TRAIN_MAX_SWING_EN (1 << 2) // Bool 131c6799d8aSAlexander von Gluck IV 132c6799d8aSAlexander von Gluck IV #define DP_TRAIN_PRE_EMPHASIS_SHIFT (3 << 0) // Shift 133c6799d8aSAlexander von Gluck IV #define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3) // Mask 134c6799d8aSAlexander von Gluck IV #define DP_TRAIN_PRE_EMPHASIS_0 (0 << 3) // Value 135c6799d8aSAlexander von Gluck IV #define DP_TRAIN_PRE_EMPHASIS_3_5 (1 << 3) // Value 136c6799d8aSAlexander von Gluck IV #define DP_TRAIN_PRE_EMPHASIS_6 (2 << 3) // Value 137c6799d8aSAlexander von Gluck IV #define DP_TRAIN_PRE_EMPHASIS_9_5 (3 << 3) // Value 138c6799d8aSAlexander von Gluck IV #define DP_TRAIN_MAX_EMPHASIS_EN (1 << 5) // Bool 1394185aa0cSAlexander von Gluck IV // DP Down-spread Control (0x0107) 14064dcb00fSAlexander von Gluck IV #define DP_DOWNSPREAD_CTRL 0x0107 // Reg 141c6799d8aSAlexander von Gluck IV #define DP_DOWNSPREAD_CTRL_FREQ_MASK (1 << 0) // Int 142c6799d8aSAlexander von Gluck IV #define DP_DOWNSPREAD_CTRL_AMP_EN (1 << 4) // Int 1434185aa0cSAlexander von Gluck IV // DP Main Link Channel Coding (0x0108) 1444185aa0cSAlexander von Gluck IV #define DP_MAIN_CHAN_CODE 0x0108 // Reg 145c6799d8aSAlexander von Gluck IV #define DP_MAIN_CHAN_CODE_ANSIX3_EN (1 << 0) // Bool 1464185aa0cSAlexander von Gluck IV 1474185aa0cSAlexander von Gluck IV /* *** DPCD Link / Sink Status Field (0x0200) *** */ 1484185aa0cSAlexander von Gluck IV /* *** VESA DisplayPort Standard, rev 1.1, p120 *** */ 1494185aa0cSAlexander von Gluck IV 1508dfc5dbbSAlexander von Gluck IV // DP Sink Count (0x0200) 1518dfc5dbbSAlexander von Gluck IV #define DP_SINK_COUNT 0x0200 // Reg 1528dfc5dbbSAlexander von Gluck IV #define DP_SINK_COUNT_MASK (63 << 0) // Mask 1538dfc5dbbSAlexander von Gluck IV #define DP_SINK_COUNT_CP_READY (1 << 6) // Bool 1548dfc5dbbSAlexander von Gluck IV // DP Service IRQ Vector (0x0201) 1558dfc5dbbSAlexander von Gluck IV #define DP_SINK_IRQ_VECTOR 0x0201 // Reg 1568dfc5dbbSAlexander von Gluck IV #define DP_SINK_IRQ_TEST_REQ (1 << 1) // Bool 1578dfc5dbbSAlexander von Gluck IV #define DP_SINK_IRQ_CP_IRQ (1 << 2) // Bool 1588dfc5dbbSAlexander von Gluck IV #define DP_SINK_IRQ_VENDOR (1 << 6) // Bool 1598dfc5dbbSAlexander von Gluck IV // DP Lane Status A B 1608dfc5dbbSAlexander von Gluck IV #define DP_LANE_STATUS_0_1 0x0202 // Reg 1618dfc5dbbSAlexander von Gluck IV #define DP_LANE_STATUS_2_3 0x0203 // Reg 1628dfc5dbbSAlexander von Gluck IV #define DP_LINK_STATUS_SIZE 6 // Size 1638dfc5dbbSAlexander von Gluck IV #define DP_LANE_STATUS_CR_DONE_A (1 << 0) // Bool 1648dfc5dbbSAlexander von Gluck IV #define DP_LANE_STATUS_CHEQ_DONE_A (1 << 1) // Bool 1658dfc5dbbSAlexander von Gluck IV #define DP_LANE_STATUS_SYMB_LOCK_A (1 << 2) // Bool 1668dfc5dbbSAlexander von Gluck IV #define DP_LANE_STATUS_CR_DONE_B (1 << 4) // Bool 1678dfc5dbbSAlexander von Gluck IV #define DP_LANE_STATUS_CHEQ_DONE_B (1 << 5) // Bool 1688dfc5dbbSAlexander von Gluck IV #define DP_LANE_STATUS_SYMB_LOCK_B (1 << 6) // Bool 1697f167d4fSAlexander von Gluck IV #define DP_LANE_STATUS_EQUALIZED_A (DP_LANE_STATUS_CR_DONE_A \ 1707f167d4fSAlexander von Gluck IV | DP_LANE_STATUS_CHEQ_DONE_A \ 1717f167d4fSAlexander von Gluck IV | DP_LANE_STATUS_SYMB_LOCK_A) 1727f167d4fSAlexander von Gluck IV #define DP_LANE_STATUS_EQUALIZED_B (DP_LANE_STATUS_CR_DONE_B \ 1737f167d4fSAlexander von Gluck IV | DP_LANE_STATUS_CHEQ_DONE_B \ 1747f167d4fSAlexander von Gluck IV | DP_LANE_STATUS_SYMB_LOCK_B) 1758dfc5dbbSAlexander von Gluck IV // DP Lane Align Status (0x0204) 176*f6e7d9dfSJérôme Duval #define DP_LANE_ALIGN_STATUS_UPDATED 0x0204 // Reg 177*f6e7d9dfSJérôme Duval #define DP_INTERLANE_ALIGN_DONE (1 << 0) // Bool 178*f6e7d9dfSJérôme Duval #define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6) // Bool 179*f6e7d9dfSJérôme Duval #define DP_LINK_STATUS_UPDATED (1 << 7) // Bool 1808dfc5dbbSAlexander von Gluck IV // DP Sink Status (0x0205) 1818dfc5dbbSAlexander von Gluck IV #define DP_SINK_STATUS 0x0205 // Reg 1828dfc5dbbSAlexander von Gluck IV #define DP_SINK_STATUS_IN_SYNC_0 (1 << 0) // Bool 1838dfc5dbbSAlexander von Gluck IV #define DP_SINK_STATUS_IN_SYNC_1 (1 << 1) // Bool 1848dfc5dbbSAlexander von Gluck IV // DP Adjust Request A B 1858dfc5dbbSAlexander von Gluck IV #define DP_ADJ_REQUEST_0_1 0x0206 // Reg 1868dfc5dbbSAlexander von Gluck IV #define DP_ADJ_REQUEST_2_3 0x0207 // Reg 1878dfc5dbbSAlexander von Gluck IV #define DP_ADJ_VCC_SWING_LANEA_SHIFT 0 // Shift 1888dfc5dbbSAlexander von Gluck IV #define DP_ADJ_VCC_SWING_LANEA_MASK (3 << 0) // Mask 1898dfc5dbbSAlexander von Gluck IV #define DP_ADJ_PRE_EMPHASIS_LANEA_SHIFT 2 // Shift 1908dfc5dbbSAlexander von Gluck IV #define DP_ADJ_PRE_EMPHASIS_LANEA_MASK (3 << 2) // Mask 1918dfc5dbbSAlexander von Gluck IV #define DP_ADJ_VCC_SWING_LANEB_SHIFT 4 // Shift 1928dfc5dbbSAlexander von Gluck IV #define DP_ADJ_VCC_SRING_LANEB_MASK (3 << 4) // Mask 1938dfc5dbbSAlexander von Gluck IV #define DP_ADJ_PRE_EMPHASIS_LANEB_SHIFT 6 // Shift 1948dfc5dbbSAlexander von Gluck IV #define DP_ADJ_PRE_EMPHASIS_LANEB_MASK (3 << 6) // Mask 1958dfc5dbbSAlexander von Gluck IV 1968dfc5dbbSAlexander von Gluck IV // TODO: 0x0210 - 0x0217 1974185aa0cSAlexander von Gluck IV 1984185aa0cSAlexander von Gluck IV /* *** DPCD Automated Self-testing Field (0x0218) *** */ 1994185aa0cSAlexander von Gluck IV /* *** VESA DisplayPort Standard, rev 1.1, p123 *** */ 2004185aa0cSAlexander von Gluck IV 2014185aa0cSAlexander von Gluck IV // TODO: Optional Field 2024185aa0cSAlexander von Gluck IV 2034185aa0cSAlexander von Gluck IV /* *** DPCD Source Device Specific Field (0x0300) *** */ 2044185aa0cSAlexander von Gluck IV /* *** VESA DisplayPort Standard, rev 1.1, p127 *** */ 2054185aa0cSAlexander von Gluck IV 2064185aa0cSAlexander von Gluck IV // TODO 2074185aa0cSAlexander von Gluck IV 2084185aa0cSAlexander von Gluck IV /* *** DPCD Sink Device Specific Field (0x0400) *** */ 2094185aa0cSAlexander von Gluck IV /* *** VESA DisplayPort Standard, rev 1.1, p127 *** */ 2104185aa0cSAlexander von Gluck IV 2114185aa0cSAlexander von Gluck IV // TODO 2124185aa0cSAlexander von Gluck IV 2134185aa0cSAlexander von Gluck IV /* *** DPCD Branch Device Specific Field (0x0500) *** */ 2144185aa0cSAlexander von Gluck IV /* *** VESA DisplayPort Standard, rev 1.1, p127 *** */ 2154185aa0cSAlexander von Gluck IV 2164185aa0cSAlexander von Gluck IV // TODO 2174185aa0cSAlexander von Gluck IV 2184185aa0cSAlexander von Gluck IV /* *** DPCD Sink Control Field (0x0600) *** */ 2194185aa0cSAlexander von Gluck IV /* *** VESA DisplayPort Standard, rev 1.1, p128 *** */ 2204185aa0cSAlexander von Gluck IV 2218dfc5dbbSAlexander von Gluck IV #define DP_SET_POWER 0x0600 // Reg 2228dfc5dbbSAlexander von Gluck IV #define DP_SET_POWER_D0 (1 << 0) // Value 2238dfc5dbbSAlexander von Gluck IV #define DP_SET_POWER_D3 (1 << 1) // Value 2244185aa0cSAlexander von Gluck IV 2254185aa0cSAlexander von Gluck IV /* *** DPCD Reserved (0x0700+) *** */ 2264185aa0cSAlexander von Gluck IV /* ****************************************************** */ 2274185aa0cSAlexander von Gluck IV 2284185aa0cSAlexander von Gluck IV 2294185aa0cSAlexander von Gluck IV #endif /* _DP_RAW_H */ 230