1 /* 2 Copyright 2007-2009 Haiku, Inc. All rights reserved. 3 Distributed under the terms of the MIT license. 4 5 Authors: 6 Gerald Zajac 2007-2009 7 */ 8 9 #ifndef DRIVERINTERFACE_H 10 #define DRIVERINTERFACE_H 11 12 13 #include <Accelerant.h> 14 #include <GraphicsDefs.h> 15 #include <Drivers.h> 16 #include <edid.h> 17 18 19 // This file contains info that is shared between the kernel driver and the 20 // accelerant, and info that is shared among the source files of the accelerant. 21 22 23 #define ENABLE_DEBUG_TRACE // if defined, turns on debug output to syslog 24 25 26 #define ARRAY_SIZE(a) (int(sizeof(a) / sizeof(a[0]))) // get number of elements in an array 27 28 struct Benaphore { 29 sem_id sem; 30 int32 count; 31 32 status_t Init(const char* name) 33 { 34 count = 0; 35 sem = create_sem(0, name); 36 return sem < 0 ? sem : B_OK; 37 } 38 39 status_t Acquire() 40 { 41 if (atomic_add(&count, 1) > 0) 42 return acquire_sem(sem); 43 return B_OK; 44 } 45 46 status_t Release() 47 { 48 if (atomic_add(&count, -1) > 1) 49 return release_sem(sem); 50 return B_OK; 51 } 52 53 void Delete() { delete_sem(sem); } 54 }; 55 56 57 enum { 58 ATI_GET_SHARED_DATA = B_DEVICE_OP_CODES_END + 123, 59 ATI_DEVICE_NAME, 60 ATI_GET_EDID, 61 ATI_RUN_INTERRUPTS, 62 ATI_SET_VESA_DISPLAY_MODE 63 }; 64 65 66 // Chip type numbers. These are used to group the chips into related 67 // groups. See table chipTable in driver.c 68 // Note that the order of the Mach64 chip types must not be changed because 69 // < or > comparisons of the chip types are made. They should be in the order 70 // of the evolution of the chips. 71 72 enum ChipType { 73 ATI_NONE = 0, 74 75 MACH64_264VT, 76 MACH64_264GT, 77 MACH64_264VTB, 78 MACH64_264GTB, 79 MACH64_264VT3, 80 MACH64_264GTDVD, 81 MACH64_264LT, 82 MACH64_264VT4, 83 MACH64_264GT2C, 84 MACH64_264GTPRO, 85 MACH64_264LTPRO, 86 MACH64_264XL, 87 MACH64_MOBILITY, 88 Mach64_ChipsEnd, // marks end of Mach64's 89 RAGE128_GL, 90 RAGE128_MOBILITY, 91 RAGE128_PRO_GL, 92 RAGE128_PRO_VR, 93 RAGE128_PRO_ULTRA, 94 RAGE128_VR, 95 }; 96 97 98 #define MACH64_FAMILY(chipType) (chipType < Mach64_ChipsEnd) 99 #define RAGE128_FAMILY(chipType) (chipType > Mach64_ChipsEnd) 100 101 102 103 enum MonitorType { 104 MT_VGA, // monitor with analog VGA interface 105 MT_DVI, // monitor with DVI interface 106 MT_LAPTOP // laptop video display 107 }; 108 109 110 // Mach64 parameters for computing register vaules and other parameters. 111 112 struct M64_Params { 113 // Clock parameters 114 uint8 clockNumberToProgram; // obtained from video BIOS 115 uint32 maxPixelClock; // obtained from video BIOS 116 int refFreq; // obtained from video BIOS 117 int refDivider; // obtained from video BIOS 118 uint8 xClkPostDivider; 119 uint8 xClkRefDivider; 120 uint16 xClkPageFaultDelay; 121 uint16 xClkMaxRASDelay; 122 uint16 displayFIFODepth; 123 uint16 displayLoopLatency; 124 uint8 vClkPostDivider; 125 uint8 vClkFeedbackDivider; 126 }; 127 128 129 struct R128_PLLParams { 130 uint16 reference_freq; 131 uint16 reference_div; 132 uint32 min_pll_freq; 133 uint32 max_pll_freq; 134 uint16 xclk; 135 }; 136 137 138 struct R128_RAMSpec { // All values in XCLKS 139 int memReadLatency; // Memory Read Latency 140 int memBurstLen; // Memory Burst Length 141 int rasToCasDelay; // RAS to CAS delay 142 int rasPercentage; // RAS percentage 143 int writeRecovery; // Write Recovery 144 int casLatency; // CAS Latency 145 int readToWriteDelay; // Read to Write Delay 146 int loopLatency; // Loop Latency 147 int loopFudgeFactor; // Add to memReadLatency to get loopLatency 148 char *name; 149 }; 150 151 152 struct VesaMode { 153 uint16 mode; // VESA mode number 154 uint16 width; 155 uint16 height; 156 uint8 bitsPerPixel; 157 }; 158 159 160 struct DisplayModeEx : display_mode { 161 uint8 bitsPerPixel; 162 uint16 bytesPerRow; // number of bytes in one line/row 163 }; 164 165 166 struct SharedInfo { 167 // Device ID info. 168 uint16 vendorID; // PCI vendor ID, from pci_info 169 uint16 deviceID; // PCI device ID, from pci_info 170 uint8 revision; // PCI device revsion, from pci_info 171 ChipType chipType; // indicates group in which chip belongs (a group has similar functionality) 172 char chipName[32]; // user recognizable name of chip 173 174 bool bAccelerantInUse; // true = accelerant has been initialized 175 bool bInterruptAssigned; // card has a useable interrupt assigned to it 176 177 sem_id vertBlankSem; // vertical blank semaphore; if < 0, there is no semaphore 178 179 // Memory mappings. 180 area_id regsArea; // area_id for the memory mapped registers. It will 181 // be cloned into accelerant's address space. 182 area_id videoMemArea; // video memory area_id. The addresses are shared with all teams. 183 void* videoMemAddr; // video memory addr as viewed from virtual memory 184 void* videoMemPCI; // video memory addr as viewed from the PCI bus (for DMA) 185 uint32 videoMemSize; // video memory size in bytes. 186 187 uint32 cursorOffset; // offset of cursor in video memory 188 uint32 frameBufferOffset; // offset of frame buffer in video memory 189 uint32 maxFrameBufferSize; // max available video memory for frame buffer 190 191 // Color spaces supported by current video chip/driver. 192 color_space colorSpaces[6]; 193 uint32 colorSpaceCount; // number of color spaces in array colorSpaces 194 195 // List of screen modes. 196 area_id modeArea; // area containing list of display modes the driver supports 197 uint32 modeCount; // number of display modes in the list 198 199 DisplayModeEx displayMode; // current display mode configuration 200 201 // List of VESA modes supported by current chip. 202 uint32 vesaModeTableOffset; // offset of table in shared info 203 uint32 vesaModeCount; 204 205 uint16 cursorHotX; // Cursor hot spot. Top left corner of the cursor 206 uint16 cursorHotY; // is 0,0 207 208 edid1_info edidInfo; 209 bool bHaveEDID; // true = EDID info from device is in edidInfo 210 211 Benaphore engineLock; // for serializing access to the acceleration engine 212 213 MonitorType displayType; 214 215 uint16 panelX; // laptop LCD width 216 uint16 panelY; // laptop LCD height 217 uint16 panelPowerDelay; 218 219 // Data members for Mach64 chips. 220 //------------------------------- 221 222 M64_Params m64Params; // parameters for Mach64 chips 223 224 // Data members for Rage128 chips. 225 //-------------------------------- 226 227 R128_RAMSpec r128MemSpec; // Rage128 memory timing spec's 228 R128_PLLParams r128PLLParams; // Rage128 PLL parameters from video BIOS ROM 229 230 uint32 r128_dpGuiMasterCntl; // flags for accelerated drawing 231 }; 232 233 234 #endif // DRIVERINTERFACE_H 235