1 /* 2 Copyright 2007-2011 Haiku, Inc. All rights reserved. 3 Distributed under the terms of the MIT license. 4 5 Authors: 6 Gerald Zajac 7 */ 8 9 #ifndef DRIVERINTERFACE_H 10 #define DRIVERINTERFACE_H 11 12 13 #include <Accelerant.h> 14 #include <GraphicsDefs.h> 15 #include <Drivers.h> 16 #include <edid.h> 17 #include <video_overlay.h> 18 19 20 // This file contains info that is shared between the kernel driver and the 21 // accelerant, and info that is shared among the source files of the accelerant. 22 23 24 #define ENABLE_DEBUG_TRACE // if defined, turns on debug output to syslog 25 26 27 #define ARRAY_SIZE(a) (int(sizeof(a) / sizeof(a[0]))) // get number of elements in an array 28 29 struct Benaphore { 30 sem_id sem; 31 int32 count; 32 33 status_t Init(const char* name) 34 { 35 count = 0; 36 sem = create_sem(0, name); 37 return sem < 0 ? sem : B_OK; 38 } 39 40 status_t Acquire() 41 { 42 if (atomic_add(&count, 1) > 0) 43 return acquire_sem(sem); 44 return B_OK; 45 } 46 47 status_t Release() 48 { 49 if (atomic_add(&count, -1) > 1) 50 return release_sem(sem); 51 return B_OK; 52 } 53 54 void Delete() { delete_sem(sem); } 55 }; 56 57 58 enum { 59 ATI_GET_SHARED_DATA = B_DEVICE_OP_CODES_END + 123, 60 ATI_DEVICE_NAME, 61 ATI_GET_EDID, 62 ATI_RUN_INTERRUPTS, 63 ATI_SET_VESA_DISPLAY_MODE 64 }; 65 66 67 // Chip type numbers. These are used to group the chips into related 68 // groups. See table chipTable in driver.c 69 // Note that the order of the Mach64 chip types must not be changed because 70 // < or > comparisons of the chip types are made. They should be in the order 71 // of the evolution of the chips. 72 73 enum ChipType { 74 ATI_NONE = 0, 75 76 MACH64_264VT, 77 MACH64_264GT, 78 MACH64_264VTB, 79 MACH64_264GTB, 80 MACH64_264VT3, 81 MACH64_264GTDVD, 82 MACH64_264LT, 83 MACH64_264VT4, 84 MACH64_264GT2C, 85 MACH64_264GTPRO, 86 MACH64_264LTPRO, 87 MACH64_264XL, 88 MACH64_MOBILITY, 89 Mach64_ChipsEnd, // marks end of Mach64's 90 RAGE128_GL, 91 RAGE128_MOBILITY, 92 RAGE128_PRO_GL, 93 RAGE128_PRO_VR, 94 RAGE128_PRO_ULTRA, 95 RAGE128_VR, 96 }; 97 98 99 #define MACH64_FAMILY(chipType) (chipType < Mach64_ChipsEnd) 100 #define RAGE128_FAMILY(chipType) (chipType > Mach64_ChipsEnd) 101 102 103 104 enum MonitorType { 105 MT_VGA, // monitor with analog VGA interface 106 MT_DVI, // monitor with DVI interface 107 MT_LAPTOP // laptop video display 108 }; 109 110 111 // Mach64 parameters for computing register vaules and other parameters. 112 113 struct M64_Params { 114 // Clock parameters 115 uint8 clockNumberToProgram; // obtained from video BIOS 116 uint32 maxPixelClock; // obtained from video BIOS 117 int refFreq; // obtained from video BIOS 118 int refDivider; // obtained from video BIOS 119 uint8 xClkPostDivider; 120 uint8 xClkRefDivider; 121 uint16 xClkPageFaultDelay; 122 uint16 xClkMaxRASDelay; 123 uint16 displayFIFODepth; 124 uint16 displayLoopLatency; 125 uint8 vClkPostDivider; 126 uint8 vClkFeedbackDivider; 127 }; 128 129 130 struct R128_PLLParams { 131 uint16 reference_freq; 132 uint16 reference_div; 133 uint32 min_pll_freq; 134 uint32 max_pll_freq; 135 uint16 xclk; 136 }; 137 138 139 struct R128_RAMSpec { // All values in XCLKS 140 int memReadLatency; // Memory Read Latency 141 int memBurstLen; // Memory Burst Length 142 int rasToCasDelay; // RAS to CAS delay 143 int rasPercentage; // RAS percentage 144 int writeRecovery; // Write Recovery 145 int casLatency; // CAS Latency 146 int readToWriteDelay; // Read to Write Delay 147 int loopLatency; // Loop Latency 148 int loopFudgeFactor; // Add to memReadLatency to get loopLatency 149 const char *name; 150 }; 151 152 153 struct VesaMode { 154 uint16 mode; // VESA mode number 155 uint16 width; 156 uint16 height; 157 uint8 bitsPerPixel; 158 }; 159 160 161 struct DisplayModeEx : display_mode { 162 uint8 bitsPerPixel; 163 uint16 bytesPerRow; // number of bytes in one line/row 164 }; 165 166 167 struct OverlayBuffer : overlay_buffer { 168 OverlayBuffer* nextBuffer; // pointer to next buffer in chain, NULL = none 169 uint32 size; // size of overlay buffer 170 }; 171 172 173 struct SharedInfo { 174 // Device ID info. 175 uint16 vendorID; // PCI vendor ID, from pci_info 176 uint16 deviceID; // PCI device ID, from pci_info 177 uint8 revision; // PCI device revsion, from pci_info 178 ChipType chipType; // indicates group in which chip belongs (a group has similar functionality) 179 char chipName[32]; // user recognizable name of chip 180 181 bool bAccelerantInUse; // true = accelerant has been initialized 182 bool bInterruptAssigned; // card has a useable interrupt assigned to it 183 184 sem_id vertBlankSem; // vertical blank semaphore; if < 0, there is no semaphore 185 186 // Memory mappings. 187 area_id regsArea; // area_id for the memory mapped registers. It will 188 // be cloned into accelerant's address space. 189 area_id videoMemArea; // video memory area_id. The addresses are shared with all teams. 190 addr_t videoMemAddr; // video memory addr as viewed from virtual memory 191 phys_addr_t videoMemPCI; // video memory addr as viewed from the PCI bus (for DMA) 192 uint32 videoMemSize; // video memory size in bytes. 193 194 uint32 cursorOffset; // offset of cursor in video memory 195 uint32 frameBufferOffset; // offset of frame buffer in video memory 196 uint32 maxFrameBufferSize; // max available video memory for frame buffer 197 198 // Color spaces supported by current video chip/driver. 199 color_space colorSpaces[6]; 200 uint32 colorSpaceCount; // number of color spaces in array colorSpaces 201 202 // List of screen modes. 203 area_id modeArea; // area containing list of display modes the driver supports 204 uint32 modeCount; // number of display modes in the list 205 206 DisplayModeEx displayMode; // current display mode configuration 207 208 // List of VESA modes supported by current chip. 209 uint32 vesaModeTableOffset; // offset of table in shared info 210 uint32 vesaModeCount; 211 212 uint16 cursorHotX; // Cursor hot spot. Top left corner of the cursor 213 uint16 cursorHotY; // is 0,0 214 215 edid1_info edidInfo; 216 bool bHaveEDID; // true = EDID info from device is in edidInfo 217 218 Benaphore engineLock; // for serializing access to the acceleration engine 219 Benaphore overlayLock; // for overlay operations 220 221 int32 overlayAllocated; // non-zero if overlay is allocated 222 uint32 overlayToken; 223 OverlayBuffer* overlayBuffer; // pointer to linked list of buffers; NULL = none 224 225 MonitorType displayType; 226 227 uint16 panelX; // laptop LCD width 228 uint16 panelY; // laptop LCD height 229 uint16 panelPowerDelay; 230 231 // Data members for Mach64 chips. 232 //------------------------------- 233 234 M64_Params m64Params; // parameters for Mach64 chips 235 236 // Data members for Rage128 chips. 237 //-------------------------------- 238 239 R128_RAMSpec r128MemSpec; // Rage128 memory timing spec's 240 R128_PLLParams r128PLLParams; // Rage128 PLL parameters from video BIOS ROM 241 242 uint32 r128_dpGuiMasterCntl; // flags for accelerated drawing 243 }; 244 245 246 #endif // DRIVERINTERFACE_H 247