1 /*- 2 * Copyright (c) 2003 Hidetoshi Shimokawa 3 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the acknowledgement as bellow: 16 * 17 * This product includes software developed by K. Kobayashi and H. Shimokawa 18 * 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: src/sys/dev/firewire/firewire.h,v 1.21 2007/04/24 12:15:05 simokawa Exp $ 35 * 36 */ 37 38 #ifndef _FIREWIRE_H 39 #define _FIREWIRE_H 1 40 #ifdef __HAIKU__ 41 #include <stdint.h> 42 #include <sys/ioccom.h> 43 #endif 44 45 #define DEV_DEF 0 46 #define DEV_DV 2 47 48 struct fw_isochreq { 49 unsigned char ch:6, 50 tag:2; 51 }; 52 53 struct fw_isobufreq { 54 struct fw_bufspec { 55 unsigned int nchunk; 56 unsigned int npacket; 57 unsigned int psize; 58 } tx, rx; 59 }; 60 61 struct fw_addr { 62 uint32_t hi; 63 uint32_t lo; 64 }; 65 66 struct fw_asybindreq { 67 struct fw_addr start; 68 unsigned long len; 69 }; 70 71 struct fw_reg_req_t { 72 uint32_t addr; 73 uint32_t data; 74 }; 75 76 #define MAXREC(x) (2 << (x)) 77 #define FWPMAX_S400 (2048 + 20) /* MAXREC plus space for control data */ 78 #define FWMAXQUEUE 128 79 80 #define FWLOCALBUS 0xffc0 81 82 #define FWTCODE_WREQQ 0 83 #define FWTCODE_WREQB 1 84 #define FWTCODE_WRES 2 85 #define FWTCODE_RREQQ 4 86 #define FWTCODE_RREQB 5 87 #define FWTCODE_RRESQ 6 88 #define FWTCODE_RRESB 7 89 #define FWTCODE_CYCS 8 90 #define FWTCODE_LREQ 9 91 #define FWTCODE_STREAM 0xa 92 #define FWTCODE_LRES 0xb 93 #define FWTCODE_PHY 0xe 94 95 #define FWRETRY_1 0 96 #define FWRETRY_X 1 97 #define FWRETRY_A 2 98 #define FWRETRY_B 3 99 100 #define FWRCODE_COMPLETE 0 101 #define FWRCODE_ER_CONFL 4 102 #define FWRCODE_ER_DATA 5 103 #define FWRCODE_ER_TYPE 6 104 #define FWRCODE_ER_ADDR 7 105 106 #define FWSPD_S100 0 107 #define FWSPD_S200 1 108 #define FWSPD_S400 2 109 110 #define FWP_TL_VALID (1 << 7) 111 112 struct fw_isohdr { 113 uint32_t hdr[1]; 114 }; 115 116 struct fw_asyhdr { 117 uint32_t hdr[4]; 118 }; 119 120 #if BYTE_ORDER == BIG_ENDIAN 121 #define BIT4x2(x,y) uint8_t x:4, y:4 122 #define BIT16x2(x,y) uint32_t x:16, y:16 123 #else 124 #define BIT4x2(x,y) uint8_t y:4, x:4 125 #define BIT16x2(x,y) uint32_t y:16, x:16 126 #endif 127 128 129 #if BYTE_ORDER == BIG_ENDIAN 130 #define COMMON_HDR(a,b,c,d) uint32_t a:16,b:8,c:4,d:4 131 #define COMMON_RES(a,b,c,d) uint32_t a:16,b:4,c:4,d:8 132 #else 133 #define COMMON_HDR(a,b,c,d) uint32_t d:4,c:4,b:8,a:16 134 #define COMMON_RES(a,b,c,d) uint32_t d:8,c:4,b:4,a:16 135 #endif 136 137 struct fw_pkt { 138 union { 139 uint32_t ld[0]; 140 struct { 141 COMMON_HDR(, , tcode, ); 142 } common; 143 struct { 144 COMMON_HDR(len, chtag, tcode, sy); 145 uint32_t payload[0]; 146 } stream; 147 struct { 148 COMMON_HDR(dst, tlrt, tcode, pri); 149 BIT16x2(src, ); 150 } hdr; 151 struct { 152 COMMON_HDR(dst, tlrt, tcode, pri); 153 BIT16x2(src, dest_hi); 154 uint32_t dest_lo; 155 } rreqq; 156 struct { 157 COMMON_HDR(dst, tlrt, tcode, pri); 158 COMMON_RES(src, rtcode, , ); 159 uint32_t :32; 160 } wres; 161 struct { 162 COMMON_HDR(dst, tlrt, tcode, pri); 163 BIT16x2(src, dest_hi); 164 uint32_t dest_lo; 165 BIT16x2(len, extcode); 166 } rreqb; 167 struct { 168 COMMON_HDR(dst, tlrt, tcode, pri); 169 BIT16x2(src, dest_hi); 170 uint32_t dest_lo; 171 uint32_t data; 172 } wreqq; 173 struct { 174 COMMON_HDR(dst, tlrt, tcode, pri); 175 BIT16x2(src, dest_hi); 176 uint32_t dest_lo; 177 uint32_t data; 178 } cyc; 179 struct { 180 COMMON_HDR(dst, tlrt, tcode, pri); 181 COMMON_RES(src, rtcode, , ); 182 uint32_t :32; 183 uint32_t data; 184 } rresq; 185 struct { 186 COMMON_HDR(dst, tlrt, tcode, pri); 187 BIT16x2(src, dest_hi); 188 uint32_t dest_lo; 189 BIT16x2(len, extcode); 190 uint32_t payload[0]; 191 } wreqb; 192 struct { 193 COMMON_HDR(dst, tlrt, tcode, pri); 194 BIT16x2(src, dest_hi); 195 uint32_t dest_lo; 196 BIT16x2(len, extcode); 197 uint32_t payload[0]; 198 } lreq; 199 struct { 200 COMMON_HDR(dst, tlrt, tcode, pri); 201 COMMON_RES(src, rtcode, , ); 202 uint32_t :32; 203 BIT16x2(len, extcode); 204 uint32_t payload[0]; 205 } rresb; 206 struct { 207 COMMON_HDR(dst, tlrt, tcode, pri); 208 COMMON_RES(src, rtcode, , ); 209 uint32_t :32; 210 BIT16x2(len, extcode); 211 uint32_t payload[0]; 212 } lres; 213 } mode; 214 }; 215 216 /* 217 * Response code (rtcode) 218 */ 219 /* The node has successfully completed the command. */ 220 #define RESP_CMP 0 221 /* A resource conflict was detected. The request may be retried. */ 222 #define RESP_CONFLICT_ERROR 4 223 /* Hardware error, data is unavailable. */ 224 #define RESP_DATA_ERROR 5 225 /* A field in the request packet header was set to an unsupported or incorrect 226 * value, or an invalid transaction was attempted (e.g., a write to a read-only 227 * address). */ 228 #define RESP_TYPE_ERROR 6 229 /* The destination offset field in the request was set to an address not 230 * accessible in the destination node. */ 231 #define RESP_ADDRESS_ERROR 7 232 233 /* 234 * Extended transaction code (extcode) 235 */ 236 #define EXTCODE_MASK_SWAP 1 237 #define EXTCODE_CMP_SWAP 2 238 #define EXTCODE_FETCH_ADD 3 239 #define EXTCODE_LITTLE_ADD 4 240 #define EXTCODE_BOUNDED_ADD 5 241 #define EXTCODE_WRAP_ADD 6 242 243 struct fw_eui64 { 244 uint32_t hi, lo; 245 }; 246 #define FW_EUI64_BYTE(eui, x) \ 247 ((((x)<4)? \ 248 ((eui)->hi >> (8*(3-(x)))): \ 249 ((eui)->lo >> (8*(7-(x)))) \ 250 ) & 0xff) 251 #define FW_EUI64_EQUAL(x, y) \ 252 ((x).hi == (y).hi && (x).lo == (y).lo) 253 254 struct fw_asyreq { 255 struct fw_asyreq_t{ 256 unsigned char sped; 257 unsigned int type; 258 #define FWASREQNODE 0 259 #define FWASREQEUI 1 260 #define FWASRESTL 2 261 #define FWASREQSTREAM 3 262 unsigned short len; 263 union { 264 struct fw_eui64 eui; 265 }dst; 266 }req; 267 struct fw_pkt pkt; 268 uint32_t data[512]; 269 }; 270 271 struct fw_devinfo { 272 struct fw_eui64 eui; 273 uint16_t dst; 274 uint16_t status; 275 }; 276 277 #define FW_MAX_DEVLST 70 278 struct fw_devlstreq { 279 uint16_t n; 280 uint16_t info_len; 281 struct fw_devinfo dev[FW_MAX_DEVLST]; 282 }; 283 284 #define FW_SELF_ID_PORT_CONNECTED_TO_CHILD 3 285 #define FW_SELF_ID_PORT_CONNECTED_TO_PARENT 2 286 #define FW_SELF_ID_PORT_NOT_CONNECTED 1 287 #define FW_SELF_ID_PORT_NOT_EXISTS 0 288 #if BYTE_ORDER == BIG_ENDIAN 289 union fw_self_id { 290 struct { 291 uint32_t id:2, 292 phy_id:6, 293 sequel:1, 294 link_active:1, 295 gap_count:6, 296 phy_speed:2, 297 phy_delay:2, 298 contender:1, 299 power_class:3, 300 port0:2, 301 port1:2, 302 port2:2, 303 initiated_reset:1, 304 more_packets:1; 305 } p0; 306 struct { 307 uint32_t 308 id:2, 309 phy_id:6, 310 sequel:1, 311 sequence_num:3, 312 :2, 313 porta:2, 314 portb:2, 315 portc:2, 316 portd:2, 317 porte:2, 318 portf:2, 319 portg:2, 320 porth:2, 321 :1, 322 more_packets:1; 323 } p1; 324 }; 325 #else 326 union fw_self_id { 327 struct { 328 uint32_t more_packets:1, 329 initiated_reset:1, 330 port2:2, 331 port1:2, 332 port0:2, 333 power_class:3, 334 contender:1, 335 phy_delay:2, 336 phy_speed:2, 337 gap_count:6, 338 link_active:1, 339 sequel:1, 340 phy_id:6, 341 id:2; 342 } p0; 343 struct { 344 uint32_t more_packets:1, 345 reserved1:1, 346 porth:2, 347 portg:2, 348 portf:2, 349 porte:2, 350 portd:2, 351 portc:2, 352 portb:2, 353 porta:2, 354 reserved2:2, 355 sequence_num:3, 356 sequel:1, 357 phy_id:6, 358 id:2; 359 } p1; 360 }; 361 #endif 362 363 364 struct fw_topology_map { 365 uint32_t crc:16, 366 crc_len:16; 367 uint32_t generation; 368 uint32_t self_id_count:16, 369 node_count:16; 370 union fw_self_id self_id[4*64]; 371 }; 372 373 struct fw_speed_map { 374 uint32_t crc:16, 375 crc_len:16; 376 uint32_t generation; 377 uint8_t speed[64][64]; 378 }; 379 380 struct fw_crom_buf { 381 struct fw_eui64 eui; 382 uint32_t len; 383 void *ptr; 384 }; 385 386 /* 387 * FireWire specific system requests. 388 */ 389 #define FW_SSTBUF _IOWR('S', 86, struct fw_isobufreq) 390 #define FW_GSTBUF _IOWR('S', 87, struct fw_isobufreq) 391 #define FW_SRSTREAM _IOWR('S', 88, struct fw_isochreq) 392 #define FW_GRSTREAM _IOWR('S', 89, struct fw_isochreq) 393 #define FW_STSTREAM _IOWR('S', 90, struct fw_isochreq) 394 #define FW_GTSTREAM _IOWR('S', 91, struct fw_isochreq) 395 396 #define FW_ASYREQ _IOWR('S', 92, struct fw_asyreq) 397 #define FW_IBUSRST _IOR('S', 1, unsigned int) 398 #define FW_GDEVLST _IOWR('S', 2, struct fw_devlstreq) 399 #define FW_SBINDADDR _IOWR('S', 3, struct fw_asybindreq) 400 #define FW_CBINDADDR _IOWR('S', 4, struct fw_asybindreq) 401 #define FW_GTPMAP _IOR('S', 5, struct fw_topology_map) 402 #define FW_GCROM _IOWR('S', 7, struct fw_crom_buf) 403 404 #define FW_SDEUI64 _IOW('S', 20, struct fw_eui64) 405 #define FW_GDEUI64 _IOR('S', 21, struct fw_eui64) 406 407 #define FWOHCI_RDREG _IOWR('S', 80, struct fw_reg_req_t) 408 #define FWOHCI_WRREG _IOWR('S', 81, struct fw_reg_req_t) 409 #define FWOHCI_RDPHYREG _IOWR('S', 82, struct fw_reg_req_t) 410 #define FWOHCI_WRPHYREG _IOWR('S', 83, struct fw_reg_req_t) 411 412 #define DUMPDMA _IOWR('S', 82, uint32_t) 413 414 #ifdef _KERNEL 415 416 #define FWMAXNDMA 0x100 /* 8 bits DMA channel id. in device No. */ 417 418 #ifndef __HAIKU__ 419 #if defined(__DragonFly__) || __FreeBSD_version < 500000 420 #define dev2unit(x) ((minor(x) & 0xff) | (minor(x) >> 8)) 421 #define unit2minor(x) (((x) & 0xff) | (((x) << 8) & ~0xffff)) 422 #endif 423 424 #define MAKEMINOR(f, u, s) \ 425 unit2minor((f) | (((u) & 0xff) << 8) | (s & 0xff)) 426 #define DEV2UNIT(x) ((dev2unit(x) & 0xff00) >> 8) 427 #define DEV2SUB(x) (dev2unit(x) & 0xff) 428 429 #define FWMEM_FLAG 0x10000 430 #define DEV_FWMEM(x) (dev2unit(x) & FWMEM_FLAG) 431 #endif /* __HAIKU__ */ 432 #endif 433 #ifdef __HAIKU__ 434 #define EX_NOINPUT 66 435 #define EX_USAGE 64 436 #endif /* __HAIKU__*/ 437 #endif 438