1 /*- 2 * Copyright (c) 2004-2005 David Schultz <das@FreeBSD.ORG> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #ifndef _FENV_H_ 30 #define _FENV_H_ 31 32 #include <stdint.h> 33 #include <sys/cdefs.h> 34 #include <sys/types.h> 35 36 typedef uint32_t fenv_t; 37 typedef uint32_t fexcept_t; 38 39 /* Exception flags */ 40 #define FE_INEXACT 0x02000000 41 #define FE_DIVBYZERO 0x04000000 42 #define FE_UNDERFLOW 0x08000000 43 #define FE_OVERFLOW 0x10000000 44 #define FE_INVALID 0x20000000 /* all types of invalid FP ops */ 45 46 /* 47 * The PowerPC architecture has extra invalid flags that indicate the 48 * specific type of invalid operation occurred. These flags may be 49 * tested, set, and cleared---but not masked---separately. All of 50 * these bits are cleared when FE_INVALID is cleared, but only 51 * FE_VXSOFT is set when FE_INVALID is explicitly set in software. 52 */ 53 #define FE_VXCVI 0x00000100 /* invalid integer convert */ 54 #define FE_VXSQRT 0x00000200 /* square root of a negative */ 55 #define FE_VXSOFT 0x00000400 /* software-requested exception */ 56 #define FE_VXVC 0x00080000 /* ordered comparison involving NaN */ 57 #define FE_VXIMZ 0x00100000 /* inf * 0 */ 58 #define FE_VXZDZ 0x00200000 /* 0 / 0 */ 59 #define FE_VXIDI 0x00400000 /* inf / inf */ 60 #define FE_VXISI 0x00800000 /* inf - inf */ 61 #define FE_VXSNAN 0x01000000 /* operation on a signalling NaN */ 62 #define FE_ALL_INVALID (FE_VXCVI | FE_VXSQRT | FE_VXSOFT | FE_VXVC | \ 63 FE_VXIMZ | FE_VXZDZ | FE_VXIDI | FE_VXISI | \ 64 FE_VXSNAN | FE_INVALID) 65 #define FE_ALL_EXCEPT (FE_DIVBYZERO | FE_INEXACT | \ 66 FE_ALL_INVALID | FE_OVERFLOW | FE_UNDERFLOW) 67 68 /* Rounding modes */ 69 #define FE_TONEAREST 0x0000 70 #define FE_TOWARDZERO 0x0001 71 #define FE_UPWARD 0x0002 72 #define FE_DOWNWARD 0x0003 73 #define _ROUND_MASK (FE_TONEAREST | FE_DOWNWARD | \ 74 FE_UPWARD | FE_TOWARDZERO) 75 76 __BEGIN_DECLS 77 78 /* Default floating-point environment */ 79 extern const fenv_t __fe_dfl_env; 80 #define FE_DFL_ENV (&__fe_dfl_env) 81 82 /* We need to be able to map status flag positions to mask flag positions */ 83 #define _FPUSW_SHIFT 22 84 #define _ENABLE_MASK ((FE_DIVBYZERO | FE_INEXACT | FE_INVALID | \ 85 FE_OVERFLOW | FE_UNDERFLOW) >> _FPUSW_SHIFT) 86 87 #ifndef _SOFT_FLOAT 88 #define __mffs(__env) __asm __volatile("mffs %0" : "=f" (*(__env))) 89 #define __mtfsf(__env) __asm __volatile("mtfsf 255,%0" : : "f" (__env)) 90 #else 91 #define __mffs(__env) 92 #define __mtfsf(__env) 93 #endif 94 95 union __fpscr { 96 double __d; 97 struct { 98 uint32_t __junk; 99 fenv_t __reg; 100 } __bits; 101 }; 102 103 static __inline int 104 feclearexcept(int __excepts) 105 { 106 union __fpscr __r; 107 108 if (__excepts & FE_INVALID) 109 __excepts |= FE_ALL_INVALID; 110 __mffs(&__r.__d); 111 __r.__bits.__reg &= ~__excepts; 112 __mtfsf(__r.__d); 113 return (0); 114 } 115 116 static __inline int 117 fegetexceptflag(fexcept_t *__flagp, int __excepts) 118 { 119 union __fpscr __r; 120 121 __mffs(&__r.__d); 122 *__flagp = __r.__bits.__reg & __excepts; 123 return (0); 124 } 125 126 static __inline int 127 fesetexceptflag(const fexcept_t *__flagp, int __excepts) 128 { 129 union __fpscr __r; 130 131 if (__excepts & FE_INVALID) 132 __excepts |= FE_ALL_EXCEPT; 133 __mffs(&__r.__d); 134 __r.__bits.__reg &= ~__excepts; 135 __r.__bits.__reg |= *__flagp & __excepts; 136 __mtfsf(__r.__d); 137 return (0); 138 } 139 140 static __inline int 141 feraiseexcept(int __excepts) 142 { 143 union __fpscr __r; 144 145 if (__excepts & FE_INVALID) 146 __excepts |= FE_VXSOFT; 147 __mffs(&__r.__d); 148 __r.__bits.__reg |= __excepts; 149 __mtfsf(__r.__d); 150 return (0); 151 } 152 153 static __inline int 154 fetestexcept(int __excepts) 155 { 156 union __fpscr __r; 157 158 __mffs(&__r.__d); 159 return (__r.__bits.__reg & __excepts); 160 } 161 162 static __inline int 163 fegetround(void) 164 { 165 union __fpscr __r; 166 167 __mffs(&__r.__d); 168 return (__r.__bits.__reg & _ROUND_MASK); 169 } 170 171 static __inline int 172 fesetround(int __round) 173 { 174 union __fpscr __r; 175 176 if (__round & ~_ROUND_MASK) 177 return (-1); 178 __mffs(&__r.__d); 179 __r.__bits.__reg &= ~_ROUND_MASK; 180 __r.__bits.__reg |= __round; 181 __mtfsf(__r.__d); 182 return (0); 183 } 184 185 static __inline int 186 fegetenv(fenv_t *__envp) 187 { 188 union __fpscr __r; 189 190 __mffs(&__r.__d); 191 *__envp = __r.__bits.__reg; 192 return (0); 193 } 194 195 static __inline int 196 feholdexcept(fenv_t *__envp) 197 { 198 union __fpscr __r; 199 200 __mffs(&__r.__d); 201 *__envp = __r.__d; 202 __r.__bits.__reg &= ~(FE_ALL_EXCEPT | _ENABLE_MASK); 203 __mtfsf(__r.__d); 204 return (0); 205 } 206 207 static __inline int 208 fesetenv(const fenv_t *__envp) 209 { 210 union __fpscr __r; 211 212 __r.__bits.__reg = *__envp; 213 __mtfsf(__r.__d); 214 return (0); 215 } 216 217 static __inline int 218 feupdateenv(const fenv_t *__envp) 219 { 220 union __fpscr __r; 221 222 __mffs(&__r.__d); 223 __r.__bits.__reg &= FE_ALL_EXCEPT; 224 __r.__bits.__reg |= *__envp; 225 __mtfsf(__r.__d); 226 return (0); 227 } 228 229 #if __BSD_VISIBLE 230 231 static __inline int 232 feenableexcept(int __mask) 233 { 234 union __fpscr __r; 235 fenv_t __oldmask; 236 237 __mffs(&__r.__d); 238 __oldmask = __r.__bits.__reg; 239 __r.__bits.__reg |= (__mask & FE_ALL_EXCEPT) >> _FPUSW_SHIFT; 240 __mtfsf(__r.__d); 241 return ((__oldmask & _ENABLE_MASK) << _FPUSW_SHIFT); 242 } 243 244 static __inline int 245 fedisableexcept(int __mask) 246 { 247 union __fpscr __r; 248 fenv_t __oldmask; 249 250 __mffs(&__r.__d); 251 __oldmask = __r.__bits.__reg; 252 __r.__bits.__reg &= ~((__mask & FE_ALL_EXCEPT) >> _FPUSW_SHIFT); 253 __mtfsf(__r.__d); 254 return ((__oldmask & _ENABLE_MASK) << _FPUSW_SHIFT); 255 } 256 257 static __inline int 258 fegetexcept(void) 259 { 260 union __fpscr __r; 261 262 __mffs(&__r.__d); 263 return ((__r.__bits.__reg & _ENABLE_MASK) << _FPUSW_SHIFT); 264 } 265 266 #endif /* __BSD_VISIBLE */ 267 268 __END_DECLS 269 270 #endif /* !_FENV_H_ */ 271