1 /*- 2 * Copyright (c) 2004-2005 David Schultz <das@FreeBSD.ORG> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #ifndef _FENV_H_ 30 #define _FENV_H_ 31 32 #include <sys/types.h> 33 #include <SupportDefs.h> 34 35 typedef uint32 fenv_t; 36 typedef uint32 fexcept_t; 37 38 /* Exception flags */ 39 #define FE_INEXACT 0x02000000 40 #define FE_DIVBYZERO 0x04000000 41 #define FE_UNDERFLOW 0x08000000 42 #define FE_OVERFLOW 0x10000000 43 #define FE_INVALID 0x20000000 /* all types of invalid FP ops */ 44 45 /* 46 * The PowerPC architecture has extra invalid flags that indicate the 47 * specific type of invalid operation occurred. These flags may be 48 * tested, set, and cleared---but not masked---separately. All of 49 * these bits are cleared when FE_INVALID is cleared, but only 50 * FE_VXSOFT is set when FE_INVALID is explicitly set in software. 51 */ 52 #define FE_VXCVI 0x00000100 /* invalid integer convert */ 53 #define FE_VXSQRT 0x00000200 /* square root of a negative */ 54 #define FE_VXSOFT 0x00000400 /* software-requested exception */ 55 #define FE_VXVC 0x00080000 /* ordered comparison involving NaN */ 56 #define FE_VXIMZ 0x00100000 /* inf * 0 */ 57 #define FE_VXZDZ 0x00200000 /* 0 / 0 */ 58 #define FE_VXIDI 0x00400000 /* inf / inf */ 59 #define FE_VXISI 0x00800000 /* inf - inf */ 60 #define FE_VXSNAN 0x01000000 /* operation on a signalling NaN */ 61 #define FE_ALL_INVALID (FE_VXCVI | FE_VXSQRT | FE_VXSOFT | FE_VXVC | \ 62 FE_VXIMZ | FE_VXZDZ | FE_VXIDI | FE_VXISI | \ 63 FE_VXSNAN | FE_INVALID) 64 #define FE_ALL_EXCEPT (FE_DIVBYZERO | FE_INEXACT | \ 65 FE_ALL_INVALID | FE_OVERFLOW | FE_UNDERFLOW) 66 67 /* Rounding modes */ 68 #define FE_TONEAREST 0x0000 69 #define FE_TOWARDZERO 0x0001 70 #define FE_UPWARD 0x0002 71 #define FE_DOWNWARD 0x0003 72 #define _ROUND_MASK (FE_TONEAREST | FE_DOWNWARD | \ 73 FE_UPWARD | FE_TOWARDZERO) 74 75 __BEGIN_DECLS 76 77 /* Default floating-point environment */ 78 extern const fenv_t __fe_dfl_env; 79 #define FE_DFL_ENV (&__fe_dfl_env) 80 81 /* We need to be able to map status flag positions to mask flag positions */ 82 #define _FPUSW_SHIFT 22 83 #define _ENABLE_MASK ((FE_DIVBYZERO | FE_INEXACT | FE_INVALID | \ 84 FE_OVERFLOW | FE_UNDERFLOW) >> _FPUSW_SHIFT) 85 86 #ifndef _SOFT_FLOAT 87 #define __mffs(__env) __asm __volatile("mffs %0" : "=f" (*(__env))) 88 #define __mtfsf(__env) __asm __volatile("mtfsf 255,%0" : : "f" (__env)) 89 #else 90 #define __mffs(__env) 91 #define __mtfsf(__env) 92 #endif 93 94 union __fpscr { 95 double __d; 96 struct { 97 __uint32_t __junk; 98 fenv_t __reg; 99 } __bits; 100 }; 101 102 static __inline int 103 feclearexcept(int __excepts) 104 { 105 union __fpscr __r; 106 107 if (__excepts & FE_INVALID) 108 __excepts |= FE_ALL_INVALID; 109 __mffs(&__r.__d); 110 __r.__bits.__reg &= ~__excepts; 111 __mtfsf(__r.__d); 112 return (0); 113 } 114 115 static __inline int 116 fegetexceptflag(fexcept_t *__flagp, int __excepts) 117 { 118 union __fpscr __r; 119 120 __mffs(&__r.__d); 121 *__flagp = __r.__bits.__reg & __excepts; 122 return (0); 123 } 124 125 static __inline int 126 fesetexceptflag(const fexcept_t *__flagp, int __excepts) 127 { 128 union __fpscr __r; 129 130 if (__excepts & FE_INVALID) 131 __excepts |= FE_ALL_EXCEPT; 132 __mffs(&__r.__d); 133 __r.__bits.__reg &= ~__excepts; 134 __r.__bits.__reg |= *__flagp & __excepts; 135 __mtfsf(__r.__d); 136 return (0); 137 } 138 139 static __inline int 140 feraiseexcept(int __excepts) 141 { 142 union __fpscr __r; 143 144 if (__excepts & FE_INVALID) 145 __excepts |= FE_VXSOFT; 146 __mffs(&__r.__d); 147 __r.__bits.__reg |= __excepts; 148 __mtfsf(__r.__d); 149 return (0); 150 } 151 152 static __inline int 153 fetestexcept(int __excepts) 154 { 155 union __fpscr __r; 156 157 __mffs(&__r.__d); 158 return (__r.__bits.__reg & __excepts); 159 } 160 161 static __inline int 162 fegetround(void) 163 { 164 union __fpscr __r; 165 166 __mffs(&__r.__d); 167 return (__r.__bits.__reg & _ROUND_MASK); 168 } 169 170 static __inline int 171 fesetround(int __round) 172 { 173 union __fpscr __r; 174 175 if (__round & ~_ROUND_MASK) 176 return (-1); 177 __mffs(&__r.__d); 178 __r.__bits.__reg &= ~_ROUND_MASK; 179 __r.__bits.__reg |= __round; 180 __mtfsf(__r.__d); 181 return (0); 182 } 183 184 static __inline int 185 fegetenv(fenv_t *__envp) 186 { 187 union __fpscr __r; 188 189 __mffs(&__r.__d); 190 *__envp = __r.__bits.__reg; 191 return (0); 192 } 193 194 static __inline int 195 feholdexcept(fenv_t *__envp) 196 { 197 union __fpscr __r; 198 199 __mffs(&__r.__d); 200 *__envp = __r.__d; 201 __r.__bits.__reg &= ~(FE_ALL_EXCEPT | _ENABLE_MASK); 202 __mtfsf(__r.__d); 203 return (0); 204 } 205 206 static __inline int 207 fesetenv(const fenv_t *__envp) 208 { 209 union __fpscr __r; 210 211 __r.__bits.__reg = *__envp; 212 __mtfsf(__r.__d); 213 return (0); 214 } 215 216 static __inline int 217 feupdateenv(const fenv_t *__envp) 218 { 219 union __fpscr __r; 220 221 __mffs(&__r.__d); 222 __r.__bits.__reg &= FE_ALL_EXCEPT; 223 __r.__bits.__reg |= *__envp; 224 __mtfsf(__r.__d); 225 return (0); 226 } 227 228 #if __BSD_VISIBLE 229 230 static __inline int 231 feenableexcept(int __mask) 232 { 233 union __fpscr __r; 234 fenv_t __oldmask; 235 236 __mffs(&__r.__d); 237 __oldmask = __r.__bits.__reg; 238 __r.__bits.__reg |= (__mask & FE_ALL_EXCEPT) >> _FPUSW_SHIFT; 239 __mtfsf(__r.__d); 240 return ((__oldmask & _ENABLE_MASK) << _FPUSW_SHIFT); 241 } 242 243 static __inline int 244 fedisableexcept(int __mask) 245 { 246 union __fpscr __r; 247 fenv_t __oldmask; 248 249 __mffs(&__r.__d); 250 __oldmask = __r.__bits.__reg; 251 __r.__bits.__reg &= ~((__mask & FE_ALL_EXCEPT) >> _FPUSW_SHIFT); 252 __mtfsf(__r.__d); 253 return ((__oldmask & _ENABLE_MASK) << _FPUSW_SHIFT); 254 } 255 256 static __inline int 257 fegetexcept(void) 258 { 259 union __fpscr __r; 260 261 __mffs(&__r.__d); 262 return ((__r.__bits.__reg & _ENABLE_MASK) << _FPUSW_SHIFT); 263 } 264 265 #endif /* __BSD_VISIBLE */ 266 267 __END_DECLS 268 269 #endif /* !_FENV_H_ */ 270